From patchwork Thu Dec 7 07:06:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751304 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="pfhuARPm" Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 559FAD7F for ; Wed, 6 Dec 2023 23:08:04 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-54c1cd8d239so754013a12.0 for ; Wed, 06 Dec 2023 23:08:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701932883; x=1702537683; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bUZ+Xi6iPmzuyCXXhpAA62gGUIVrLESrpvXoWFTaEuQ=; b=pfhuARPm3GVHnoU/4zDsTaU9G0Nrv9BxUZo/odlaf10z7EsmErfaRLzJXlSI3yXK0y 2TXrP4VEB5/otvxhuWEU7U7+eOeerlhImW+7gf7KcpIBbDPLJYau3t8obFTEiOi5XgsU GjOi2aLjbVjagj3aupFMbcNlwpEBrn9EBJqigBYTSgTvXUzS5M+0UtEXo0ZNnaoYhkyt tWOP7PRdLSSM1nGDse237gAV+7JqI+BFV7QJrHAG+N+0MmdPjB0e15UPQvPWwCh+k3Ub 9I6jdqTis/NwQqm5T/f38nYjwhT82CvsJGNscZtEM8Qd5hcc/CInsziPy6gWSYVxZAti uvOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701932883; x=1702537683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bUZ+Xi6iPmzuyCXXhpAA62gGUIVrLESrpvXoWFTaEuQ=; b=fOnrW/wExOS8TAQ/1oXULLRzJlzIMrF0KvxwhCVW56KZZz8tbpF/qO6NSdpeSACXdg m3Jg49IM3dXG7j6Ua52p8DFAo5V6jnWOvHdUDk9sO4pFTpJgY4X313ekus/80jbDva8d w8S5R11uIOvGWj1rm4HcpiPeZz2xE5Yq5RuNfqMZhdeNUqDSv908IwSQvUVNpL5LZTu0 JJnF3tMu8/Sxn3hz0VpzJK2EdQLxbxXjYBISub+BMdm9JHJJvzcc6eiSwpFJzHjQ+uR0 52phC7PWoNY5K5tb0t9TAgvy7BcTbY0nt3aJau51jkcG65mEEB+XsVk4nv80QCH3XL62 qEGg== X-Gm-Message-State: AOJu0YzoWXu6Rz1pqupcukHbisPHEAMRzVJO/FKeVPdQ2PlYYSkQh8/Z C768O6N9Wuwy1zg8m7nIwU7kvQ== X-Google-Smtp-Source: AGHT+IFYgHoezyMBS5pVMBDpau8vEgCGmmvXZ2I9QTiAtdjmWuM1kvPNgWs04XfPEI5GdV69KGuAkA== X-Received: by 2002:a50:8ad8:0:b0:54c:d1d5:7682 with SMTP id k24-20020a508ad8000000b0054cd1d57682mr523483edk.22.1701932882708; Wed, 06 Dec 2023 23:08:02 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:02 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 01/11] clk: renesas: rzg2l-cpg: Check reset monitor registers Date: Thu, 7 Dec 2023 09:06:50 +0200 Message-Id: <20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset monitor registers need to be interrogated when the reset signals are toggled (chapters "Procedures for Supplying and Stopping Reset Signals" and "Procedure for Activating Modules"). Without this, there is a chance that different modules (e.g., Ethernet) to not be ready after their reset signal is toggled, leading to failures (on probe or resume from deep sleep states). The same indications are available for RZ/V2M for TYPE-B reset controls. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") Signed-off-by: Claudiu Beznea --- Changes in v2: - adapted for CPG versions with monbit (e.g., RZ/V2M) - added a fixes tag for RZ/V2M - fixed typos in commit description drivers/clk/renesas/rzg2l-cpg.c | 59 ++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3189c3167ba8..1424fe78f09f 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1416,12 +1416,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); const struct rzg2l_cpg_info *info = priv->info; unsigned int reg = info->resets[id].off; - u32 value = BIT(info->resets[id].bit) << 16; + u32 mask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; + u32 value = mask << 16; dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); writel(value, priv->base + CLK_RST_R(reg)); - return 0; + + if (info->has_clk_mon_regs) { + reg = CLK_MRST_R(reg); + } else if (monbit >= 0) { + reg = CPG_RST_MON; + mask = BIT(monbit); + } else { + /* Wait for at least one cyc le of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + return 0; + } + + return readl_poll_timeout_atomic(priv->base + reg, value, + value & mask, 10, 200); } static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, @@ -1430,14 +1445,28 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); const struct rzg2l_cpg_info *info = priv->info; unsigned int reg = info->resets[id].off; - u32 dis = BIT(info->resets[id].bit); - u32 value = (dis << 16) | dis; + u32 mask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; + u32 value = (mask << 16) | mask; dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); writel(value, priv->base + CLK_RST_R(reg)); - return 0; + + if (info->has_clk_mon_regs) { + reg = CLK_MRST_R(reg); + } else if (monbit >= 0) { + reg = CPG_RST_MON; + mask = BIT(monbit); + } else { + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + return 0; + } + + return readl_poll_timeout_atomic(priv->base + reg, value, + !(value & mask), 10, 200); } static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, @@ -1449,9 +1478,6 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, if (ret) return ret; - /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ - udelay(35); - return rzg2l_cpg_deassert(rcdev, id); } @@ -1460,18 +1486,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, { struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); const struct rzg2l_cpg_info *info = priv->info; - unsigned int reg = info->resets[id].off; - u32 bitmask = BIT(info->resets[id].bit); s8 monbit = info->resets[id].monbit; + unsigned int reg; + u32 bitmask; if (info->has_clk_mon_regs) { - return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + reg = CLK_MRST_R(info->resets[id].off); + bitmask = BIT(info->resets[id].bit); } else if (monbit >= 0) { - u32 monbitmask = BIT(monbit); - - return !!(readl(priv->base + CPG_RST_MON) & monbitmask); + reg = CPG_RST_MON; + bitmask = BIT(monbit); + } else { + return -ENOTSUPP; } - return -ENOTSUPP; + + return !!(readl(priv->base + reg) & bitmask); } static const struct reset_control_ops rzg2l_cpg_reset_ops = { From patchwork Thu Dec 7 07:06:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751303 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="FsxYiEDT" Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4831FD7F for ; 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([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:07 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 03/11] pinctrl: renesas: rzg2l: Move arg and index in the main function block Date: Thu, 7 Dec 2023 09:06:52 +0200 Message-Id: <20231207070700.4156557-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Move arg and index in the main block of the function as they are used by more than one case block of switch-case (3 out of 4 for arg, 2 out of 4 for index). In this way some lines of code are removed. Signed-off-by: Claudiu Beznea --- Changes in v2: - adapted for index variable and updated patch title and description accordingly drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f01aa51b00c4..2eb240b731d5 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -842,7 +842,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - unsigned int i; + unsigned int i, arg, index; u32 cfg, off; int ret; u8 bit; @@ -864,24 +864,21 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(_configs[i]); switch (param) { - case PIN_CONFIG_INPUT_ENABLE: { - unsigned int arg = - pinconf_to_config_argument(_configs[i]); + case PIN_CONFIG_INPUT_ENABLE: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IEN)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; - } case PIN_CONFIG_POWER_SOURCE: settings.power_source = pinconf_to_config_argument(_configs[i]); break; - case PIN_CONFIG_DRIVE_STRENGTH: { - unsigned int arg = pinconf_to_config_argument(_configs[i]); - unsigned int index; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; @@ -896,7 +893,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; - } case PIN_CONFIG_DRIVE_STRENGTH_UA: if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || @@ -906,9 +902,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); break; - case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { - unsigned int arg = pinconf_to_config_argument(_configs[i]); - unsigned int index; + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; @@ -922,7 +917,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; - } default: return -EOPNOTSUPP; From patchwork Thu Dec 7 07:06:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751302 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="jMtbvCaH" Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B5D1D7F for ; Wed, 6 Dec 2023 23:08:15 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-54cb4fa667bso723953a12.3 for ; Wed, 06 Dec 2023 23:08:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701932894; x=1702537694; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j8pztiQQJvW9+Mn6ZeFPQfpFGzwj80OOzIuVXmlAIAU=; b=jMtbvCaHXoyPfufiMlyvzGyAebCJXcOajHgUDd7NuUX0z1WboDoO614lhR1N7Me0T4 3KXwWMn9FQt/I2XYT+l8dVakVx+2p+ujRFxIjaf7fNrl9fpBeUX0TnwyQ0UKzRKD8LSY kuEW6uLgZDtH7Mtk9zU326h5d9qnXxBvhAm6GSE+CwNDcT2p4JX+mkwBx0G+o/U/msjM sROozmEdAmMKr13+zF5tqQeSEHPcyMIPniH/580mXKey49FPC0xiarVO7ErOgF+61i3b m5mssbbxFLQc9BXg5TVKomBCorDGViCGQFgyVbh+/7lVZMC7avET44QUhDtGTCPNr4d4 kXXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701932894; x=1702537694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j8pztiQQJvW9+Mn6ZeFPQfpFGzwj80OOzIuVXmlAIAU=; b=i1qvyAIsGGxww7P6oxRELOj0SO3qwKpwQTP5EVbVZpcWswwxFjoupUdOeTg1l3cS1P K43ZMQKm3ggRZy1UYCWeHf8OUUQjuZnmPNIgvc3L1cBliPRimHTdZRshPIeQy8rTjNHp x0nKxTP67uc/Dg8B+CUrz15a2pAenO4FHucse+RP5lWrMcGSg70N8IUAJqEsvJ9IVRpj IoYrZGXlTlySMnjpNPXGMzGmLPIr8IyfXn2vVoMLa6waX6uTNmmKTaA2iFQrZHHYDRUO zYasoMKM8FzNPX0u8UxlITudtvJJyddTifnT2l3W/QASM+ZOreECjiQM02sztu8ZehT5 8ODg== X-Gm-Message-State: AOJu0Yxp6eDBY9mywFKhR7o+9XhEPDqOuNgMBBTxRAzOiiew921jLPGX 0iGmKgXDjGAju0u2b8XWIxUJbA== X-Google-Smtp-Source: AGHT+IEquNJ3LGoK/iqURqpBr6fKSuGAusD/V+gm0/HJ4c/qkdfjbM3einYaGw245MU4dYq89BceSw== X-Received: by 2002:a50:d65a:0:b0:54c:4837:8b7f with SMTP id c26-20020a50d65a000000b0054c48378b7fmr1378223edj.77.1701932894161; Wed, 06 Dec 2023 23:08:14 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:13 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 05/11] pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins Date: Thu, 7 Dec 2023 09:06:54 +0200 Message-Id: <20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The GPIO controller available on RZ/G3S (but also on RZ/G2L) allows setting the power source for Ethernet pins. Based on the interface b/w the Ethernet controller and the Ethernet PHY and board design specific power source need to be selected. The GPIO controller allows 1.8V, 2.5V and 3.3V power source selection for Ethernet pins. This could be selected though ETHX_POC registers (X={0, 1}). Commit adjust the driver to support this and does proper instantiation for RZ/G3S and RZ/G2L SoC. On RZ/G2L only get operation has been tested at the moment. While at it, as the power registers on RZ/G2L support access sizes of 8 bits and RZ/G3S support access sizes of 8/16/32 bits, changed writel()/readl() on these registers with writeb()/readb(). This should allow using the same code for both SoCs w/o any issues. Signed-off-by: Claudiu Beznea --- Changes in v2: - removed PVDD_MASK - use 8 bit helpers to get/set value of power register - replaced if/else with switch/case everywhere drivers/pinctrl/renesas/pinctrl-rzg2l.c | 42 +++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 58786455ecf3..6b082161e821 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -107,8 +107,10 @@ #define IEN(off) (0x1800 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) +#define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ @@ -116,7 +118,6 @@ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PM_MASK 0x03 -#define PVDD_MASK 0x01 #define PFC_MASK 0x07 #define IEN_MASK 0x01 #define IOLH_MASK 0x03 @@ -135,10 +136,12 @@ * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset + * @eth_poc: ETH_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; + u16 eth_poc; }; /** @@ -604,6 +607,10 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 return SD_CH(regs->sd_ch, 0); if (caps & PIN_CFG_IO_VMC_SD1) return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_ETH0) + return ETH_POC(regs->eth_poc, 0); + if (caps & PIN_CFG_IO_VMC_ETH1) + return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; @@ -615,6 +622,7 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; int pwr_reg; + u8 val; if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; @@ -623,7 +631,18 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps if (pwr_reg < 0) return pwr_reg; - return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300; + val = readb(pctrl->base + pwr_reg); + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + default: + /* Should not happen. */ + return -EINVAL; + } } static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) @@ -631,17 +650,32 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; int pwr_reg; + u8 val; if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source = ps; return 0; } + switch (ps) { + case 1800: + val = PVDD_1800; + break; + case 2500: + val = PVDD_2500; + break; + case 3300: + val = PVDD_3300; + break; + default: + return -EINVAL; + } + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); if (pwr_reg < 0) return pwr_reg; - writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg); + writeb(val, pctrl->base + pwr_reg); pctrl->settings[pin].power_source = ps; return 0; @@ -1885,6 +1919,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .regs = { .pwpr = 0x3014, .sd_ch = 0x3000, + .eth_poc = 0x300c, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -1897,6 +1932,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { .regs = { .pwpr = 0x3000, .sd_ch = 0x3004, + .eth_poc = 0x3010, }, .iolh_groupa_ua = { /* 1v8 power source */ From patchwork Thu Dec 7 07:06:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751301 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="jqMXOIHM" Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CB5210EB for ; Wed, 6 Dec 2023 23:08:21 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-54d712c254aso751025a12.0 for ; Wed, 06 Dec 2023 23:08:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701932899; x=1702537699; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KuAnHZUJssT/ogjytdawjrgSLlqBwwzWO4plVJg60Do=; b=jqMXOIHM7NIXqMSoon8Tj4OiojoQsSLX2/6BgPjh+kQEJb2tNRAvMtwr80Zq/+rxar zA6zWDMwm1H7uKoO6SUqbKvJuqYEkyqH+cAYLEWSVqMzzHZJXa4SVlI92vPjrOTU+uJd 54WU0CELrbRUuz6yPC4i1buqDWphqHEKSiZSKy6TVDdraaf6TLx9vIDbvPMioneYPaLh lrXYCDqR7roY1d2s05sjVo3lU2onA3bhE4VZnpLGE58FvQVj78oL/nFMbaHbM12Heg0d zP21IRcdYVgXyTk89LXgqYxiAzywVARsz0kr7GOzei/VwbT9y9iFYuOPHv547AF4xZZC t5HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701932899; x=1702537699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KuAnHZUJssT/ogjytdawjrgSLlqBwwzWO4plVJg60Do=; b=aZFku7CoYzmCXqq8l8Co0JoryMN1vwfRi+bencPKkMwEdF4P+/crVAWzRyefvA9bwB 2zKYUJ1TXEIY2KcAuz6vBK2Vdd0dKzHIJCCQTAJ4daHC6tqqOORmpzouS6xzGuiQDdXH 95T/2rqZzfUPnqUISYSlVJLYx10zsqwKyx0s+HQG/IDKnT4ndDQm/a/jdCf0T68PI98b ABIhvDEpp3KekN79WcPPJSp4ogjNQX4s8upUsEmzEYJA7lqJZKx0yr+JSQssKbHwJ9Nz H8x87lbIulEnm+K+DmFf0Ox6CygTqeEz9TDyLUMYpMk21g99Q65gy2xEvtuokjQOOwYX g2TA== X-Gm-Message-State: AOJu0YyJtMAkH2lKaVclM6W+GVtwBYhNeLSE6rHNIeuuFt4Vxb48iqui bfnElxZZF7wA/De+1o/po0WfbA== X-Google-Smtp-Source: AGHT+IEK/F8KEkOlDZ8jP3JRofMjdFI+uwlBNgwbxKm8acFivOfhgfyBJhuNrj6wnLXSiVf/gPl5mQ== X-Received: by 2002:a05:6402:1ada:b0:54c:4837:8b5e with SMTP id ba26-20020a0564021ada00b0054c48378b5emr1070240edb.44.1701932899557; Wed, 06 Dec 2023 23:08:19 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:19 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 07/11] pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins Date: Thu, 7 Dec 2023 09:06:56 +0200 Message-Id: <20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Some of the RZ/G3S Ethernet pins (P1_0, P7_0) could be configured with input enable. Enable this functionality for these pins. Signed-off-by: Claudiu Beznea --- Changes in v2: - this patch is new in v2 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 0c05ccd03eb2..03253b3150e0 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1444,7 +1444,7 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)) | - PIN_CFG_OEN, /* P1 */ + PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P2 */ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1455,7 +1455,7 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)) | - PIN_CFG_OEN, /* P7 */ + PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)), /* P8 */ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | From patchwork Thu Dec 7 07:06:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751300 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="PcFYmU2r" Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 943D710D7 for ; Wed, 6 Dec 2023 23:08:26 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-54c77e0835bso726151a12.2 for ; Wed, 06 Dec 2023 23:08:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701932905; x=1702537705; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gBYF9QpO8SrhIdSFCDMv2cfVKm7GC7rzruG040ItQBw=; b=PcFYmU2r9sqap1N65jkwIrsaEFmXJ/h4EbdUxZVfAOkrnLfwKaa0/b7kN9a56b4DFj W3nYKIDnQ6NegWhM4s3L+/4orCiTyheRts6Y4dHD8/eut6W5qsTUjsRh/TynQHOn/iFv tw2yDpVj7qqjmev2vd0HpCK+BVn+RYrDX7DFkRd/9wb8TFssVG1NxCvpktTxlN/S1gyh 6STUPc1I4+zBuxr2lIQnIUaLI2DwyhZ/i1A8WKXyeZWBCnhtFAeqkGDfGJLFJhv35h8O K6UoT2iY/hanCBW3aQGky/hIAc5WU/B+sdDlYcsPHU3QMDZH4x8KwfrzI5lJUa+Z9jyr nm4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701932905; x=1702537705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gBYF9QpO8SrhIdSFCDMv2cfVKm7GC7rzruG040ItQBw=; b=sb0AFX3IcV5VuZrmrGElVpQBpFVMk02lbghIzYlr/GCt4pyYiiJ1WSyc7mKwSWzCX1 OhpM6OURdgNX4rm6i6ZOER593MocTwrlTfNoBeN4cRLPSr9972gCG2vRqHq7+4ilZZnE yOtJ7IV3f+xElXlsw3xNn1NOX2G4muCjnrJ6DZY4zSW66UKBouXHmq7m/zW1k4QLswtZ Wfdo7DqHL3aC9fy1u98WDp8guaGNFGCCtchOTa1GIgoFHih/a/trlavNbJCjAIKKdryC g1wgStSBqBT7QGvVOzhOMbulVjnuHfwd3ne10MFl/4ZNjkwYTobGE3pdMr4o7KP5cHHW Jk2A== X-Gm-Message-State: AOJu0Yw2deSdlKOKYtNM8m5hI2I/BKD1p0IBLQhkoUsisrXBpjHjo/m1 YdgV9Cc3/Hhoq9TTw6o9NIkWPw== X-Google-Smtp-Source: AGHT+IHyWA46x9d/N0Itj6CxhWYpryaZpfLZ/5MUDx6RV9OPnuZqeWqpWuACNAJ8F70tFzh8Abi6Dg== X-Received: by 2002:a05:6402:508:b0:54b:fe15:1e9e with SMTP id m8-20020a056402050800b0054bfe151e9emr1190179edv.30.1701932904921; Wed, 06 Dec 2023 23:08:24 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:24 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 09/11] arm64: renesas: r9a08g045: Add the Ethernet nodes Date: Thu, 7 Dec 2023 09:06:58 +0200 Message-Id: <20231207070700.4156557-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add the Ethernet nodes available on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea --- Changes in v2: - added phy-mode = "rgmii" and #address-cells, #size-cells for both Ethernet nodes arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 6c7b29b69d0e..aaab5739c134 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -149,6 +149,44 @@ sdhi2: mmc@11c20000 { status = "disabled"; }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Thu Dec 7 07:07:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751299 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="O/9Uni0v" Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22C3610EC for ; Wed, 6 Dec 2023 23:08:31 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-50bfd3a5b54so356651e87.3 for ; Wed, 06 Dec 2023 23:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701932910; x=1702537710; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yeSFEu7OukF0Tuu74YIE2VRnBvTHvA9bdAjWp6LMSbU=; b=O/9Uni0vZdw0ycdIqGqxwvSsUpKFUqMMwQgStYOhDs6i73kT3RP8IFCoyzxYEHTwVV ij9//XnQ6xftxkQT6E9DV15UjgMP4sOGKalo+/F5IkcLZ9aTh+uWECCqCtbjUQYRZK7+ ZWc9/85NOObX/HMgs6iok3hLeAu/nVXf1s39OKoM2QvgKG5LmiEolghPG3SYx9ojlt/h xA6Z31j0p3QB/ABzYfx/vXY5Q0iKLi7alSDwLORBeyErbANR0vBEqUebJ/Kt5SSdbBgV Yatqrqn5OAqtGd4bwcXdrFBiSmK9udz+UnorAtb4BNeM1qjox6Fm4DhXQ8NjADo7a6r1 vdzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701932910; x=1702537710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yeSFEu7OukF0Tuu74YIE2VRnBvTHvA9bdAjWp6LMSbU=; b=q4zYTuNUvdhDiPldpuKINcFFWgf1Gbl0nWcQKuTMUiMEqrsquOODJmiDzie7tOXxZh cnRMb6wLwYaCiuOMdzb3//lSes18YGHjy7oqHS1OY9OLOyI3ArqL4HV7dWoET0lvXu3V XbBNSO2rJDqI1Pj5mAYy7NqI7s8EveQ2YBGg0DUahRf/P4JfTowY1BOzJNFVfxUfdWqL NRMG6cRyZrHMrTJbYhPxvNUCM+iJYByoFJ6wu8xh3dktFIqWe1W5AfiaNMMrmgI4qsnX H8xga+09FVVCa3M/kDZUU07w7J6fEAPnyw3LqDh6ZWoRmBXRg5VQkOQ2frZA+qIqj0fC f9eg== X-Gm-Message-State: AOJu0YzowvyFStz/69FaJqroW4PphDVbIEfWAiZsV+kPN96fyo2dH8KK zd8+uJFpJ7x7czRkAjEaGjkRzw== X-Google-Smtp-Source: AGHT+IHwFM1deCGaB8hL4AjkVZKdcxII4qcU+r4kO/s02JIjcDLdN1i2kMafFqDp+LcjJNvru3CAlQ== X-Received: by 2002:a05:6512:3b97:b0:50b:effb:c63f with SMTP id g23-20020a0565123b9700b0050beffbc63fmr1725491lfv.6.1701932909933; Wed, 06 Dec 2023 23:08:29 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:29 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 11/11] arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces Date: Thu, 7 Dec 2023 09:07:00 +0200 Message-Id: <20231207070700.4156557-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S Smarc Module has Ethernet PHYs (KSZ9131) connected to each Ethernet IP. For this, add proper DT bindings to enable the Ethernet communication through these PHYs. The interface b/w PHYs and MACs is RGMII. The skew settings were set to zero as based on phy-mode (rgmii-id) the KSZ9131 driver enables internal DLL, which adds a 2ns delay b/w clocks (TX/RX) and data signals. Different pin settings were applied to TXC and TX_CTL compared with the rest of the RGMII pins to comply with requirements for these pins imposed by HW manual of RZ/G3S (see chapters "Ether Ch0 Voltage Mode Control Register (ETH0_POC)", "Ether Ch1 Voltage Mode Control Register (ETH1_POC)", for power source selection, "Ether MII/RGMII Mode Control Register (ETH_MODE)" for output-enable and "Input Enable Control Register (IEN_m)" for input-enable configurations). Commit also enables the Ethernet interfaces by selecting SW_CONFIG3 = SW_ON. Signed-off-by: Claudiu Beznea --- Changes in v2: - removed #address-cells, #size-cells - adapted patch description to reflect the usage of SW_CONFIG .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 141 +++++++++++++++++- 1 file changed, 140 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index f59094701a4a..f062d4ad78b7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -26,7 +26,7 @@ * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC */ #define SW_CONFIG2 SW_ON -#define SW_CONFIG3 SW_OFF +#define SW_CONFIG3 SW_ON / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; @@ -35,6 +35,9 @@ aliases { mmc0 = &sdhi0; #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; +#else + eth0 = ð0; + eth1 = ð1; #endif }; @@ -89,6 +92,60 @@ vcc_sdhi2: regulator2 { }; }; +#if SW_CONFIG3 == SW_ON +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = ; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = ; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + &extal_clk { clock-frequency = <24000000>; }; @@ -136,6 +193,88 @@ &sdhi2 { #endif &pinctrl { + eth0-phy-irq-hog { + gpio-hog; + gpios = ; + input; + line-name = "eth0-phy-irq"; + }; + + eth0_pins: eth0 { + txc { + pinmux = ; /* ET0_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = ; /* ET0_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + ; /* ET0_LINKSTA */ + power-source = <1800>; + }; + }; + + eth1-phy-irq-hog { + gpio-hog; + gpios = ; + input; + line-name = "eth1-phy-irq"; + }; + + eth1_pins: eth1 { + txc { + pinmux = ; /* ET1_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = ; /* ET1_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + , /* ET1_RXD3 */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + ; /* ET1_LINKSTA */ + power-source = <1800>; + }; + }; + sdhi0_pins: sd0 { data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";