From patchwork Thu Dec 7 07:59:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751297 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="JanL5Eku" Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.219]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D16C1A9; Thu, 7 Dec 2023 00:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=B3xSh 3pkeOtaKv+3Outtg7o/L43oM6faIEHTjYD8usE=; b=JanL5Eku32O30yMgUdLKu VpRU8iRG9ekzTAQg81p7V6qtztJSqLnZ/XnATyG9G7yDi70aJ0PL8I6/Vj6KUBBk kj9n80afJj4Hdq5oE8Cwu//xdNem9RmB3dgXYSJo56tUeDigXm0FgVAEgJY+5jo3 683GpW3rTgyAGGGjLCBUGU= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g2-3 (Coremail) with SMTP id _____wCnt_dqe3FlwimwEw--.44252S2; Thu, 07 Dec 2023 15:59:43 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan , Sascha Hauer Subject: [PATCH v4 01/17] drm/rockchip: move output interface related definition to rockchip_drm_drv.h Date: Thu, 7 Dec 2023 15:59:37 +0800 Message-Id: <20231207075937.651864-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wCnt_dqe3FlwimwEw--.44252S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxtFW3Zw17XF4DCr1xZr45trb_yoW3XryDpa 1DAryjvrW7CF42qrnrAFs3Ar4fta1qyayxCr97W3WavF1Ikr1DG3sxWws5Xr9xXr1xAFW2 krsrG34UAF42gr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jSKZJUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEgs-XmVOA0WqfQAEsG From: Andy Yan The output interface related definition can shared between vop and vop2, move them to rockchip_drm_drv.h can avoid duplicated definition. Signed-off-by: Andy Yan Reviewed-by: Sascha Hauer --- (no changes since v1) drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 - drivers/gpu/drm/rockchip/cdn-dp-core.c | 1 - drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 1 - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 - drivers/gpu/drm/rockchip/inno_hdmi.c | 1 - drivers/gpu/drm/rockchip/rk3066_hdmi.c | 1 - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 12 +----------- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 16 +--------------- drivers/gpu/drm/rockchip/rockchip_lvds.c | 1 - drivers/gpu/drm/rockchip/rockchip_rgb.c | 1 - 11 files changed, 19 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 84aa811ca1e9..bd08d57486fe 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -30,7 +30,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define RK3288_GRF_SOC_CON6 0x25c #define RK3288_EDP_LCDC_SEL BIT(5) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index 21254e4e107a..a855c45ae7f3 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -24,7 +24,6 @@ #include "cdn-dp-core.h" #include "cdn-dp-reg.h" -#include "rockchip_drm_vop.h" static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) { diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 6396f9324dab..4cc8ed8f4fbd 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -26,7 +26,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define DSI_PHY_RSTZ 0xa0 #define PHY_DISFORCEPLL 0 diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 341550199111..fe33092abbe7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -18,7 +18,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define RK3228_GRF_SOC_CON2 0x0408 #define RK3228_HDMI_SDAIN_MSK BIT(14) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index 6e5b922a121e..f6d819803c0e 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -23,7 +23,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #include "inno_hdmi.h" diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c index fa6e592e0276..78136d0c5a65 100644 --- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c +++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c @@ -17,7 +17,6 @@ #include "rk3066_hdmi.h" #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define DEFAULT_PLLA_RATE 30000000 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index aeb03a57240f..3d8ab2defa1b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -20,6 +20,23 @@ #define ROCKCHIP_MAX_CONNECTOR 2 #define ROCKCHIP_MAX_CRTC 4 +/* + * display output interface supported by rockchip lcdc + */ +#define ROCKCHIP_OUT_MODE_P888 0 +#define ROCKCHIP_OUT_MODE_BT1120 0 +#define ROCKCHIP_OUT_MODE_P666 1 +#define ROCKCHIP_OUT_MODE_P565 2 +#define ROCKCHIP_OUT_MODE_BT656 5 +#define ROCKCHIP_OUT_MODE_S888 8 +#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 +#define ROCKCHIP_OUT_MODE_YUV420 14 +/* for use special outface */ +#define ROCKCHIP_OUT_MODE_AAAA 15 + +/* output flags */ +#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) + struct drm_device; struct drm_connector; struct iommu_domain; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 4b2daefeb8c1..43d9c9191b7a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -277,17 +277,7 @@ struct vop_data { /* dst alpha ctrl define */ #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) -/* - * display output interface supported by rockchip lcdc - */ -#define ROCKCHIP_OUT_MODE_P888 0 -#define ROCKCHIP_OUT_MODE_P666 1 -#define ROCKCHIP_OUT_MODE_P565 2 -/* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 - -/* output flags */ -#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) + enum alpha_mode { ALPHA_STRAIGHT, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h index 56fd31e05238..7175f46a2014 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -7,10 +7,9 @@ #ifndef _ROCKCHIP_DRM_VOP2_H #define _ROCKCHIP_DRM_VOP2_H -#include "rockchip_drm_vop.h" - #include #include +#include "rockchip_drm_vop.h" #define VOP_FEATURE_OUTPUT_10BIT BIT(0) @@ -166,19 +165,6 @@ struct vop2_data { #define WB_YRGB_FIFO_FULL_INTR BIT(18) #define WB_COMPLETE_INTR BIT(19) -/* - * display output interface supported by rockchip lcdc - */ -#define ROCKCHIP_OUT_MODE_P888 0 -#define ROCKCHIP_OUT_MODE_BT1120 0 -#define ROCKCHIP_OUT_MODE_P666 1 -#define ROCKCHIP_OUT_MODE_P565 2 -#define ROCKCHIP_OUT_MODE_BT656 5 -#define ROCKCHIP_OUT_MODE_S888 8 -#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 -#define ROCKCHIP_OUT_MODE_YUV420 14 -/* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 enum vop_csc_format { CSC_BT601L, diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index f0f47e9abf5a..59341654ec32 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -27,7 +27,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #include "rockchip_lvds.h" #define DISPLAY_OUTPUT_RGB 0 diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index c677b71ae516..dbfbde24698e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -19,7 +19,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #include "rockchip_rgb.h" struct rockchip_rgb { From patchwork Thu Dec 7 08:00:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751296 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="OKq28FKF" Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.220]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 048EDDD; Thu, 7 Dec 2023 00:01:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=c7kjH jIQ4/nlmiPUxBorZmmivgfaJAOI5Gw9Jj5OowE=; b=OKq28FKFyYa6b2htLqGNk 7n0gxfW6w4Ry12uVjON3FpSilpH14JBP3fdiTWFYnHcexD/F51X/S85Cmm/nzXnn pBXP1x4uqZ/Yps9Q/ryfaNJKiws5IClqDgOZJXYhOHvPqkNEyQzG0PtGYW+L3vLV qwW5eY00Ifora/G/WGoNX8= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g2-2 (Coremail) with SMTP id _____wD3f3ORe3FlNJyiAg--.51521S2; Thu, 07 Dec 2023 16:00:20 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan , Sascha Hauer Subject: [PATCH v4 04/17] drm/rockchip: vop2: clear afbc en and transform bit for cluster window at linear mode Date: Thu, 7 Dec 2023 16:00:16 +0800 Message-Id: <20231207080016.652051-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wD3f3ORe3FlNJyiAg--.51521S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZrW3WF1DuFyrWryfXrWkZwb_yoW8Gr1kpr W5AFWqqr4xK3yqqa1DJF9xZFZYk3ZFkayxWrZ7JwnFgFWUKa4kG3Z0kryDJrWUJ3WagF48 trn3JrW7ZFWYvr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jSwZ7UUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEhg-XmVOA0WxpgAAsR From: Andy Yan The enable bit and transform offset of cluster windows should be cleared when it work at linear mode, or we may have a iommu fault issue on rk3588 which cluster windows switch between afbc and linear mode. As the cluster windows of rk3568 only supports afbc format so is therefore not affected. Signed-off-by: Andy Yan Reviewed-by: Sascha Hauer --- (no changes since v1) drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 639dfebc6bd1..a019cc9bbd54 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1312,6 +1312,11 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); } else { + if (vop2_cluster_window(win)) { + vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0); + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0); + } + vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); } From patchwork Thu Dec 7 08:00:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751294 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="mDDS1ncW" X-Greylist: delayed 113 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Thu, 07 Dec 2023 00:02:09 PST Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.214]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9726B1711; Thu, 7 Dec 2023 00:02:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=J7E+B pO4zUY8zBD6oBKSRdW051kiXnsXucME7l+c/aQ=; b=mDDS1ncW2MczHVNiWFD8m OPJoK+GCeiGHKPfqsdVIua2pOwXgMd1V+4JznAgzfi6pOKq2Xkk7pE2Vdwc1huCT VNY+cX4VL7UzmIT/IxfbTliBeTsBkzSjkr9dekp5J2yZ0Hh9XHua4LTmaV7BDYgA sleEHaiHZhC5zaw3HJ8h60= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g5-2 (Coremail) with SMTP id _____wDn706qe3FlJlmfEw--.42456S2; Thu, 07 Dec 2023 16:00:46 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan Subject: [PATCH v4 06/17] drm/rockchip: vop2: Set YUV/RGB overlay mode Date: Thu, 7 Dec 2023 16:00:41 +0800 Message-Id: <20231207080041.652171-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDn706qe3FlJlmfEw--.42456S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxXr18XrWkAFyrWFW3Ww47XFb_yoWrCr1fpw n7ZryYqrWDKF4qqw1kAF98ZF4Skw4Iyay7GFn7Gasxua4vgryDWwnxuas8AFnrXF17urWj yrZFkry5AF42vr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jo5lbUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEBQ-XmVOA0WnwQAAsu From: Andy Yan Set overlay mode register according to the output mode is yuv or rgb. Signed-off-by: Andy Yan --- (no changes since v3) Changes in v3: - put bool variable yuv_overlay next to other bool variable - define macro for RK3568_OVL_CTRL__YUV_MODE - just write RK3568_OVL_CTRL register once in function vop2_setup_layer_mixer drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 18 +++++++++++++++--- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index 3d8ab2defa1b..bbb9e0bf6804 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -48,6 +48,7 @@ struct rockchip_crtc_state { int output_bpc; int output_flags; bool enable_afbc; + bool yuv_overlay; u32 bus_format; u32 bus_flags; int color_space; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 25c1f33c5622..40b5c5ca4864 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1623,6 +1623,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, vop2->enable_count++; + vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format); + vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); polflags = 0; @@ -1650,7 +1652,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; - if (is_yuv_output(vcstate->bus_format)) + if (vcstate->yuv_overlay) dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; vop2_dither_setup(crtc, &dsp_ctrl); @@ -1959,10 +1961,12 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) u16 hdisplay; u32 bg_dly; u32 pre_scan_dly; + u32 ovl_ctrl; int i; struct vop2_video_port *vp0 = &vop2->vps[0]; struct vop2_video_port *vp1 = &vop2->vps[1]; struct vop2_video_port *vp2 = &vop2->vps[2]; + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); adjusted_mode = &vp->crtc.state->adjusted_mode; hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; @@ -1975,7 +1979,15 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); - vop2_writel(vop2, RK3568_OVL_CTRL, 0); + ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL); + ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD; + if (vcstate->yuv_overlay) + ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id); + else + ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id); + + vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); + port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; @@ -2047,9 +2059,9 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); } + vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); - vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); } static void vop2_setup_dly_for_windows(struct vop2 *vop2) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h index 7175f46a2014..8d7ff52523fb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -401,6 +401,7 @@ enum dst_factor_mode { #define VOP2_COLOR_KEY_MASK BIT(31) #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) +#define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp) #define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) From patchwork Thu Dec 7 08:00:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751295 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="IQ008HFp" Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EC3CE10EC; Thu, 7 Dec 2023 00:02:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=VvpYT W40NZ46U/uC3kxp5psTC7U46RpXFvNEExH8M2A=; b=IQ008HFp5OA3GgxNQsPyq hv/z0ZxaYe2bxDJCj/rqLB1bEBTCF8GJ7NqCbMbkdOZTuV4XboNI/nQz9OVFwe7c r0fAIKQWx32Ne4FGO1VxIztm/a28xQChjnqEilr9UvY18/g/3VXISE2kakhF414I ercPPE6F5ZpLu2Y1RuwykQ= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g5-4 (Coremail) with SMTP id _____wDXP+u5e3FlrnEFCg--.40966S2; Thu, 07 Dec 2023 16:01:01 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan Subject: [PATCH v4 07/17] drm/rockchip: vop2: set bg dly and prescan dly at vop2_post_config Date: Thu, 7 Dec 2023 16:00:55 +0800 Message-Id: <20231207080055.652230-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDXP+u5e3FlrnEFCg--.40966S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxZw4kZw1UJrWUtF15Ww1Utrb_yoW5Xr4rp3 4fGry3CrWUJF4qvw1kZa4DZr4fKws7tr47JFW7Jas2yF90qr9xZwn8urn8GrWqqFy7AFy2 9rWvgrWYgF1akr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jSOJnUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnAs-Xlghl3ZClgABs7 From: Andy Yan We need to setup background delay cycle and prescan delay cycle when a mode is enable to avoid trigger POST_BUF_EMPTY irq on rk3588. Note: RK356x has no such requirement. Signed-off-by: Andy Yan --- (no changes since v1) drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 ++++++++------------ 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 40b5c5ca4864..d52395b6aff7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1460,8 +1460,18 @@ static void vop2_post_config(struct drm_crtc *crtc) u32 top_margin = 100, bottom_margin = 100; u16 hsize = hdisplay * (left_margin + right_margin) / 200; u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; + u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; u16 hact_end, vact_end; u32 val; + u32 bg_dly; + u32 pre_scan_dly; + + bg_dly = vp->data->pre_scan_max_dly[3]; + vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id), + FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); + + pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; + vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); vsize = rounddown(vsize, 2); hsize = rounddown(hsize, 2); @@ -1956,11 +1966,6 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) u32 layer_sel = 0; u32 port_sel; unsigned int nlayer, ofs; - struct drm_display_mode *adjusted_mode; - u16 hsync_len; - u16 hdisplay; - u32 bg_dly; - u32 pre_scan_dly; u32 ovl_ctrl; int i; struct vop2_video_port *vp0 = &vop2->vps[0]; @@ -1968,17 +1973,6 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) struct vop2_video_port *vp2 = &vop2->vps[2]; struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); - adjusted_mode = &vp->crtc.state->adjusted_mode; - hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; - hdisplay = adjusted_mode->crtc_hdisplay; - - bg_dly = vp->data->pre_scan_max_dly[3]; - vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), - FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); - - pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; - vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); - ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL); ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD; if (vcstate->yuv_overlay) From patchwork Thu Dec 7 08:01:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751293 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Cr0WyG91" Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C2CB810C8; Thu, 7 Dec 2023 00:02:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=4hIly MNzL863/Hk1Ll2QKnKQl9tBh0XjMWCIZh2OIFg=; b=Cr0WyG91SPFplCRGTcl8X nJqB3h0/iKjJ9nJw2ZFOctyCPBRHh9moPourNcxJCiSIrZrsrSIUFhi56xMxIryH xDn62NNVAQ52k04BUbjNlum91uEnRyMKFVOmh90+h7ItPUpI9Dv1Ryw3Unj4tL7n KVv9lE9nqZ1nw8a6TOlGuI= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g3-0 (Coremail) with SMTP id _____wDn75vSe3FlApkTAQ--.44804S2; Thu, 07 Dec 2023 16:01:25 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan , Rob Herring Subject: [PATCH v4 09/17] dt-bindings: soc: rockchip: add rk3588 vop/vo syscon Date: Thu, 7 Dec 2023 16:01:21 +0800 Message-Id: <20231207080121.652355-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wDn75vSe3FlApkTAQ--.44804S2 X-Coremail-Antispam: 1Uf129KBjvdXoW7XF13Ar4UKr17uw1Utw47urg_yoWfCFgE9a 4xZ3WUuFW8GryFgw1qyayIk3Z8A3Z2kFykCa1jyF4kCaykZrWDKF95tw1Svr15u3Wfuwn3 GFn5WrWUGFnxGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7IU8tfQtUUUUU== X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEhM-XmVOA0W3vwABsE From: Andy Yan Add VOP and VO GRF syscon compatibles for RK3588 Signed-off-by: Andy Yan Acked-by: Rob Herring --- (no changes since v1) Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index e4fa6a07b4fa..26db4f48ff62 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -28,6 +28,8 @@ properties: - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf + - rockchip,rk3588-vo-grf + - rockchip,rk3588-vop-grf - rockchip,rv1108-usbgrf - const: syscon - items: From patchwork Thu Dec 7 08:01:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751291 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="auWbLeCT" Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.219]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AC12210C2; Thu, 7 Dec 2023 00:03:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=17D9Q nUCFtUpWuAxl+D67XBKy8UWEn57ifZQCN+m49Q=; b=auWbLeCT8lgWpnnCGURTD G5bsrkSYB6Ch+Vj4idv2xeomn58nk+/fQCL2DDuJjHaJvC+riUANgT2ivWh6w2uj FJp6cFYd5hIGiZz7kjKEKU8NX81KA592Z6YmUhA0VFKP2QkDDJWk/SgZEC83CZOD 2HbFF6xCIY5NDHDppUsMLo= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g2-4 (Coremail) with SMTP id _____wD3Pzz1e3Fly_ZcEw--.33725S2; Thu, 07 Dec 2023 16:02:00 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan , Sascha Hauer Subject: [PATCH v4 12/17] drm/rockchip: vop2: Add support for rk3588 Date: Thu, 7 Dec 2023 16:01:56 +0800 Message-Id: <20231207080156.652535-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wD3Pzz1e3Fly_ZcEw--.33725S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfAF1DZryUWFWkuryUuFyxAFb_yoW5KF17Ao W7C3W3Xw15tw1fCwsrWr1xX347uw4xA3WxurZrA39avanxWw4UKryIvasFvF12y3yYkFW3 Ar1vqw1rXFWfA3Wxn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxU3nmiDUUUU X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqBY-XmVOA0YL3QABsm From: Andy Yan VOP2 on rk3588: Four video ports: VP0 Max 4096x2160 VP1 Max 4096x2160 VP2 Max 4096x2160 VP3 Max 2048x1080 4 4K Cluster windows with AFBC/line RGB and AFBC-only YUV support 4 4K Esmart windows with line RGB/YUV support Signed-off-by: Andy Yan Reviewed-by: Sascha Hauer --- Changes in v4: - keep all VOP2_FEATURE_HAS_xxx macros increase in order. Changes in v3: - add braces for x in macro vop2_output_if_is_yyy(x) - clear the bits of a mask before setting it in rk3588_set_intf_mux - add more comments. Changes in v2: - add rk3588_ prefix for functions which are rk3588 only - make some calculation as fixed value and keep calculation formula as comment - check return value for some cru calculation functions. - check return value for syscon_regmap_lookup_by_phandle - add NV20/NV30 for esmart plane drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 402 ++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 81 ++++ drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 221 ++++++++++ 3 files changed, 698 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 64155b115744..edca7723335f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -191,6 +191,9 @@ struct vop2 { struct regmap *map; struct regmap *sys_grf; + struct regmap *vop_grf; + struct regmap *vo1_grf; + struct regmap *sys_pmu; /* physical map length of vop2 register */ u32 len; @@ -209,6 +212,7 @@ struct vop2 { unsigned int enable_count; struct clk *hclk; struct clk *aclk; + struct clk *pclk; /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -217,6 +221,23 @@ struct vop2 { struct vop2_win win[]; }; +#define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \ + (x) == ROCKCHIP_VOP2_EP_HDMI1) + +#define vop2_output_if_is_dp(x) ((x) == ROCKCHIP_VOP2_EP_DP0 || \ + (x) == ROCKCHIP_VOP2_EP_DP1) + +#define vop2_output_if_is_edp(x) ((x) == ROCKCHIP_VOP2_EP_EDP0 || \ + (x) == ROCKCHIP_VOP2_EP_EDP1) + +#define vop2_output_if_is_mipi(x) ((x) == ROCKCHIP_VOP2_EP_MIPI0 || \ + (x) == ROCKCHIP_VOP2_EP_MIPI1) + +#define vop2_output_if_is_lvds(x) ((x) == ROCKCHIP_VOP2_EP_LVDS0 || \ + (x) == ROCKCHIP_VOP2_EP_LVDS1) + +#define vop2_output_if_is_dpi(x) ((x) == ROCKCHIP_VOP2_EP_RGB0) + static const struct regmap_config vop2_regmap_config; static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) @@ -475,6 +496,17 @@ static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) return false; } +static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format) +{ + if (vop2->data->soc_id == 3588) { + if (bus_format == MEDIA_BUS_FMT_YUV8_1X24 || + bus_format == MEDIA_BUS_FMT_YUV10_1X30) + return true; + } + + return false; +} + static bool is_yuv_output(u32 bus_format) { switch (bus_format) { @@ -879,13 +911,32 @@ static int vop2_core_clks_prepare_enable(struct vop2 *vop2) goto err; } + ret = clk_prepare_enable(vop2->pclk); + if (ret < 0) { + drm_err(vop2->drm, "failed to enable pclk - %d\n", ret); + goto err1; + } + return 0; +err1: + clk_disable_unprepare(vop2->aclk); err: clk_disable_unprepare(vop2->hclk); return ret; } +static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2) +{ + u32 pd; + + pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL); + pd &= ~(VOP2_PD_CLUSTER0 | VOP2_PD_CLUSTER1 | VOP2_PD_CLUSTER2 | + VOP2_PD_CLUSTER3 | VOP2_PD_ESMART); + + vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd); +} + static void vop2_enable(struct vop2 *vop2) { int ret; @@ -917,6 +968,9 @@ static void vop2_enable(struct vop2 *vop2) if (vop2->data->soc_id == 3566) vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); + if (vop2->data->soc_id == 3588) + rk3588_vop2_power_domain_enable_all(vop2); + vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); /* @@ -942,6 +996,7 @@ static void vop2_disable(struct vop2 *vop2) pm_runtime_put_sync(vop2->dev); + clk_disable_unprepare(vop2->pclk); clk_disable_unprepare(vop2->aclk); clk_disable_unprepare(vop2->hclk); } @@ -1309,7 +1364,19 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); - vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); + /* + * On rk3566/8, this bit is auto gating enable, + * but this function is not work well so we need + * to disable it for these two platform. + * On rk3588, and the following new soc(rk3528/rk3576), + * this bit is gating disable, we should write 1 to + * disable gating when enable afbc. + */ + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); + else + vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1); + vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); transform_offset = vop2_afbc_transform_offset(pstate, half_block_en); vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); @@ -1507,10 +1574,10 @@ static void vop2_post_config(struct drm_crtc *crtc) vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); } -static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, - u32 polflags) +static unsigned long rk3568_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) { struct vop2 *vop2 = vp->vop2; + struct drm_crtc *crtc = &vp->crtc; u32 die, dip; die = vop2_readl(vop2, RK3568_DSP_IF_EN); @@ -1572,13 +1639,281 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, break; default: drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); - return; + return 0; } dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; vop2_writel(vop2, RK3568_DSP_IF_EN, die); vop2_writel(vop2, RK3568_DSP_IF_POL, dip); + + return crtc->state->adjusted_mode.crtc_clock * 1000LL; +} + +/* + * calc the dclk on rk3588 + * the available div of dclk is 1, 2, 4 + */ +static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max_dclk) +{ + if (child_clk * 4 <= max_dclk) + return child_clk * 4; + else if (child_clk * 2 <= max_dclk) + return child_clk * 2; + else if (child_clk <= max_dclk) + return child_clk; + else + return 0; +} + +/* + * 4 pixclk/cycle on rk3588 + * RGB/eDP/HDMI: if_pixclk >= dclk_core + * DP: dp_pixclk = dclk_out <= dclk_core + * DSI: mipi_pixclk <= dclk_out <= dclk_core + */ +static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id, + int *dclk_core_div, int *dclk_out_div, + int *if_pixclk_div, int *if_dclk_div) +{ + struct vop2 *vop2 = vp->vop2; + struct drm_crtc *crtc = &vp->crtc; + struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); + int output_mode = vcstate->output_mode; + unsigned long v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */ + unsigned long dclk_core_rate = v_pixclk >> 2; + unsigned long dclk_rate = v_pixclk; + unsigned long dclk_out_rate; + unsigned long if_dclk_rate; + unsigned long if_pixclk_rate; + int K = 1; + + if (vop2_output_if_is_hdmi(id)) { + /* + * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate + * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate + */ + if (output_mode == ROCKCHIP_OUT_MODE_YUV420) { + dclk_rate = dclk_rate >> 1; + K = 2; + } + + if_pixclk_rate = (dclk_core_rate << 1) / K; + if_dclk_rate = dclk_core_rate / K; + /* + * *if_pixclk_div = dclk_rate / if_pixclk_rate; + * *if_dclk_div = dclk_rate / if_dclk_rate; + */ + *if_pixclk_div = 2; + *if_dclk_div = 4; + } else if (vop2_output_if_is_edp(id)) { + /* + * edp_pixclk = edp_dclk > dclk_core + */ + if_pixclk_rate = v_pixclk / K; + dclk_rate = if_pixclk_rate * K; + /* + * *if_pixclk_div = dclk_rate / if_pixclk_rate; + * *if_dclk_div = *if_pixclk_div; + */ + *if_pixclk_div = K; + *if_dclk_div = K; + } else if (vop2_output_if_is_dp(id)) { + if (output_mode == ROCKCHIP_OUT_MODE_YUV420) + dclk_out_rate = v_pixclk >> 3; + else + dclk_out_rate = v_pixclk >> 2; + + dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000); + if (!dclk_rate) { + drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n", + dclk_out_rate); + return 0; + } + *dclk_out_div = dclk_rate / dclk_out_rate; + } else if (vop2_output_if_is_mipi(id)) { + if_pixclk_rate = dclk_core_rate / K; + /* + * dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 + */ + dclk_out_rate = if_pixclk_rate; + /* + * dclk_rate = N * dclk_core_rate N = (1,2,4 ), + * we get a little factor here + */ + dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000); + if (!dclk_rate) { + drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n", + dclk_out_rate); + return 0; + } + *dclk_out_div = dclk_rate / dclk_out_rate; + /* + * mipi pixclk == dclk_out + */ + *if_pixclk_div = 1; + } else if (vop2_output_if_is_dpi(id)) { + dclk_rate = v_pixclk; + } + + *dclk_core_div = dclk_rate / dclk_core_rate; + *if_pixclk_div = ilog2(*if_pixclk_div); + *if_dclk_div = ilog2(*if_dclk_div); + *dclk_core_div = ilog2(*dclk_core_div); + *dclk_out_div = ilog2(*dclk_out_div); + + drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n", + dclk_rate, *if_pixclk_div, *if_dclk_div); + + return dclk_rate; +} + +/* + * MIPI port mux on rk3588: + * 0: Video Port2 + * 1: Video Port3 + * 3: Video Port 1(MIPI1 only) + */ +static u32 rk3588_get_mipi_port_mux(int vp_id) +{ + if (vp_id == 1) + return 3; + else if (vp_id == 3) + return 1; + else + return 0; +} + +static u32 rk3588_get_hdmi_pol(u32 flags) +{ + u32 val; + + val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; + val |= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; + + return val; +} + +static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) +{ + struct vop2 *vop2 = vp->vop2; + int dclk_core_div, dclk_out_div, if_pixclk_div, if_dclk_div; + unsigned long clock; + u32 die, dip, div, vp_clk_div, val; + + clock = rk3588_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div, + &if_pixclk_div, &if_dclk_div); + if (!clock) + return 0; + + vp_clk_div = FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_CORE_DIV, dclk_core_div); + vp_clk_div |= FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_OUT_DIV, dclk_out_div); + + die = vop2_readl(vop2, RK3568_DSP_IF_EN); + dip = vop2_readl(vop2, RK3568_DSP_IF_POL); + div = vop2_readl(vop2, RK3568_DSP_IF_CTRL); + + switch (id) { + case ROCKCHIP_VOP2_EP_HDMI0: + div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV; + div &= ~RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV; + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_HDMI0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); + val = rk3588_get_hdmi_pol(polflags); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1)); + regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5)); + break; + case ROCKCHIP_VOP2_EP_HDMI1: + div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV; + div &= ~RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV; + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_HDMI1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id); + val = rk3588_get_hdmi_pol(polflags); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4)); + regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7)); + break; + case ROCKCHIP_VOP2_EP_EDP0: + div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV; + div &= ~RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV; + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_EDP0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0)); + break; + case ROCKCHIP_VOP2_EP_EDP1: + div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV; + div &= ~RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV; + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_EDP1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3)); + break; + case ROCKCHIP_VOP2_EP_MIPI0: + div &= ~RK3588_DSP_IF_MIPI0_PCLK_DIV; + div |= FIELD_PREP(RK3588_DSP_IF_MIPI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX; + val = rk3588_get_mipi_port_mux(vp->id); + die |= RK3588_SYS_DSP_INFACE_EN_MIPI0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX, !!val); + break; + case ROCKCHIP_VOP2_EP_MIPI1: + div &= ~RK3588_DSP_IF_MIPI1_PCLK_DIV; + div |= FIELD_PREP(RK3588_DSP_IF_MIPI1_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX; + val = rk3588_get_mipi_port_mux(vp->id); + die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, val); + break; + case ROCKCHIP_VOP2_EP_DP0: + die &= ~RK3588_SYS_DSP_INFACE_EN_DP0_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_DP0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP0_MUX, vp->id); + dip &= ~RK3588_DSP_IF_POL__DP0_PIN_POL; + dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags); + break; + case ROCKCHIP_VOP2_EP_DP1: + die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); + dip &= ~RK3588_DSP_IF_POL__DP1_PIN_POL; + dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags); + break; + default: + drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); + return 0; + } + + dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; + + vop2_vp_write(vp, RK3588_VP_CLK_CTRL, vp_clk_div); + vop2_writel(vop2, RK3568_DSP_IF_EN, die); + vop2_writel(vop2, RK3568_DSP_IF_CTRL, div); + vop2_writel(vop2, RK3568_DSP_IF_POL, dip); + + return clock; +} + +static unsigned long vop2_set_intf_mux(struct vop2_video_port *vp, int ep_id, u32 polflags) +{ + struct vop2 *vop2 = vp->vop2; + + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + return rk3568_set_intf_mux(vp, ep_id, polflags); + else if (vop2->data->soc_id == 3588) + return rk3588_set_intf_mux(vp, ep_id, polflags); + else + return 0; } static int us_to_vertical_line(struct drm_display_mode *mode, int us) @@ -1648,9 +1983,17 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); + /* + * for drive a high resolution(4KP120, 8K), vop on rk3588/rk3576 need + * process multi(1/2/4/8) pixels per cycle, so the dclk feed by the + * system cru may be the 1/2 or 1/4 of mode->clock. + */ + clock = vop2_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); } + if (!clock) + return; + if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) out_mode = ROCKCHIP_OUT_MODE_P888; @@ -1661,6 +2004,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; + if (vop2_output_rg_swap(vop2, vcstate->bus_format)) + dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RG_SWAP; if (vcstate->yuv_overlay) dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; @@ -2022,6 +2367,14 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); break; + case ROCKCHIP_VOP2_CLUSTER2: + port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER2; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER2, vp->id); + break; + case ROCKCHIP_VOP2_CLUSTER3: + port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER3; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER3, vp->id); + break; case ROCKCHIP_VOP2_ESMART0: port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); @@ -2030,6 +2383,14 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); break; + case ROCKCHIP_VOP2_ESMART2: + port_sel &= ~RK3588_OVL_PORT_SEL__ESMART2; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART2, vp->id); + break; + case ROCKCHIP_VOP2_ESMART3: + port_sel &= ~RK3588_OVL_PORT_SEL__ESMART3; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART3, vp->id); + break; case ROCKCHIP_VOP2_SMART0: port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); @@ -2767,8 +3128,31 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) if (IS_ERR(vop2->lut_regs)) return PTR_ERR(vop2->lut_regs); } + if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_GRF) { + vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + if (IS_ERR(vop2->sys_grf)) + return dev_err_probe(dev, PTR_ERR(vop2->sys_grf), "cannot get sys_grf"); + } - vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + if (vop2_data->feature & VOP2_FEATURE_HAS_VOP_GRF) { + vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf"); + if (IS_ERR(vop2->vop_grf)) + return dev_err_probe(dev, PTR_ERR(vop2->vop_grf), "cannot get vop_grf"); + + } + + if (vop2_data->feature & VOP2_FEATURE_HAS_VO1_GRF) { + vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf"); + if (IS_ERR(vop2->vo1_grf)) + return dev_err_probe(dev, PTR_ERR(vop2->vo1_grf), "cannot get vo1_grf"); + + } + + if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_PMU) { + vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); + if (IS_ERR(vop2->sys_pmu)) + return dev_err_probe(dev, PTR_ERR(vop2->sys_pmu), "cannot get sys_pmu"); + } vop2->hclk = devm_clk_get(vop2->dev, "hclk"); if (IS_ERR(vop2->hclk)) { @@ -2782,6 +3166,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->aclk); } + vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); + if (IS_ERR(vop2->pclk)) { + drm_err(vop2->drm, "failed to get pclk source\n"); + return PTR_ERR(vop2->pclk); + } + vop2->irq = platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h index 8d7ff52523fb..2763e54350a9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -13,9 +13,16 @@ #define VOP_FEATURE_OUTPUT_10BIT BIT(0) +#define VOP2_FEATURE_HAS_SYS_GRF BIT(0) +#define VOP2_FEATURE_HAS_VO0_GRF BIT(1) +#define VOP2_FEATURE_HAS_VO1_GRF BIT(2) +#define VOP2_FEATURE_HAS_VOP_GRF BIT(3) +#define VOP2_FEATURE_HAS_SYS_PMU BIT(4) + #define WIN_FEATURE_AFBDC BIT(0) #define WIN_FEATURE_CLUSTER BIT(1) +#define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) /* * the delay number of a window in different mode. */ @@ -38,6 +45,18 @@ enum vop2_scale_down_mode { VOP2_SCALE_DOWN_AVG, }; +/* + * vop2 internal power domain id, + * should be all none zero, 0 will be treat as invalid; + */ +#define VOP2_PD_CLUSTER0 BIT(0) +#define VOP2_PD_CLUSTER1 BIT(1) +#define VOP2_PD_CLUSTER2 BIT(2) +#define VOP2_PD_CLUSTER3 BIT(3) +#define VOP2_PD_DSC_8K BIT(5) +#define VOP2_PD_DSC_4K BIT(6) +#define VOP2_PD_ESMART BIT(7) + enum vop2_win_regs { VOP2_WIN_ENABLE, VOP2_WIN_FORMAT, @@ -138,6 +157,7 @@ struct vop2_video_port_data { struct vop2_data { u8 nr_vps; + u64 feature; const struct vop2_win_data *win; const struct vop2_video_port_data *vp; struct vop_rect max_input; @@ -192,6 +212,11 @@ enum dst_factor_mode { }; #define RK3568_GRF_VO_CON1 0x0364 + +#define RK3588_GRF_SOC_CON1 0x0304 +#define RK3588_GRF_VOP_CON2 0x08 +#define RK3588_GRF_VO1_CON0 0x00 + /* System registers definition */ #define RK3568_REG_CFG_DONE 0x000 #define RK3568_VERSION_INFO 0x004 @@ -200,6 +225,7 @@ enum dst_factor_mode { #define RK3568_DSP_IF_EN 0x028 #define RK3568_DSP_IF_CTRL 0x02c #define RK3568_DSP_IF_POL 0x030 +#define RK3588_SYS_PD_CTRL 0x034 #define RK3568_WB_CTRL 0x40 #define RK3568_WB_XSCAL_FACTOR 0x44 #define RK3568_WB_YRGB_MST 0x48 @@ -220,9 +246,14 @@ enum dst_factor_mode { #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) /* Video Port registers definition */ +#define RK3568_VP0_CTRL_BASE 0x0C00 +#define RK3568_VP1_CTRL_BASE 0x0D00 +#define RK3568_VP2_CTRL_BASE 0x0E00 +#define RK3588_VP3_CTRL_BASE 0x0F00 #define RK3568_VP_DSP_CTRL 0x00 #define RK3568_VP_MIPI_CTRL 0x04 #define RK3568_VP_COLOR_BAR_CTRL 0x08 +#define RK3588_VP_CLK_CTRL 0x0C #define RK3568_VP_3D_LUT_CTRL 0x10 #define RK3568_VP_3D_LUT_MST 0x20 #define RK3568_VP_DSP_BG 0x2C @@ -264,6 +295,17 @@ enum dst_factor_mode { #define RK3568_SMART_DLY_NUM 0x6F8 /* Cluster register definition, offset relative to window base */ +#define RK3568_CLUSTER0_CTRL_BASE 0x1000 +#define RK3568_CLUSTER1_CTRL_BASE 0x1200 +#define RK3588_CLUSTER2_CTRL_BASE 0x1400 +#define RK3588_CLUSTER3_CTRL_BASE 0x1600 +#define RK3568_ESMART0_CTRL_BASE 0x1800 +#define RK3568_ESMART1_CTRL_BASE 0x1A00 +#define RK3568_SMART0_CTRL_BASE 0x1C00 +#define RK3568_SMART1_CTRL_BASE 0x1E00 +#define RK3588_ESMART2_CTRL_BASE 0x1C00 +#define RK3588_ESMART3_CTRL_BASE 0x1E00 + #define RK3568_CLUSTER_WIN_CTRL0 0x00 #define RK3568_CLUSTER_WIN_CTRL1 0x04 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10 @@ -357,13 +399,18 @@ enum dst_factor_mode { #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) +#define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10) #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) +#define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8) #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) +#define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2) +#define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0) + #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) @@ -382,11 +429,37 @@ enum dst_factor_mode { #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) +#define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) +#define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(20, 20) +#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX GENMASK(19, 18) +#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX GENMASK(17, 16) +#define RK3588_SYS_DSP_INFACE_EN_DP1_MUX GENMASK(15, 14) +#define RK3588_SYS_DSP_INFACE_EN_DP0_MUX GENMASK(13, 12) +#define RK3588_SYS_DSP_INFACE_EN_DPI GENMASK(9, 8) +#define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7) +#define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6) +#define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5) +#define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4) +#define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3) +#define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2) +#define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1) +#define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0) + +#define RK3588_DSP_IF_MIPI1_PCLK_DIV GENMASK(27, 26) +#define RK3588_DSP_IF_MIPI0_PCLK_DIV GENMASK(25, 24) +#define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV GENMASK(22, 22) +#define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV GENMASK(21, 20) +#define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV GENMASK(18, 18) +#define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV GENMASK(17, 16) + #define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) #define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) #define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) +#define RK3588_DSP_IF_POL__DP1_PIN_POL GENMASK(14, 12) +#define RK3588_DSP_IF_POL__DP0_PIN_POL GENMASK(10, 8) + #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) @@ -408,8 +481,12 @@ enum dst_factor_mode { #define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) #define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) #define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) +#define RK3588_OVL_PORT_SEL__ESMART3 GENMASK(31, 30) +#define RK3588_OVL_PORT_SEL__ESMART2 GENMASK(29, 28) #define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) #define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) +#define RK3588_OVL_PORT_SEL__CLUSTER3 GENMASK(23, 22) +#define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20) #define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) #define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) #define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) @@ -422,6 +499,10 @@ enum dst_factor_mode { #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) +#define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0) + +#define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0) + #define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) #define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) #define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 2c45d81983a5..275d265891db 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -34,6 +34,30 @@ static const uint32_t formats_cluster[] = { DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */ }; +static const uint32_t formats_esmart[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */ + DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */ + DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */ + DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */ +}; + static const uint32_t formats_rk356x_esmart[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -236,7 +260,188 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { }, }; +static const struct vop2_video_port_data rk3588_vop_video_ports[] = { + { + .id = 0, + .feature = VOP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len = 1024, + .cubic_lut_len = 9 * 9 * 9, /* 9x9x9 */ + .max_output = { 4096, 2304 }, + /* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */ + .pre_scan_max_dly = { 76, 65, 65, 54 }, + .offset = 0xc00, + }, { + .id = 1, + .feature = VOP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len = 1024, + .cubic_lut_len = 729, /* 9x9x9 */ + .max_output = { 4096, 2304 }, + .pre_scan_max_dly = { 76, 65, 65, 54 }, + .offset = 0xd00, + }, { + .id = 2, + .feature = VOP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len = 1024, + .cubic_lut_len = 17 * 17 * 17, /* 17x17x17 */ + .max_output = { 4096, 2304 }, + .pre_scan_max_dly = { 52, 52, 52, 52 }, + .offset = 0xe00, + }, { + .id = 3, + .gamma_lut_len = 1024, + .max_output = { 2048, 1536 }, + .pre_scan_max_dly = { 52, 52, 52, 52 }, + .offset = 0xf00, + }, +}; + +/* + * rk3588 vop with 4 cluster, 4 esmart win. + * Every cluster can work as 4K win or split into two win. + * All win in cluster support AFBCD. + * + * Every esmart win and smart win support 4 Multi-region. + * + * Scale filter mode: + * + * * Cluster: bicubic for horizontal scale up, others use bilinear + * * ESmart: + * * nearest-neighbor/bilinear/bicubic for scale up + * * nearest-neighbor/bilinear/average for scale down + * + * AXI Read ID assignment: + * Two AXI bus: + * AXI0 is a read/write bus with a higher performance. + * AXI1 is a read only bus. + * + * Every window on a AXI bus must assigned two unique + * read id(yrgb_id/uv_id, valid id are 0x1~0xe). + * + * AXI0: + * Cluster0/1, Esmart0/1, WriteBack + * + * AXI 1: + * Cluster2/3, Esmart2/3 + * + */ +static const struct vop2_win_data rk3588_vop_win_data[] = { + { + .name = "Cluster0-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER0, + .base = 0x1000, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 0, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .type = DRM_PLANE_TYPE_PRIMARY, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Cluster1-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER1, + .base = 0x1200, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 1, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Cluster2-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER2, + .base = 0x1400, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 4, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Cluster3-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER3, + .base = 0x1600, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 5, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Esmart0-win0", + .phys_id = ROCKCHIP_VOP2_ESMART0, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .base = 0x1800, + .layer_sel_id = 2, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, { + .name = "Esmart1-win0", + .phys_id = ROCKCHIP_VOP2_ESMART1, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .base = 0x1a00, + .layer_sel_id = 3, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, { + .name = "Esmart2-win0", + .phys_id = ROCKCHIP_VOP2_ESMART2, + .base = 0x1c00, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .layer_sel_id = 6, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, { + .name = "Esmart3-win0", + .phys_id = ROCKCHIP_VOP2_ESMART3, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .base = 0x1e00, + .layer_sel_id = 7, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, +}; + static const struct vop2_data rk3566_vop = { + .feature = VOP2_FEATURE_HAS_SYS_GRF, .nr_vps = 3, .max_input = { 4096, 2304 }, .max_output = { 4096, 2304 }, @@ -247,6 +452,7 @@ static const struct vop2_data rk3566_vop = { }; static const struct vop2_data rk3568_vop = { + .feature = VOP2_FEATURE_HAS_SYS_GRF, .nr_vps = 3, .max_input = { 4096, 2304 }, .max_output = { 4096, 2304 }, @@ -256,6 +462,18 @@ static const struct vop2_data rk3568_vop = { .soc_id = 3568, }; +static const struct vop2_data rk3588_vop = { + .feature = VOP2_FEATURE_HAS_SYS_GRF | VOP2_FEATURE_HAS_VO1_GRF | + VOP2_FEATURE_HAS_VOP_GRF | VOP2_FEATURE_HAS_SYS_PMU, + .nr_vps = 4, + .max_input = { 4096, 4320 }, + .max_output = { 4096, 4320 }, + .vp = rk3588_vop_video_ports, + .win = rk3588_vop_win_data, + .win_size = ARRAY_SIZE(rk3588_vop_win_data), + .soc_id = 3588, +}; + static const struct of_device_id vop2_dt_match[] = { { .compatible = "rockchip,rk3566-vop", @@ -263,6 +481,9 @@ static const struct of_device_id vop2_dt_match[] = { }, { .compatible = "rockchip,rk3568-vop", .data = &rk3568_vop, + }, { + .compatible = "rockchip,rk3588-vop", + .data = &rk3588_vop }, { }, }; From patchwork Thu Dec 7 08:02:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751292 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="G8VAugyK" Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DA2F8D73; Thu, 7 Dec 2023 00:03:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=7UFyQ nQVsJKLgpuqB6gs/J3SwmQuFN9FeaP3Q+gt1XU=; b=G8VAugyK9D+MyPFxsb/wp Etmzjr3j3nPcTOMUg64aQaK0CpQ320uNuGCy/frwAIIV8DyF4TgI3XSQBaJkXbUR wqyzvd9k24Xfn0ERbQtMqg6KWbTZEbawRCl31jbMmeoX3cbVK6WtTsUbOmWqo6Tp +KmOa9dhKw8fgt9lyT2EH4= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g4-0 (Coremail) with SMTP id _____wBn7wEDfHFlxFycEw--.44530S2; Thu, 07 Dec 2023 16:02:15 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan Subject: [PATCH v4 13/17] drm/rockchip: vop2: rename VOP_FEATURE_OUTPUT_10BIT to VOP2_VP_FEATURE_OUTPUT_10BIT Date: Thu, 7 Dec 2023 16:02:10 +0800 Message-Id: <20231207080210.652594-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wBn7wEDfHFlxFycEw--.44530S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxAF48CF4UCw4DAry7WFy3Jwb_yoW5ury7pa 9xAryjvrW8Cr4aqw4DXFZxZFs0y3ZxCayIka17K3W7JFy3Kr1DWFsF93W8Ary3Jry7uFWY krsrX34UJF42qr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jw4SOUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEgk-XmVOA0W9dgAAsc From: Andy Yan VOP2 has multiple independent video ports with different feature, so rename VOP_FEATURE_OUTPUT_10BIT to VOP2_VP_FEATURE_OUTPUT_10BIT for more clearly meaning. Signed-off-by: Andy Yan Reviewed-by: Sascha Hauer --- (no changes since v1) drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 2 +- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index edca7723335f..2b996f1a25ad 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1995,7 +1995,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, return; if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && - !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) + !(vp_data->feature & VOP2_VP_FEATURE_OUTPUT_10BIT)) out_mode = ROCKCHIP_OUT_MODE_P888; else out_mode = vcstate->output_mode; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h index 2763e54350a9..615a16196aff 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -11,7 +11,7 @@ #include #include "rockchip_drm_vop.h" -#define VOP_FEATURE_OUTPUT_10BIT BIT(0) +#define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0) #define VOP2_FEATURE_HAS_SYS_GRF BIT(0) #define VOP2_FEATURE_HAS_VO0_GRF BIT(1) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 275d265891db..48170694ac6b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -136,7 +136,7 @@ static const uint64_t format_modifiers_afbc[] = { static const struct vop2_video_port_data rk3568_vop_video_ports[] = { { .id = 0, - .feature = VOP_FEATURE_OUTPUT_10BIT, + .feature = VOP2_VP_FEATURE_OUTPUT_10BIT, .gamma_lut_len = 1024, .cubic_lut_len = 9 * 9 * 9, .max_output = { 4096, 2304 }, @@ -263,7 +263,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { static const struct vop2_video_port_data rk3588_vop_video_ports[] = { { .id = 0, - .feature = VOP_FEATURE_OUTPUT_10BIT, + .feature = VOP2_VP_FEATURE_OUTPUT_10BIT, .gamma_lut_len = 1024, .cubic_lut_len = 9 * 9 * 9, /* 9x9x9 */ .max_output = { 4096, 2304 }, @@ -272,7 +272,7 @@ static const struct vop2_video_port_data rk3588_vop_video_ports[] = { .offset = 0xc00, }, { .id = 1, - .feature = VOP_FEATURE_OUTPUT_10BIT, + .feature = VOP2_VP_FEATURE_OUTPUT_10BIT, .gamma_lut_len = 1024, .cubic_lut_len = 729, /* 9x9x9 */ .max_output = { 4096, 2304 }, @@ -280,7 +280,7 @@ static const struct vop2_video_port_data rk3588_vop_video_ports[] = { .offset = 0xd00, }, { .id = 2, - .feature = VOP_FEATURE_OUTPUT_10BIT, + .feature = VOP2_VP_FEATURE_OUTPUT_10BIT, .gamma_lut_len = 1024, .cubic_lut_len = 17 * 17 * 17, /* 17x17x17 */ .max_output = { 4096, 2304 }, From patchwork Thu Dec 7 08:02:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 751290 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="TfUvT0RU" Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A40621715; Thu, 7 Dec 2023 00:03:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=Eagjj KWNWKSpKBM+wTEZQyp+boVbVHbVzJJ39PCuk0M=; b=TfUvT0RUFYc7U2/AlB+F5 UFEjE8ZxIUvKFTTlvaIjLSSd5yLel5Jek3mV1A833tuQNQkFRyizA1xoAYACBvzx ng4IYufs223SmaK8LluDXg0ozVxzHLEE4PXq6eGZ0+3LZc1Lg54jmxsI7oOuV+b4 DTT0vhR4f8h5Mkgv0S7qYE= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g4-0 (Coremail) with SMTP id _____wD3_wsefHFlU2WcEw--.43577S2; Thu, 07 Dec 2023 16:02:41 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan Subject: [PATCH v4 15/17] dt-bindings: iommu: rockchip: Add Rockchip RK3588 Date: Thu, 7 Dec 2023 16:02:35 +0800 Message-Id: <20231207080235.652719-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231207075906.651771-1-andyshrk@163.com> References: <20231207075906.651771-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wD3_wsefHFlU2WcEw--.43577S2 X-Coremail-Antispam: 1Uf129KBjvdXoWrKF45ZrW7uFyDKrWfAryxKrg_yoWDJrX_C3 WxZw45XF4rtFWF93WDA3yfGFyDCw42kr1kXa9YkF1vya4q9rykKr93J34rAr4rWr47uF9a 93WS9ry3WF9xGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7IU8KFAPUUUUU== X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBEgM-XmVOA0XAIwAAs+ From: Andy Yan Add a Rockchip RK3588 compatible Signed-off-by: Andy Yan Reviewed-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski --- Changes in v4: - Add const for rockchip,rk3588-iommu compatible .../devicetree/bindings/iommu/rockchip,iommu.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml index ba9124f721f1..621dde0e45d8 100644 --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml @@ -19,9 +19,14 @@ description: |+ properties: compatible: - enum: - - rockchip,iommu - - rockchip,rk3568-iommu + oneOf: + - enum: + - rockchip,iommu + - rockchip,rk3568-iommu + - items: + - enum: + - rockchip,rk3588-iommu + - const: rockchip,rk3568-iommu reg: items: