From patchwork Mon Aug 26 20:43:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 172200 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4862454ily; Mon, 26 Aug 2019 13:44:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkdESGDh1RL8NB4WCBRY/Jot0IfUmE37n3IWw9NFfVpI0BHJ49NHj31Pu3XOrcSHrrz9EZ X-Received: by 2002:a17:902:720a:: with SMTP id ba10mr19127155plb.231.1566852285600; Mon, 26 Aug 2019 13:44:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566852285; cv=none; d=google.com; s=arc-20160816; b=Z2toU9Px6UrAoxxZFsl9JPrBMXbKtUoP8km62Qmvf50foU8tP3Lwyl1lYHK9fDzVbi LY/y9ZvRKJ5pVwo0nnpfqpkeYb80AwrVr8vCHRS/xTVp84eTz/ZbaS21vIpd0/sAck82 bFO59qVKUkVnQh8QcgchhzURl4ZA+1MNvQsxH2NZM7rHIFv3CCX+A+4cCV69X3OoV0TZ vKJk4te/mvQhYi4ZQXOTluBg7+IiJRNhUrPo73PXC7FqQ/JCXbQ8jq9FoZ7G8d4J7jf9 VE7ow8aEm4M5L8VU15z7mAf1kLHE+UK5A8aK+ZL9Xb9kSv6mcER+xpLJbJj1VJJXNJNJ Pfiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Fw7X0u9RSVpb9YP6GvJgpnhL1eZP3GnuovkdNKVahNQ=; b=MjOu69/XMzGUWs/8xvtze67eGSue+B135haBedltBqTtvrMZXHwv4EcTQKf+vZgfGV CVaSzKtsPY3qWn6wJj06INEroHCsEwQ/9VeTHxdDwYvVQ+jB4lXFSJq2G8CgbplQ8igy aD0oN2IysObaII/UU0Rmk+TPl2syQtwXS0jXiNsdEmb5D1iQr1RYZFIYfC2oX8RU6k+h UrjS3prWJViEJ/5UwfpvZCVJHx7paTPIumHbrhFEAjrjAHPH3WDh7vPqXhXmP6gjzHaq 2fxuCCqDXCjh6phCWIjSVFOL4Zqp3D1qVMHl6FHuPBZriUqx0XOwu7D5AMJ5kMGhQf8Y jS4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l6sh4qDy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k12si10392636plt.92.2019.08.26.13.44.45; Mon, 26 Aug 2019 13:44:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l6sh4qDy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730424AbfHZUoo (ORCPT + 8 others); Mon, 26 Aug 2019 16:44:44 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:45817 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730439AbfHZUoo (ORCPT ); Mon, 26 Aug 2019 16:44:44 -0400 Received: by mail-wr1-f68.google.com with SMTP id q12so16555120wrj.12 for ; Mon, 26 Aug 2019 13:44:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fw7X0u9RSVpb9YP6GvJgpnhL1eZP3GnuovkdNKVahNQ=; b=l6sh4qDylt4FBGKZbeZbgdchgf+Ftcthdvk7xzUqt1v1xshu0jydYLG40UO/b9oXc4 qsqbemoS4PVcuf0R1a+fcHbHXAJQe9PO5cq8UIcT7hRO8CxZSTmign0nSdfQhUu7fiZs Ms4ELGQ8eo5W1GDUT3mW3f57i3861kIE7zKLLD814esraGpUpxp8a1SNweInJCPEGwy6 oD0q5ysgRBsCv1Qtksz98fu14zSZCdrq1hvnkz2RGUf5Oq3tqjIN2Rq4CGqrB20NHFwl UN4pC8rK2b/aqkRqY8aVpzUxULN2VbdJ1xSSPUls0YzvKhNNNg9ogsc4C72ylII9owiF IMXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fw7X0u9RSVpb9YP6GvJgpnhL1eZP3GnuovkdNKVahNQ=; b=i8rAABvgeqSS/A6Ua+8700Djog82lOIvnYykGU0utRCcyv6z63loz6rDrrrqs06f/c PNbYWUCIQ3/e56drfaEnWTKGMi/IDJdqxQ33LBbREMBaResEUF96N6yYNtiufAFPVPoQ QvYxiomJwaTE1ER49/fozhwB6un1zsLq52uIFg2iSLeDh5cNxGjphHlwG0CrBm2qRHVD ZCwxoiwfQ2mZECON1u7mnWCpVV1iqzmVUVWzy/pmOd6OrTYpspl/THd97+8ZLYmQKILn uBBdYlnoOB/M2TQdmRw8o1dFfSxOyiQrA/37TO+sSZqhaGTTK/iztLWMLjrxaZ5X+7Cx +ZPA== X-Gm-Message-State: APjAAAV2QxGlPDiDIzox/tCGQv5gESPo1bGqCBHz6kGm3wIjXn5mLR3I uhkjykrvPLB0X0Enu8/bhOHGbw== X-Received: by 2002:a5d:6a45:: with SMTP id t5mr23996401wrw.228.1566852281822; Mon, 26 Aug 2019 13:44:41 -0700 (PDT) Received: from mai.imgcgcw.net ([2a01:e34:ed2f:f020:f881:f5ed:b15d:96ab]) by smtp.gmail.com with ESMTPSA id 20sm549557wmk.34.2019.08.26.13.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 13:44:41 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Allwinner sunXi SoC support) Subject: [PATCH 02/20] dt-bindings: timer: Convert Allwinner A10 Timer to a schema Date: Mon, 26 Aug 2019 22:43:49 +0200 Message-Id: <20190826204407.17759-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org> References: <20190826204407.17759-1-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Maxime Ripard The older Allwinner SoCs have a Timer supported in Linux, with a matching Device Tree binding. While the original binding only mentions one interrupt, the timer actually has 6 of them. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../timer/allwinner,sun4i-a10-timer.yaml | 76 +++++++++++++++++++ .../bindings/timer/allwinner,sun4i-timer.txt | 19 ----- 2 files changed, 76 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml new file mode 100644 index 000000000000..7292a424092c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Timer Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + enum: + - allwinner,sun4i-a10-timer + - allwinner,suniv-f1c100s-timer + + reg: + maxItems: 1 + + interrupts: + description: + List of timers interrupts + + clocks: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + items: + const: allwinner,sun4i-a10-timer + + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + items: + const: allwinner,suniv-f1c100s-timer + + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x400>; + interrupts = <22>, + <23>, + <24>, + <25>, + <67>, + <68>; + clocks = <&osc>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt deleted file mode 100644 index 3da9d515c03a..000000000000 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +++ /dev/null @@ -1,19 +0,0 @@ -Allwinner A1X SoCs Timer Controller - -Required properties: - -- compatible : should be one of the following: - "allwinner,sun4i-a10-timer" - "allwinner,suniv-f1c100s-timer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer -- clocks: phandle to the source clock (usually a 24 MHz fixed clock) - -Example: - -timer { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x400>; - interrupts = <22>; - clocks = <&osc>; -}; From patchwork Mon Aug 26 20:43:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 172202 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4862575ily; Mon, 26 Aug 2019 13:44:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzGe2Umo8LX2VAIr8EYXSJ161oh6uj2lOKWW8BqLQJyKJOHv/Ddy372uzgsvrSyBUtm1Je+ X-Received: by 2002:a62:e910:: with SMTP id j16mr22811138pfh.123.1566852291979; Mon, 26 Aug 2019 13:44:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566852291; cv=none; d=google.com; s=arc-20160816; b=gpSTYkbkBRswT/84AhOvwONbKRB0H8W6jUir82VMQJQeALYwhH+xAASyFGlLTH1bAx g7SHFjOPiV97+zXmVSap0jS4yXI1evMSyyAI/tGTPchT6YB1uPFcJPwUTNO1fE1UXu8z Hi3l0C+cNS5zffQhDoIj+ysV1Qj6aFcfnVYsZOnX08GS5Zm3r3aDhPAj4rZGBJRwh2X7 GDFBVBlnkaf/lyI8XNTIQbjMJ80uQQe0QqZjDsfWAQoPTk2FBP4JUJEteTDBuwEs3z0C UqctQEF+Tc6di6hZdR8eS78swxy13Swe9nsE3mbuxQX+HQyN1jaze+4MXbfJkpb8n4H0 wv3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=SZT7LwQ4zVm6UpU1R0QaKTwCzMI6AEH9QZz6xkZt/VY=; b=cMD5hKVscJbAA/4pED1zIDKB9/+42N3e0pqZphjf8Nmj30DfUntkFhvwjzpO5AvR9a 9cHeqdGzfAerP12YknULcsmgtteINcu7DBb0TCP+PCmZmV+vOYUYZ3RHWnQNEaZCYV+n 0HPBOvAm5LRavax1CNYCqXUSs+6pyoZBfm3Z+amAvMFQLZFTHDyPc9932Q+C+oeKB7IZ WKUhT2bCpVkto13mvtj/cGbx9YYRv7QD6VvkgL49ORgMpQ3c4sDiBvf5sRl8W4B9JT1L kXVZLKVx0g3MO6HdoXMjkB7Id3+WHV4100i7dlKtBOb3mwvYAcpd7J9YLrtLQoDcBpvC wj5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SOVljHUU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 89si11180047plb.213.2019.08.26.13.44.51; Mon, 26 Aug 2019 13:44:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SOVljHUU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730634AbfHZUou (ORCPT + 8 others); Mon, 26 Aug 2019 16:44:50 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:43979 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730446AbfHZUou (ORCPT ); Mon, 26 Aug 2019 16:44:50 -0400 Received: by mail-wr1-f65.google.com with SMTP id y8so16572282wrn.10 for ; Mon, 26 Aug 2019 13:44:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SZT7LwQ4zVm6UpU1R0QaKTwCzMI6AEH9QZz6xkZt/VY=; b=SOVljHUU8N7UbYj/cOCqgEomKmgW/J60GyZGE8TlJHFlEQP3S8H5JbmKJRln4V8uTH 1wmjcjxn/otSmTYMMbHHqk9cpXO+iunSYYqnkeDJFnZrbagQOcDvaYvDvTSuCkGdobYH yPdEdjfRf6YWiDbWw1rcR4Xbnt+xZQDzSLOJ8+NCTjg8G6U1uArrZc6VWR7N2eiz78O8 OLrmN2VVwjDWJN9bIz+7NwHo+JPHDfW9WOQ/cQXIiT4ozFmPGQjrtNYzUU9q0dF2RvPz fmrQAxhgz9q1XKjICu+OBZQTaq9AJl3SQ+jbS2GjyferSwq0iMEqajyG2HyIPnOs0OVR eKZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SZT7LwQ4zVm6UpU1R0QaKTwCzMI6AEH9QZz6xkZt/VY=; b=a9UqpWy7/RnrTE9+LZzBecWXIS8+EWqF3AY0sSOaNJnRM1z9uvQfDNohACoVE5L0eD t7GRGu7c9YkavZ1WzEP0OzlKrgo6Sq8GylWDkGH5OdUvouuTE1mgYeXryGbNv0hcQHRH cYJqmMsNm8i97wmXhXZQdw5JRKs2scVoItSlOb35ygzCG3B5lQPMus0YGFE5yxTECpir cWVCGMLU0V7nYE4KKG79ZMaPWc4PV4jZiJj/vMAZll9aVeQ/triHnUSjjYwD9dDiX6yW eSNYIARYYWo2EZsT68QsUbivsLeN7fcHQ+RzIfmxlNTeI86fU2dkh0X8tdGDFVyBvvWy 807g== X-Gm-Message-State: APjAAAU1dhzioLhERHNsufSkt2k+NRRMtDYk8XRhZndqWy3rf7FR/Qah GBhY6F9Gc+Ve8Pn8XHcNDKysf1MeZOQ= X-Received: by 2002:adf:e5cd:: with SMTP id a13mr23978628wrn.316.1566852288125; Mon, 26 Aug 2019 13:44:48 -0700 (PDT) Received: from mai.imgcgcw.net ([2a01:e34:ed2f:f020:f881:f5ed:b15d:96ab]) by smtp.gmail.com with ESMTPSA id 20sm549557wmk.34.2019.08.26.13.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 13:44:47 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Allwinner sunXi SoC support) Subject: [PATCH 05/20] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema Date: Mon, 26 Aug 2019 22:43:52 +0200 Message-Id: <20190826204407.17759-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org> References: <20190826204407.17759-1-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Maxime Ripard The newer Allwinner SoCs have a High Speed Timer supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../timer/allwinner,sun5i-a13-hstimer.txt | 26 ------ .../timer/allwinner,sun5i-a13-hstimer.yaml | 79 +++++++++++++++++++ 2 files changed, 79 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt deleted file mode 100644 index 2c5c1be78360..000000000000 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +++ /dev/null @@ -1,26 +0,0 @@ -Allwinner SoCs High Speed Timer Controller - -Required properties: - -- compatible : should be "allwinner,sun5i-a13-hstimer" or - "allwinner,sun7i-a20-hstimer" -- reg : Specifies base physical address and size of the registers. -- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i - one) -- clocks: phandle to the source clock (usually the AHB clock) - -Optional properties: -- resets: phandle to a reset controller asserting the timer - -Example: - -timer@1c60000 { - compatible = "allwinner,sun7i-a20-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <0 51 1>, - <0 52 1>, - <0 53 1>, - <0 54 1>; - clocks = <&ahb1_gates 19>; - resets = <&ahb1rst 19>; -}; diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml new file mode 100644 index 000000000000..dfa0c41fd261 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A13 High-Speed Timer Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + oneOf: + - const: allwinner,sun5i-a13-hstimer + - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun6i-a31-hstimer + - const: allwinner,sun7i-a20-hstimer + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 4 + items: + - description: Timer 0 Interrupt + - description: Timer 1 Interrupt + - description: Timer 2 Interrupt + - description: Timer 3 Interrupt + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +if: + properties: + compatible: + items: + const: allwinner,sun5i-a13-hstimer + +then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +else: + properties: + interrupts: + minItems: 4 + maxItems: 4 + +additionalProperties: false + +examples: + - | + timer@1c60000 { + compatible = "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <0 51 1>, + <0 52 1>, + <0 53 1>, + <0 54 1>; + clocks = <&ahb1_gates 19>; + resets = <&ahb1rst 19>; + }; + +... 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[209.132.180.67]) by mx.google.com with ESMTP id c1si10944517pld.348.2019.08.26.13.45.17; Mon, 26 Aug 2019 13:45:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="N/2V0MqH"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731504AbfHZUpQ (ORCPT + 8 others); Mon, 26 Aug 2019 16:45:16 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:35165 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731426AbfHZUpP (ORCPT ); Mon, 26 Aug 2019 16:45:15 -0400 Received: by mail-wm1-f65.google.com with SMTP id l2so802808wmg.0 for ; Mon, 26 Aug 2019 13:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/ZJzCcrxyM6IhpQ4LAj7ILikjbYfCQse07WeYUJxBzQ=; b=N/2V0MqH6uUI/PbxTsOZSQz+Zpd9bK7VVLZF1nDiWA5rmBkVk3yrJlFKYKLuN396Ob DnKPxf6Q8D67GuonmhDcsrAVB78c77v3BzfCJplIhghjNQwnE6pws4mcPXspmlYD9gTJ lcVvxT/mdxt7j6SUtlTBsFYLuqGaPqznF7AQ2IEuzytDfwxxZIrpsvfPQKZPzwNsozqi 5BKGruFUKPJbUcsoQ5/2Rm9X8qM8ylIl66YhKCOQV1CHbVbL6jp5VeLv0KbCzwfWdr/o +dnDRBv2oipFUPIKFUgDHl3UsL8WB7AzC6oapi/gMiGuZTbtfDxychKGfnLgkbuCP3Fa joVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/ZJzCcrxyM6IhpQ4LAj7ILikjbYfCQse07WeYUJxBzQ=; b=YTbDfUOnXoUY9DgXoV12X8nS+3dsOqtQgls1LXBgw7RGR6grYE8N0FR9cRx1PVcgIU JnD6R7F5PyM8FZ1Eec8kHLuWxTcmiRfaQbL0HO/ifNv5Yn7shmMlq3PzxutDhx1FPU2r I78tBK+Y3D1GNkO9LGy9/sZV7TdOThqzM5joXiIJhSi64/gk3u9VsCcLO/TwIc/DJ+s7 Ye0rtEz4U71F5eXZiqFw1i4MZr5lLDH5t8BM48Hi0OKeaz+wzUji+/PArCa6+XWKqfRn 9ICR+QF+FNZPpIJqdp285OP21QLMwhhfJ5i0gcTqU1ASCh0mZy9mSn1RU78lWC7qx/jJ Ea/w== X-Gm-Message-State: APjAAAUayzcRXlZjfPsJ28bhBJN+WnKehMK2tqcR57qjzt5iHPoxbYSa w5hvCMSRdYlz1lXX7/LC8fIRsw== X-Received: by 2002:a1c:7606:: with SMTP id r6mr23209536wmc.118.1566852313866; Mon, 26 Aug 2019 13:45:13 -0700 (PDT) Received: from mai.imgcgcw.net ([2a01:e34:ed2f:f020:f881:f5ed:b15d:96ab]) by smtp.gmail.com with ESMTPSA id 20sm549557wmk.34.2019.08.26.13.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 13:45:13 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 15/20] dt-bindings: timer: renesas, cmt: Update CMT1 on sh73a0 and r8a7740 Date: Mon, 26 Aug 2019 22:44:02 +0200 Message-Id: <20190826204407.17759-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org> References: <20190826204407.17759-1-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Magnus Damm This patch reworks the DT binding documentation for the 6-channel 48-bit CMTs known as CMT1 on r8a7740 and sh73a0. After the update the same style of DT binding as the rest of the upstream SoCs will now also be used by r8a7740 and sh73a0. The DT binding "cmt-48" is removed from the DT binding documentation, however software support for this deprecated binding will still remain in the CMT driver for some time. Signed-off-by: Magnus Damm Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 45840d475050..a297fca5b61e 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -12,17 +12,10 @@ datasheets. Required Properties: - compatible: must contain one or more of the following: - - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT - (CMT1) - - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT - (CMT1) - - "renesas,cmt-48" for all non-second generation 48-bit CMT - (CMT1 on sh73a0 and r8a7740) - This is a fallback for the above renesas,cmt-48-* entries. - - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4. - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4. - "renesas,r8a7740-cmt0" for the 32-bit CMT0 device included in r8a7740. + - "renesas,r8a7740-cmt1" for the 48-bit CMT1 device included in r8a7740. - "renesas,r8a7740-cmt2" for the 32-bit CMT2 device included in r8a7740. - "renesas,r8a7740-cmt3" for the 32-bit CMT3 device included in r8a7740. - "renesas,r8a7740-cmt4" for the 32-bit CMT4 device included in r8a7740. @@ -59,6 +52,7 @@ Required Properties: - "renesas,r8a77990-cmt0" for the 32-bit CMT0 device included in r8a77990. - "renesas,r8a77990-cmt1" for the 48-bit CMT1 device included in r8a77990. - "renesas,sh73a0-cmt0" for the 32-bit CMT0 device included in sh73a0. + - "renesas,sh73a0-cmt1" for the 48-bit CMT1 device included in sh73a0. - "renesas,sh73a0-cmt2" for the 32-bit CMT2 device included in sh73a0. - "renesas,sh73a0-cmt3" for the 32-bit CMT3 device included in sh73a0. - "renesas,sh73a0-cmt4" for the 32-bit CMT4 device included in sh73a0. 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Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 5b7690ae8b9d..c7fdcb02e083 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -53,6 +53,8 @@ Required Properties: - "renesas,r8a77980-cmt1" for the 48-bit CMT1 device included in r8a77980. - "renesas,r8a77990-cmt0" for the 32-bit CMT0 device included in r8a77990. - "renesas,r8a77990-cmt1" for the 48-bit CMT1 device included in r8a77990. + - "renesas,r8a77995-cmt0" for the 32-bit CMT0 device included in r8a77995. + - "renesas,r8a77995-cmt1" for the 48-bit CMT1 device included in r8a77995. - "renesas,sh73a0-cmt0" for the 32-bit CMT0 device included in sh73a0. - "renesas,sh73a0-cmt1" for the 48-bit CMT1 device included in sh73a0. - "renesas,sh73a0-cmt2" for the 32-bit CMT2 device included in sh73a0. From patchwork Mon Aug 26 20:44:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 172212 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4863186ily; Mon, 26 Aug 2019 13:45:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqxRcY9Q7mJfccHWrfK48Igry5ibMqusdQ4z5vYHQOqA0WF/p67QOHFlAw5laZaYL3pw4ecB X-Received: by 2002:a17:90a:256f:: with SMTP id j102mr22590562pje.14.1566852325161; Mon, 26 Aug 2019 13:45:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566852325; cv=none; d=google.com; s=arc-20160816; b=Ctjfs1Smli95n0UGMabXJyIeLYGx1lB7606pKgbhXvUj8KzVeBgwWLa7n/bbegopxM 6p7n4UHSyDN2O1Rk4EGg3kXmM3q6Dgr4gW9uiGe4vJz0QNshQWsJ37VQ9iNLKtKevxSP ZZUuseaoA05T+GaD+deXWeLukMd0PaKw9zxRP7iacuaiMylhheFc0v5s1UYMGTRlHQcj MCujG7QUw10Clohtkqgx1u9OVGVI+6JBEtFM7U4tre3OcM6aIsCuoMGznY99JFJFrtxX rFnyJxH7CRjfUgOW2n8qm0EhE2EnBQQmXPTaJReDmKRWvOSrAzeqm6ThguLjDz44j6kc yHXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=iM5BJyr4mn2hoXsP74QtrPoZacw8VcD7wJN6v4Wcvr4=; b=RvG31Y9OcHbyPABlKssFTmcAQGHtRYsHkFETdJTOddpWVlYv2eFWeoHkLt92kADnYH 4TL7zJlT6kp0GFJrSrbPM8yB6GHH21CYoxMpXLu3/fTtWxnLwSVzne0Wdbhn/AiLiI3E FlNGyptqNCUt8JapApOF2z0lAi40QEuOEAOqcK2GSQPifnHkU2dQ0EkQ/cQ4MjC3bjVv prSpp5KBNSzI/4c0PNA43wvaDVjU0D32tnhO3UWcDFZCd7llR7xeTjS1c5o2deyqTLQJ 7wM9HNvkKFxVqOtyViCG2nVqSmqiffeOzLIk+1dqJWe0fP699umcympe2rdGRusCt77R wLzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rWec3DHj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 200si11665105pfu.152.2019.08.26.13.45.24; Mon, 26 Aug 2019 13:45:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rWec3DHj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731462AbfHZUpX (ORCPT + 8 others); Mon, 26 Aug 2019 16:45:23 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:40791 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731686AbfHZUpX (ORCPT ); Mon, 26 Aug 2019 16:45:23 -0400 Received: by mail-wr1-f68.google.com with SMTP id c3so16580268wrd.7 for ; Mon, 26 Aug 2019 13:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iM5BJyr4mn2hoXsP74QtrPoZacw8VcD7wJN6v4Wcvr4=; b=rWec3DHjN+OMnET4cKmo5FTJ6PFPh0M+ViJ5jsHArDp2zJwNheWC7MfsSfeZTTYG1O 5SW1JyjSC9PBd9qZWv6F8J886PzxO+t2xf9zRMNLybWHuAqu7SMm25HWvPVxbaCfuN7j mhlWUrDtsqDVWoBx734i8qMKJdwQqSUMIwhlpuL5QKbLTnbQsB2iPESMmcgumx0Zwp5c B0/osc7Lr80E3LBy8Ku57OQ3pvp3ZDrXGfTcUxG7H4lCfBFYN9HpArY0uO9rFV0jT7tc uhrPKQ6BjAV1OnlYzfoGAGNbGjpaKtMcdL0xRac+Ik8b8MiX9cZAi0arykL6wgFEWNi7 JIFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iM5BJyr4mn2hoXsP74QtrPoZacw8VcD7wJN6v4Wcvr4=; b=ONxxVqro/MokYJD9ClV9pOStxI7Mmh51iKZYROXOkNr3vprRuZGatpHu2rKi7VQcal IEoUBb6m8axheOzPLk4mSSQJfUSTpQddOA0u67RRverF0+ddqwSO97gTHnU10Yn46ksa JPL9rJqyChG51mEzbsVRlKpSk53u1vJaHW7UUNbutffPRprE8RrGlZ9YQzgVYNmjVS85 U3+qCfNlA48CoIG5lh+pozTFGa7nVMWeOmHK4ZEylGF5bpGE9zEemHFJQvkqZo1t0Z4i di5OpomJ2WpeISlGSNuMFkXggne0uAENwqWBUFpY+gW2egBdyDK8gGSDZUZSKksrG6Z+ zoPQ== X-Gm-Message-State: APjAAAWWoVn7R8TlnYwcymTM4lCXWZU9Ov4Jmg2MTqrH5hpZXJupzzdR hchd/lNTvl2P+Ig5evrgUlvalw== X-Received: by 2002:adf:dcc2:: with SMTP id x2mr25391450wrm.295.1566852320844; Mon, 26 Aug 2019 13:45:20 -0700 (PDT) Received: from mai.imgcgcw.net ([2a01:e34:ed2f:f020:f881:f5ed:b15d:96ab]) by smtp.gmail.com with ESMTPSA id 20sm549557wmk.34.2019.08.26.13.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 13:45:19 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 18/20] dt-bindings: timer: renesas, cmt: Update R-Car Gen3 CMT1 usage Date: Mon, 26 Aug 2019 22:44:05 +0200 Message-Id: <20190826204407.17759-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org> References: <20190826204407.17759-1-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Magnus Damm The R-Car Gen3 SoCs so far come with a total for 4 on-chip CMT devices: - CMT0 - CMT1 - CMT2 - CMT3 CMT0 includes two rather basic 32-bit timer channels. The rest of the on-chip CMT devices support 48-bit counters and have 8 channels each. Based on the data sheet information "CMT2/3 are exactly same as CMT1" it seems that CMT2 and CMT3 now use the CMT1 compat string in the DTSI. Clarify this in the DT binding documentation by describing R-Car Gen3 and RZ/G2 CMT1 as "48-bit CMT devices". Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index c7fdcb02e083..a444cfc5852a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -28,9 +28,9 @@ Required Properties: - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470. - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. - - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1. + - "renesas,r8a774a1-cmt1" for the 48-bit CMT devices included in r8a774a1. - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0. - - "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0. + - "renesas,r8a774c0-cmt1" for the 48-bit CMT devices included in r8a774c0. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. @@ -42,19 +42,19 @@ Required Properties: - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. - "renesas,r8a7795-cmt0" for the 32-bit CMT0 device included in r8a7795. - - "renesas,r8a7795-cmt1" for the 48-bit CMT1 device included in r8a7795. + - "renesas,r8a7795-cmt1" for the 48-bit CMT devices included in r8a7795. - "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796. - - "renesas,r8a7796-cmt1" for the 48-bit CMT1 device included in r8a7796. + - "renesas,r8a7796-cmt1" for the 48-bit CMT devices included in r8a7796. - "renesas,r8a77965-cmt0" for the 32-bit CMT0 device included in r8a77965. - - "renesas,r8a77965-cmt1" for the 48-bit CMT1 device included in r8a77965. + - "renesas,r8a77965-cmt1" for the 48-bit CMT devices included in r8a77965. - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970. - - "renesas,r8a77970-cmt1" for the 48-bit CMT1 device included in r8a77970. + - "renesas,r8a77970-cmt1" for the 48-bit CMT devices included in r8a77970. - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980. - - "renesas,r8a77980-cmt1" for the 48-bit CMT1 device included in r8a77980. + - "renesas,r8a77980-cmt1" for the 48-bit CMT devices included in r8a77980. - "renesas,r8a77990-cmt0" for the 32-bit CMT0 device included in r8a77990. - - "renesas,r8a77990-cmt1" for the 48-bit CMT1 device included in r8a77990. + - "renesas,r8a77990-cmt1" for the 48-bit CMT devices included in r8a77990. - "renesas,r8a77995-cmt0" for the 32-bit CMT0 device included in r8a77995. - - "renesas,r8a77995-cmt1" for the 48-bit CMT1 device included in r8a77995. + - "renesas,r8a77995-cmt1" for the 48-bit CMT devices included in r8a77995. - "renesas,sh73a0-cmt0" for the 32-bit CMT0 device included in sh73a0. - "renesas,sh73a0-cmt1" for the 48-bit CMT1 device included in sh73a0. - "renesas,sh73a0-cmt2" for the 32-bit CMT2 device included in sh73a0. @@ -69,7 +69,7 @@ Required Properties: listed above. - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3 and RZ/G2. - - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3 + - "renesas,rcar-gen3-cmt1" for 48-bit CMT devices included in R-Car Gen3 and RZ/G2. These are fallbacks for R-Car Gen3 and RZ/G2 entries listed above.