From patchwork Thu Dec 7 13:06:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751174 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TLh4FkGB" Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C564610CF for ; Thu, 7 Dec 2023 05:07:07 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-50c0f13ea11so729779e87.3 for ; Thu, 07 Dec 2023 05:07:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701954426; x=1702559226; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=TLh4FkGBPNFCOlmVHBuCDYgOkQtnDLuC82lNaertkTOndOCBriygTBHq0Xs+eI0oaG 2mBZ+iUOASuEjlCZFLKuU+yq/v+ROuho5+3XIeyB/kKGvEg6dBV4py/RFZRMFNkpLw71 Rn44jF61KTrJNmzaaA722NQxefrcqC4TnrwrcnkbTWIRJc58hkfqaagzTd6Llnk3ZXev xj7dCEi4NqPn9f6VROJk60q8PK2qN78PdDCYWrR2tOKBhxf2atdwaYaGvXLIS4CVkUFk N4u6Kpfu/3Dg0PL0me8IBzAVPQh/GGGbWTWtWKpNzCLGGjWmWXxNc9h9eco865P7d4Mj +b2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701954426; x=1702559226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=Anr1JprxKe/YBorDLccBGlVdZvMJggqtT2ybQUK3f3kKnflpq0vSLW2eF4KxVtvg2x nZYyRJoZ7C8eMfSGdpv4jyCoy6bImUkfDAX5ATCRYc14daYiys8K60l3Re3+qKTuJPWr taONJkVi/FAMsM/097pyde6L8+88EgVz8GE1G8Cod+OYyMQWkqA1Td6ckdvfD/m5oGNF IblnLjR9j642UI0eGZ3B/lvAxr/7noi3HIzD5ks9rDT/+bokky62+keu5sXGD9SonWGD gC0VG/3upp88DZVwzna/d8BmL9Mvb8pJdqSpLMcH6/0upRI7cbbREIJgLSQXlGi+3ovy gZkg== X-Gm-Message-State: AOJu0Yy7rccgXHTl4aBekpgdULcXtqnWw1O12HZYQbMXNIg/vHMcgp/z t3BIMAx3811qnsWV8hbrvEcRog== X-Google-Smtp-Source: AGHT+IGWVhEt5sgampTn26wevOKIkl4VtpaVT5OrP6q/xHul1q3Upen/SVYuPhcl0phV8oGNXleR1w== X-Received: by 2002:a05:6512:230e:b0:50b:e697:10d5 with SMTP id o14-20020a056512230e00b0050be69710d5mr1558263lfu.68.1701954426048; Thu, 07 Dec 2023 05:07:06 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j21-20020a056512109500b0050bc41caf04sm167685lfg.304.2023.12.07.05.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 05:07:05 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v5 02/10] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Thu, 7 Dec 2023 16:06:55 +0300 Message-Id: <20231207130703.3322321-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> References: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Change the boolean 'regulator' property into a proper regulator description. This breaks schema compatibility for the sake of properly describing the regulator. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 84b3f01d590c..a2d871ba8c45 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,7 +47,7 @@ properties: minItems: 1 regulator: - type: boolean + $ref: /schemas/regulator/regulator.yaml# description: Indicates that this SPM device acts as a regulator device device for the core (CPU or Cache) the SPM is attached to. @@ -96,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... From patchwork Thu Dec 7 13:06:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751172 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Akh1dCwl" Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D20F10E7 for ; Thu, 7 Dec 2023 05:07:08 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50be3eed85aso839316e87.2 for ; Thu, 07 Dec 2023 05:07:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701954427; x=1702559227; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yLKGJjqVnU2Wm3Zgin7pA30JtWvao8SZmntEz34aPKQ=; b=Akh1dCwlDcrtKCApTT6PneXu4s2/ts4uOnJgXeSgMOO7Gcm/QGAYui5JCqQMW4j4o2 ejZLtfD9Od12r+HuUfYr0aGT0ovEPfgyKukji7meP0vgsXRpcUfIoCShYuNwpTg0QWAN buKVg1ELEetLWHHvyKAjrsxBbkuj1jyCt/WUnFMOw+V5Q400ZI10OnkeWxWyDJ7ENnkI 4jscXExq1pcXAH182V49rKCd5llp+j0e4sfQjDZKhDvpDKXiglsJohnSeJNCghLO/bA2 1KmqGogh06u2TNsy+SJ86kYYxq5g1zCGNhk+UfkvPaXmB7GhLwPwOBc2aows+LrMsrnj dIlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701954427; x=1702559227; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yLKGJjqVnU2Wm3Zgin7pA30JtWvao8SZmntEz34aPKQ=; b=d1CjCOpT9TcKf/Y8OfmW3qR0Uci0msgChOTLy7OBLnSW7dc6Dp3Qj+3SG/wlmHzMsX OSMZvEgPBVrSlJuFw/CaLBi45cjzDxsGddNeyzt3/wKaiddF1Hd73ZwSUna3heHSxb1L wxDYtfQZIdPPgguKIT3+ggUCLGrxkbhvnU9j9FtrUN5geEcV2x3Iusv8MDnsFJ1QEKPF Z3lCR0Ce/qwkoCtV/N/5btVC1hTlWYOErm0OxvDW981NJ8Uam5WsvRC7oDCEPU0uDQ+T GLLe/fkJ+9m53KLxjMj/1GAMLkWyI8ixRY8snJ2migakqjBIiH9lLaRGGAyc2tRwTGrs AROA== X-Gm-Message-State: AOJu0YzmqADowPd67DkaZbJYf12XKITpHx5/bMl5sxBYM3xUlfC7ky7e elSxHMkxmqaZ5J57IHfi4AeAYw== X-Google-Smtp-Source: AGHT+IGZ5PJupehTovqOBieFi4dd1mejoSpUIVv6UVfHefiU0RDKcsrTORGCYbNq7uWsVG8pvQADRg== X-Received: by 2002:a05:6512:ad5:b0:50c:1bc5:6a73 with SMTP id n21-20020a0565120ad500b0050c1bc56a73mr792071lfu.33.1701954426863; Thu, 07 Dec 2023 05:07:06 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j21-20020a056512109500b0050bc41caf04sm167685lfg.304.2023.12.07.05.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 05:07:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 03/10] soc: qcom: spm: add support for voltage regulator Date: Thu, 7 Dec 2023 16:06:56 +0300 Message-Id: <20231207130703.3322321-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> References: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SPM / SAW2 device also provides a voltage regulator functionality with optional AVS (Adaptive Voltage Scaling) support. The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 221 ++++++++++++++++++++++++++++++++++++++++- include/soc/qcom/spm.h | 9 ++ 2 files changed, 225 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2f0b1bfe7658..595e2afb2141 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -6,20 +6,40 @@ * SAW power controller driver */ -#include +#include +#include #include #include +#include +#include +#include #include -#include #include -#include #include +#include +#include + +#include + #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +/* These registers might be specific to SPM 1.1 */ +#define SPM_VCTL_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0) +#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16) + +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17) +#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -29,10 +49,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -169,6 +191,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -176,7 +202,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -187,6 +218,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -238,6 +273,181 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vctl, data0, data1, avs_ctl, sts; + unsigned int vlevel, volt_sel; + bool avs_enabled; + + volt_sel = drv->volt_sel; + vlevel = volt_sel | 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); + data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = volt_sel; + unsigned int min_avs = max(max_avs, 4U) - 4; + + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, tie it to CPU0 */ + + return 0; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + drv->reg_cpu = spm_get_cpu(dev); + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -288,6 +498,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -315,7 +526,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..9859ebe42003 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -30,11 +30,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; void spm_set_low_power_mode(struct spm_driver_data *drv, From patchwork Thu Dec 7 13:06:57 2023 Content-Type: text/plain; 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Thu, 07 Dec 2023 05:07:07 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 04/10] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Date: Thu, 7 Dec 2023 16:06:57 +0300 Message-Id: <20231207130703.3322321-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> References: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Per the power-domain.yaml, the power-controller node name is reserved for power-domain providers. Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,spm.yaml Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 95ac25e1a3b4..6832030c2c88 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -365,25 +365,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Thu Dec 7 13:06:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751171 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="noT1QQ5J" Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F1F110F1 for ; Thu, 7 Dec 2023 05:07:11 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-50bf2d9b3fdso834228e87.3 for ; Thu, 07 Dec 2023 05:07:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701954429; x=1702559229; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tRH0ltu/8xOeCYgi26zDqsTtGrYZ67tsC2xGcsHS4PY=; b=noT1QQ5JvJmco7Zx2DiaCaQZEPhdmbywAujcKJRNc6oUydwpcrLlDHpyvdfuhuUqfm Zmh8ALAr6Af/pR11aQ/JNNu3TTY8WfejXiiiJ8h8VMaIVjvbD2nABn3JOYc4qU0iqVmG Q22ry9NzyCKrP77rpxJmw1fyJa1WC4o21FYh0pvc7ME6DWaSbR42dCYrHNj0aQhXoMAj 81oJYO0QJ+Saj29bnHv1a705bgIVC/+EmLWfmuuwoR+w3A/LbIxa+Fg7FYiYxv9bC4Op EmXF2QKqhbj79zMvL3EePIT23YM/jtVlfA0zvF6OTDjoB/M254kpcV2WqMtWlkiJvKId HB6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701954429; x=1702559229; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tRH0ltu/8xOeCYgi26zDqsTtGrYZ67tsC2xGcsHS4PY=; b=XHxp+9K/gnOxloFu/M57JIlAjE+q57vLiuoa20jg14FBQXXTjG9DqxMpjlS7YczmeZ Rj+28aEueSj+itv1iSBHjCXmnML9PCZT2t6L0PoAeLftvd8RzXs82BX68BkhPJlzKsUn 7o736fAX0vei3qAu6qgM2eA7tHm32r40VP1yyFvKvCAD0nfAxZyF7UPKB3vwLAPNP9F3 nAADhKvl1sCQ15zrzeqSyYVp7qG2J6rWm1ssvXpJe3Qq/N4sFRpwdKK1RSk2aiKW6WXC YnUsIfUHjI2g87WC/Bq/hZ2hyzSGxVJ/3QId07Q9YgVt+zeVpP6g5YA9rEi6Iaze3YR6 qo1A== X-Gm-Message-State: AOJu0YxWnVQ/SSI0YZpEL2lZdk/IEiLYZwBIvheZKcsb9C++5tTN9hEZ BuRcAPCal3IwVgXSo4IEKDW4wQ== X-Google-Smtp-Source: AGHT+IEsyxo0MGyaQjyuCabGJdhhwA/ISqYGFHCfD0Cv0cJ6xp/BS7GC183ITUf6/GYMLLK663TFIA== X-Received: by 2002:a05:6512:3124:b0:50c:a39:ee37 with SMTP id p4-20020a056512312400b0050c0a39ee37mr1543140lfd.109.1701954429293; Thu, 07 Dec 2023 05:07:09 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j21-20020a056512109500b0050bc41caf04sm167685lfg.304.2023.12.07.05.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 05:07:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 06/10] ARM: dts: qcom: msm8960: declare SAW2 regulators Date: Thu, 7 Dec 2023 16:06:59 +0300 Message-Id: <20231207130703.3322321-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> References: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index f420740e068e..0ab340405784 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -223,13 +223,21 @@ acc1: clock-controller@2098000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { From patchwork Thu Dec 7 13:07:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751170 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="a5bU6+dN" Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7558E10F2 for ; Thu, 7 Dec 2023 05:07:12 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-50be3eed85aso839426e87.2 for ; Thu, 07 Dec 2023 05:07:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701954430; x=1702559230; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o0J8cjOv5k8AIvIFhvZ5YWOKOlem3yXviyX9wh+j9fA=; b=a5bU6+dNjHxBhonIQnoHkBn7zEj9dQOGEjF2j2OQw4sCPMLkg0Aq1n4d6GnHbn2dJ1 ejFswTEBT8cnoqcJW9fuT0PrE9ZQJK3A62LaKJ/wJwDhgBbg+IUUcbr8yTOiIhQnTkOn nx7lAHotmHT1JDdF7qj8aarmEe5QkvwtAhnEEy9oPahAK/4bDrD7rK22zDM4AkuUl8x5 XAujjglsJ6yR165puQ1tAHqCkrqbsLKEzzzpAwTQXQuNF6lDWS1ZAkAdooDBNQLAmHV1 7HgkFLnmVXC9wyBaMsgQaSTQZzfJ+rpKEGN70uJbK1tdhHx7+eRa/5qZnV9/oBmFu1/k NYuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701954430; x=1702559230; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o0J8cjOv5k8AIvIFhvZ5YWOKOlem3yXviyX9wh+j9fA=; b=hOYyFeIID0OYT/Ub/gAikcY+CvPJ/7Ta+F18TQk1mXhiRYiPKDCrkWVlEY9fxEcMnI Z9n2qvZXMqqLrd79LoOL/znPVMVy5kC8iVCvlhgf8j6vAFHc3PMa89QPCtmYB0dVoYGM hDkqEKXpu89u5BapVYegc8IsRhfnITLUEEeq0bkuuP2WbfMGgnq/Uo3wotDxUYs7KA2m NVGXzNU9ClJzkoOOd/Psq0DeTQIZ6Tz+eehJeTvBAts/q/LQL9FV/V8Ts5A2zTc3ZCB6 a7L5u+rCKFNg1Omx2rdFSXheEVXg/yPCzEIi053edLvaZuA+mZy0buuzAqSCzCZnKa3P Siaw== X-Gm-Message-State: AOJu0Yx35k2wMeUIeV2dUKitfMGvF4KFc1RpaSYyOPT6gIs/C/NRPqUo Pw6tIcvFuBcqY5Ue5WxEnO+3me8zYmupvDHVYGw= X-Google-Smtp-Source: AGHT+IFzyt+iYxTC1a62j+mR15slvY8zxvT4eeIUbRHT4qYXWdaU7x85njaKSmOSg2VeQbs+g1F7YQ== X-Received: by 2002:ac2:5227:0:b0:50b:f6a8:c778 with SMTP id i7-20020ac25227000000b0050bf6a8c778mr1593710lfl.5.1701954430710; Thu, 07 Dec 2023 05:07:10 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j21-20020a056512109500b0050bc41caf04sm167685lfg.304.2023.12.07.05.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 05:07:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 08/10] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device Date: Thu, 7 Dec 2023 16:07:01 +0300 Message-Id: <20231207130703.3322321-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> References: <20231207130703.3322321-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index ee202f3f161e..3e1e88d69c2e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -349,7 +349,6 @@ apcs: syscon@f9011000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; watchdog@f9017000 {