From patchwork Mon Aug 26 19:46:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 172196 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4806933ily; Mon, 26 Aug 2019 12:46:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqwTidPwRlub+ge+t0KdD7lSdDBamGuG2xM037vQF4yJ7BrB0VwZdhF89sQ230xA7SuW/2Hw X-Received: by 2002:a17:902:f096:: with SMTP id go22mr21130340plb.58.1566848773087; Mon, 26 Aug 2019 12:46:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566848773; cv=none; d=google.com; s=arc-20160816; b=aV1xHVuzzej0uMahPXUmOndPG7Ml/CDVtdxXUuK1Xq7vRPJ7JowevOS6aMTRhzWNP+ fq1ZNxzcDH9QP8Gl1mfwrRRMNmmuphnTWBsYpZ4d/hNVm7PVjttaz+4wdImSYy+ioR4a lijrWi2+JK7uET5SnggeXbfT9GZDm9mpaksy0w2kbty0yLQhfPQ+y0sVchnp2+1l3ruM vVYR1ya2zfvvgO/rYbDrSpSMe29RMSjWpZxDw3bUxhOaRx4JtiEsQHISpUxyn6+MibSl hwMIzYoRZpJEKkhuLDT79+On0ks889j8D5jFR7+3bBHr3qnRuYiymSiCRw++7ednRlbS bFDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=+5gWSemuxt3HHekdvm6tHeI05f3zrGiyld+SNG7Me4c=; b=0QQXb0f2xzIoDs8LibQsc4c63W4P4YoEw/3gT7pYHoS/ACzZIRw0/Zx9grjNRm8mHW Hewo1q8cCYY0iVsBXwmRd8DRS2IaZhjL/qK73lNjeURRmQhYzHgsCogxGjBAvooTqvR2 kJATQQT2jNuKkfQr3igtBXzstfmL2ryiQidQVWoZN3jd/vrkHGKmy3VYn6Znwtgi/4Vr 7/YkJf5Igbkgg+m9VEDjNhCplcZysfPqLki0wJPBRd8cuDnoN3qv9nxmBIqzfwVYYR0C LXZFfIA7XuIAGsTbeRwSOlDT/eTi9249xcKEpRVWsdZpuR2PZB9eWtd3XhUJNOVt4z2m BtrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q+kCsyIh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c35sm13214789pgl.72.2019.08.26.12.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 12:46:07 -0700 (PDT) From: Mathieu Poirier To: suzuki.poulose@arm.com, leo.yan@linaro.org, mike.leach@arm.com Cc: yabinc@google.com, alexander.shishkin@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] coresight: tmc: Make memory width mask computation into a function Date: Mon, 26 Aug 2019 13:46:03 -0600 Message-Id: <20190826194605.3791-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org> References: <20190826194605.3791-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make the computation of a memory mask representing the width of the memory bus into a function so that it can be re-used by the ETR driver. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etf.c | 23 ++------------- drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 3 files changed, 31 insertions(+), 21 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 23b7ff00af5c..807416b75ecc 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, * traces. */ if (!buf->snapshot && to_read > handle->size) { - u32 mask = 0; - - /* - * The value written to RRP must be byte-address aligned to - * the width of the trace memory databus _and_ to a frame - * boundary (16 byte), whichever is the biggest. For example, - * for 32-bit, 64-bit and 128-bit wide trace memory, the four - * LSBs must be 0s. For 256-bit wide trace memory, the five - * LSBs must be 0s. - */ - switch (drvdata->memwidth) { - case TMC_MEM_INTF_WIDTH_32BITS: - case TMC_MEM_INTF_WIDTH_64BITS: - case TMC_MEM_INTF_WIDTH_128BITS: - mask = GENMASK(31, 4); - break; - case TMC_MEM_INTF_WIDTH_256BITS: - mask = GENMASK(31, 5); - break; - } + u32 mask = tmc_get_memwidth_mask(drvdata); /* * Make sure the new size is aligned in accordance with the - * requirement explained above. + * requirement explained in function tmc_get_memwidth_mask(). */ to_read = handle->size & mask; /* Move the RAM read pointer up */ diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 3055bf8e2236..1cf82fa58289 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata) writel_relaxed(0x0, drvdata->base + TMC_CTL); } +u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) +{ + u32 mask = 0; + + /* + * When moving RRP or an offset address forward, the new values must + * be byte-address aligned to the width of the trace memory databus + * _and_ to a frame boundary (16 byte), whichever is the biggest. For + * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four + * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must + * be 0s. + */ + switch (drvdata->memwidth) { + case TMC_MEM_INTF_WIDTH_32BITS: + /* fallthrough */ + case TMC_MEM_INTF_WIDTH_64BITS: + /* fallthrough */ + case TMC_MEM_INTF_WIDTH_128BITS: + mask = GENMASK(31, 4); + break; + case TMC_MEM_INTF_WIDTH_256BITS: + mask = GENMASK(31, 5); + break; + } + + return mask; +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret = 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 9dbcdf453e22..71de978575f3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); +u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); /* ETB/ETF functions */ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); From patchwork Mon Aug 26 19:46:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 172197 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4806978ily; Mon, 26 Aug 2019 12:46:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqyQ0iWu2ldrb0ufxVXEETuwZgqVauyftlHnMlxvw+zMjCMa9bMARMjBr1zPnkTwy3rcN1f5 X-Received: by 2002:a62:1858:: with SMTP id 85mr22379615pfy.120.1566848775142; Mon, 26 Aug 2019 12:46:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566848775; cv=none; d=google.com; s=arc-20160816; b=fr0hUGx745F51ZX+xvz+4rPymeW5wIVPtzrkwliB9Qv0UtMosmhBZHRCjotq228QCE /H7ufSAw0XeIwQVXOKiHPdv/rMSDJyOoF3BkCA1JJLID+y8ttLlaTaLJ5rrQfQ7mPqGV ZdfiOVCy+k6r7sgP8lufgAB8uzNEc+c+UaM+gtPq4OJrvNsGlWZ4d71a/P5I1pTss8An +nlT0zsfMgqC7lfgcO+IRQDtaCL/NNJdjW/kKxlFZH1vPadageRtMwnG5/+Oavbn64tF x4ShHvMKp6vsrwIhUJsPCgpX66R/C03UEoypYzGvlaK2n8C5tnh0wWGKXxwTlcLsp4mP tNgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=to1oeNA++JDNSoQZ9+DGa/c6NmOGbTyxF1scobzI6zQ=; b=kazI57ZSx7uimHFWGZKefa21uO15V5WyW/ISobd7EeP3aadA2ycBLvVvb8s/52WaB2 8I1SQx1MzlgA/2wyQv3wE+LiUlB5WkbvhmMcMV/py58pJ4gq7uWMw6Q4NZHK9nXNRR/G 1d92w4s26PiLzwIT2VRKOzwgPFy2oJsjJR5gBY0qgOvOiKpaRT4in9/qBSfC3Pq06bpo Pwd9jc6RuQ/zITnrIp+N36quMQs5zuRUW+MngO8yIjobAfynsOU3PSi7AieRh2qIeSLA UTx5gRNGgG9mRWQrol4oSwAjiBRZjapzs/aId53yBXtiDhl2pAIO5mAcqlD0roltyAzN MOKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vy0jQd6i; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c35sm13214789pgl.72.2019.08.26.12.46.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 12:46:08 -0700 (PDT) From: Mathieu Poirier To: suzuki.poulose@arm.com, leo.yan@linaro.org, mike.leach@arm.com Cc: yabinc@google.com, alexander.shishkin@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion Date: Mon, 26 Aug 2019 13:46:04 -0600 Message-Id: <20190826194605.3791-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org> References: <20190826194605.3791-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If less space is available in the perf ring buffer than the ETR buffer, barrier packets inserted in the trace stream by tmc_sync_etr_buf() are skipped over when the head of the buffer is moved forward, resulting in traces that can't be decoded. This patch decouples the process of syncing ETR buffers and the addition of barrier packets in order to perform the latter once the offset in the trace buffer has been properly computed. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Leo Yan diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 4f000a03152e..bae47272de98 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -946,10 +946,6 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) WARN_ON(!etr_buf->ops || !etr_buf->ops->sync); etr_buf->ops->sync(etr_buf, rrp, rwp); - - /* Insert barrier packets at the beginning, if there was an overflow */ - if (etr_buf->full) - tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset); } static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) @@ -1086,6 +1082,13 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata) drvdata->sysfs_buf = NULL; } else { tmc_sync_etr_buf(drvdata); + /* + * Insert barrier packets at the beginning, if there was + * an overflow. + */ + if (etr_buf->full) + tmc_etr_buf_insert_barrier_packet(etr_buf, + etr_buf->offset); } } @@ -1502,11 +1505,16 @@ tmc_update_etr_buffer(struct coresight_device *csdev, CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); + lost = etr_buf->full; size = etr_buf->len; if (!etr_perf->snapshot && size > handle->size) { size = handle->size; lost = true; } + + /* Insert barrier packets at the beginning, if there was an overflow */ + if (lost) + tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset); tmc_etr_sync_perf_buffer(etr_perf, size); /* @@ -1517,8 +1525,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev, */ if (etr_perf->snapshot) handle->head += size; - - lost |= etr_buf->full; out: /* * Don't set the TRUNCATED flag in snapshot mode because 1) the From patchwork Mon Aug 26 19:46:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 172198 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4807066ily; Mon, 26 Aug 2019 12:46:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkn+aXAG55clp6oeyqCPf7QZa+p5hkQ0Bg63w/57mDINjysbNMk/CY8jMU294KdhVtLzyd X-Received: by 2002:a17:902:e9:: with SMTP id a96mr8700564pla.169.1566848780412; Mon, 26 Aug 2019 12:46:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566848780; cv=none; d=google.com; s=arc-20160816; b=BIOvDlQEPWHQMiYKCb97AaDmI7cSx3R7Ncn1WCMVu7mdafTWjGpf2wDBsI0gzfwqJb yG6EE+cdUHp8Kds+M1DI05YOhNaGRYxM2idJMMzymZapXBAg14I/hM4xZFWrjCRNmbYd CQQ1nyxX5KYJTtSb3kPxpyG2Ad80rsYhcxhpX1p4yQ91qyizNWFZBDQ92sfcrpaGrBJW ZWZCOJjhSi1uDEciDmFGsKOInKXLC4a7F6seMfgWV31qzDUjy4LKMrr0SNhCEK0hqkml 6CKjqkFqqt75xXPS40NClOS6/o/57E2noebgYV66NsB+qU16035BBMvfLySafFEoLykw Ab2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=CW9u0WKr9dqfCIpHqZBfiXSJtaw0A8YWyqVfALCj0kc=; b=P542TvD6NIZNVkAO0HmGHtck3vZ7K3VPsKs4HjucaBqicrOmNKcWCww8u8dbZt9MFB 31r9pKRs+zfn53KvjTTIQh5bwoSUmfcSRjOXCJqPhpawL5IxUIV3Q8Nsxh2BEmmJKpWe POfsIx0sCzwHf8OTTHU6TmUuneeqQfESHPzHbJ2frzO0izPdwB8k7+XJCm4/wX1wkWJM hMt5CzbGC/ix4O573FnUM0fBWobagCJgB+Vo7jmArZBMVcrI8tshAL1NSMssy0oi4dR5 SJCWb/ca3aJTEJPgO8DXpOGoNtTzUqFOvP86qE48CoZPbjJKQeS1uJxWq//R1nBihekQ yCzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WVwg3TwB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c35sm13214789pgl.72.2019.08.26.12.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 12:46:09 -0700 (PDT) From: Mathieu Poirier To: suzuki.poulose@arm.com, leo.yan@linaro.org, mike.leach@arm.com Cc: yabinc@google.com, alexander.shishkin@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] coresight: tmc-etr: Add barrier packets when moving offset forward Date: Mon, 26 Aug 2019 13:46:05 -0600 Message-Id: <20190826194605.3791-4-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org> References: <20190826194605.3791-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds barrier packets in the trace stream when the offset in the data buffer needs to be moved forward. Otherwise the decoder isn't aware of the break in the stream and can't synchronise itself with the trace data. Signed-off-by: Mathieu Poirier Tested-by: Yabin Cui --- .../hwtracing/coresight/coresight-tmc-etr.c | 29 +++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index bae47272de98..625882bc8b08 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1418,10 +1418,11 @@ static void tmc_free_etr_buffer(void *config) * buffer to the perf ring buffer. */ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, + unsigned long src_offset, unsigned long to_copy) { long bytes; - long pg_idx, pg_offset, src_offset; + long pg_idx, pg_offset; unsigned long head = etr_perf->head; char **dst_pages, *src_buf; struct etr_buf *etr_buf = etr_perf->etr_buf; @@ -1430,7 +1431,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, pg_idx = head >> PAGE_SHIFT; pg_offset = head & (PAGE_SIZE - 1); dst_pages = (char **)etr_perf->pages; - src_offset = etr_buf->offset + etr_buf->len - to_copy; while (to_copy > 0) { /* @@ -1478,7 +1478,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, void *config) { bool lost = false; - unsigned long flags, size = 0; + unsigned long flags, offset, size = 0; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etr_perf_buffer *etr_perf = config; struct etr_buf *etr_buf = etr_perf->etr_buf; @@ -1506,16 +1506,35 @@ tmc_update_etr_buffer(struct coresight_device *csdev, spin_unlock_irqrestore(&drvdata->spinlock, flags); lost = etr_buf->full; + offset = etr_buf->offset; size = etr_buf->len; + + /* + * The ETR buffer may be bigger than the space available in the + * perf ring buffer (handle->size). If so advance the offset so that we + * get the latest trace data. In snapshot mode none of that matters + * since we are expected to clobber stale data in favour of the latest + * traces. + */ if (!etr_perf->snapshot && size > handle->size) { - size = handle->size; + u32 mask = tmc_get_memwidth_mask(drvdata); + + /* + * Make sure the new size is aligned in accordance with the + * requirement explained in function tmc_get_memwidth_mask(). + */ + size = handle->size & mask; + offset = etr_buf->offset + etr_buf->len - size; + + if (offset >= etr_buf->size) + offset -= etr_buf->size; lost = true; } /* Insert barrier packets at the beginning, if there was an overflow */ if (lost) tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset); - tmc_etr_sync_perf_buffer(etr_perf, size); + tmc_etr_sync_perf_buffer(etr_perf, offset, size); /* * In snapshot mode we simply increment the head by the number of byte