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[83.36.179.124]) by smtp.gmail.com with ESMTPSA id o14sm21800076wrg.64.2019.08.26.09.48.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Aug 2019 09:48:10 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, agross@kernel.org, mark.rutland@arm.com Cc: niklas.cassel@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: mailbox: qcom: Add clock-name optional property Date: Mon, 26 Aug 2019 18:48:02 +0200 Message-Id: <20190826164807.7028-1-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the APCS clock is registered (platform dependent), it retrieves its parent names from hardcoded values in the driver. The following commit allows the DT node to provide such clock names to the platform data based clock driver therefore avoiding having to explicitly embed those names in the clock driver source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../mailbox/qcom,apcs-kpss-global.txt | 24 ++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) -- 2.22.0 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index 1232fc9fc709..b69310322b09 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -18,10 +18,11 @@ platforms. Usage: required Value type: Definition: must specify the base address and size of the global block + - clocks: - Usage: required if #clocks-cells property is present - Value type: - Definition: phandle to the input PLL, which feeds the APCS mux/divider + Usage: required if #clock-names property is present + Value type: + Definition: phandles to the two parent clocks of the clock driver. - #mbox-cells: Usage: required @@ -33,6 +34,12 @@ platforms. Value type: Definition: as described in clock.txt, must be 0 +- clock-names: + Usage: required if the platform data based clock driver needs to + retrieve the parent clock names from device tree. + This will requires two mandatory clocks to be defined. + Value type: + Definition: must be "aux" and "pll" = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -65,3 +72,14 @@ Below is another example of the APCS binding on MSM8916 platforms: clocks = <&a53pll>; #clock-cells = <0>; }; + +Below is another example of the APCS binding on QCS404 platforms: + + apcs_glb: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>; + clock-names = "aux", "pll"; + #clock-cells = <0>; + }; From patchwork Mon Aug 26 16:48:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 172184 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4600540ily; Mon, 26 Aug 2019 09:48:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqwdEpmGyHDNeXaFdvnHNeIxK8yFc+4/Q38nWoEeptCuC6IQTxSEkUHJgPu5rthWQOi9tU6f X-Received: by 2002:aa7:8559:: with SMTP id y25mr20757374pfn.260.1566838099510; Mon, 26 Aug 2019 09:48:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566838099; cv=none; d=google.com; s=arc-20160816; b=JJTgvM2UtytBhxMvLZVRgC2Jz6G5pbZccT9onrDSxbbSmZakhGeaP0hQCl6KELg72w /BIUDVvd4HFd6J3dqlxqXDZGEO96j0ogCJ1oRTbwUBuyhKIofYd2AfWtArhWctY54Kzb 4hx4FOUSRlT3l0ExU7+dT46BFdx8dUrDVkEsjVMnIc+sAXXBpxq4hM3WBS6ZBn80diOp v4dWfkmM7+4nCDZHXu7uOLAJjsRUWhvd7nGpHCL2Pful5IetX8oJHVO5NOgUWkiks+qM Qhfev0hhZOwbxOUmEQGEAx7+YtxgkNfkgxuYuPIIBvMPE7nAXAXigc47eEtcQrvvKYWK 4xww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6aBjlsqiqqTgtzhykCGPDbSLi9lpwGSk1XF7w3yerKo=; b=G448EioSinGVTawoAlG3xoacGDEDhu54DtPP/BVZDZGvxDF+GIR1wmjl/1/DXDRlEv 1flAm8xyqatVPuOEE+7XSyCB2jR6FtuUcAsmiHcev85wpnLkFi9pGDIGTAePtJgRbX6U mmodtWYBBy8FySh2ltllkb0fllE2s71tsZ9c3f6MoWhhawezMn/nez3QPqRBlxKqk6Ed BDpYWA5sFB91E86Q3z9UDFMlUwZEAI+S74HG1XdoADw2jMw+55+KmTfCZbzkHP4gDKaG SO/wSE4HRcarLPSLOZCaE0qqk10NHvF9jLizoWh4v2eSfYyRn8sUIGHbphueVzFebgl+ yjdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WiPY2VmO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.36.179.124]) by smtp.gmail.com with ESMTPSA id o14sm21800076wrg.64.2019.08.26.09.48.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Aug 2019 09:48:11 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, agross@kernel.org, mark.rutland@arm.com Cc: niklas.cassel@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] arm64: dts: qcom: qcs404: Add HFPLL node Date: Mon, 26 Aug 2019 18:48:04 +0200 Message-Id: <20190826164807.7028-3-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190826164807.7028-1-jorge.ramirez-ortiz@linaro.org> References: <20190826164807.7028-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a97eeb4569c0..75ea356a3fb0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -869,6 +869,15 @@ #mbox-cells = <1>; }; + apcs_hfpll: clock-controller@b016000 { + compatible = "qcom,hfpll"; + reg = <0x0b016000 0x30>; + #clock-cells = <0>; + clock-output-names = "apcs_hfpll"; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; From patchwork Mon Aug 26 16:48:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 172185 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp4600599ily; Mon, 26 Aug 2019 09:48:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqzDQ1bbi+DklMVSssfwUyjZzlbMrN7fHHDEw9iBiTHzTqXmdNnDMUq5MkHhaky+5nYpcuM7 X-Received: by 2002:a17:902:a9c3:: with SMTP id b3mr19746682plr.179.1566838102358; Mon, 26 Aug 2019 09:48:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566838102; cv=none; d=google.com; s=arc-20160816; b=SN3wnkzT+1v7eK803aHs4+JGVqxz5cVj7Es+mK09epp/MTeuB6/f6r4eTslNjP+Dm6 NLpt95sQJWv9mZOv4toBDIS2eLIzeEhZvUXazWXklI19UafKfPCUDR0l19iZbaAv9Ceb Z15GraSjgu7JNwlDodvJVDgzE/Dxowcdej9SClor1lPcV+I+vA+IBlo4MF3CMH2VFFW2 jRG4y3xpmnWv1Wl0bEd7XlwPCAPllWJl8HLLbm/Q929LFGAR6Heh3k45/RixjfXCVnWB W/6ptAA7clh/MoN0L1FqLhUWJR7MUqJVUibKutyYMiBIybB9F5YvZIKkTnOpCaENZkep j2xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Hupd+NjOPBz3nsSvh0rk5zeJMQwvXm41o+AWQWydlzs=; b=AkGdOl5LSbCjW9KUBkiOhbjy688o00sRdW60LV/2IecPed+H8giFyvjdXS0zRM6pBv ZOZctxEoKxuk8QHHEvOBx32tGZ8mfyt0lPz1ibNV0Kp8Fq14q8Elrvy9ORtDNKL/xiMA pReRsUJMqFmbzCgEceWbt6/HxB34eQk96VkCPC18cf/h/0GuaoTseAgLjRdH2pIgTJ/P xXKQUDk1IFmoimJC/875DlF8dZcj+w432xfqgDKOG+TGcl/503gAhx99SUHAkvP5cq8q 4HKi0qMQiVULnagBhKCvUf1ngVmCVuyrtYP/0VQluJGvm+SrhKlqTTpFxP2xmXTLAs2L ABkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="sZMXmbW/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.36.179.124]) by smtp.gmail.com with ESMTPSA id o14sm21800076wrg.64.2019.08.26.09.48.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Aug 2019 09:48:12 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, agross@kernel.org, mark.rutland@arm.com Cc: niklas.cassel@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Date: Mon, 26 Aug 2019 18:48:05 +0200 Message-Id: <20190826164807.7028-4-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190826164807.7028-1-jorge.ramirez-ortiz@linaro.org> References: <20190826164807.7028-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 75ea356a3fb0..34360b2d3e0d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -867,6 +867,9 @@ compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>; + clock-names = "aux", "pll"; + #clock-cells = <0>; }; apcs_hfpll: clock-controller@b016000 {