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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id gq18-20020a170906e25200b00a0a8b2b74ddsm6795404ejb.154.2023.12.05.06.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 06:39:05 -0800 (PST) From: Luca Weiss Date: Tue, 05 Dec 2023 15:38:54 +0100 Subject: [PATCH v6 1/3] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231205-sc7280-ufs-v6-1-ad6ca7796de7@fairphone.com> References: <20231205-sc7280-ufs-v6-0-ad6ca7796de7@fairphone.com> In-Reply-To: <20231205-sc7280-ufs-v6-0-ad6ca7796de7@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nitin Rawat , Krzysztof Kozlowski , "Bao D. Nguyen" , Luca Weiss X-Mailer: b4 0.12.4 From: Nitin Rawat Document the compatible string for the UFS found on SC7280. Signed-off-by: Nitin Rawat Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bao D. Nguyen Acked-by: Manivannan Sadhasivam Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 2cf3d016db42..10c146424baa 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -27,6 +27,7 @@ properties: - qcom,msm8996-ufshc - qcom,msm8998-ufshc - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc @@ -118,6 +119,7 @@ allOf: enum: - qcom,msm8998-ufshc - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc From patchwork Tue Dec 5 14:38:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 750450 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="am5rSL4X" Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1595C1B5 for ; Tue, 5 Dec 2023 06:39:09 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a00f67f120aso754804166b.2 for ; Tue, 05 Dec 2023 06:39:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1701787147; x=1702391947; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=C4O0UDDPSWRyxJ5a3wx0+K3NYIqTeYfsWlSp1+sj3fc=; b=am5rSL4X2KsMD3Hq5llpYHfX6DxKp/vmxP4x2L7xfCi09RvOZNz7fIEv69/HtYhm4m E4+F4MGcOUYooEQ05KNVbtE1mJnBRT9IH/jbOH45O608Qv8E4DYCN4OP+keKbzRrtGxM xZDEt1pthG7LMYWYAiUfsdGEvlGAVFbUpB4bVYmFtfqWf8KocljWzDEvomLnVS9uyeCW h7gD3fuuwMoLfcKLnQdHNcfijVCTKcR/gPRrL5++6EymMop0jWmLFhFCwj1jt+/PpK1Y usjGKzAhrWYRn3Zp+/ZOxs6bRRA1xyFUt0PmUYeWqBEFvJXZRLCFuzSuDtfIOkVb5m4V GZ7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701787147; x=1702391947; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C4O0UDDPSWRyxJ5a3wx0+K3NYIqTeYfsWlSp1+sj3fc=; b=ooDqUHLO66UUPfQSI3u9vLxmGZTa6UyrFeijZx+uMcUrUvBWcsVrtgPtOGVebitzNI hx6tSkskKKx745Zshf03MH2We39m2bqdhUCwkcsRGctrjPUDWyBuX8UUcPoqID7OsjRn sPkgU7ylVAVthn2pxoXV6j0fVCYi3HjtHcGikPvnZwKjlZB5hION9MKMk0vatLtuQlnr XbVvs61bDhES6NXluieDxbgIl2GvpZ607cTiFPlGKhCtS06iIL7dZYCHlWIJlPPqeovk 0o6p2wom4PD09dn+WlAjJ6miJssuw+Gsvj5L1/qDkpdOuqSBDC6SUqF7zBZJfpLkHBza 5rbA== X-Gm-Message-State: AOJu0YyUlVf2Dx4KTP+Ml3pt2tJMZbyxzDQstIEWEUVKuUTR4jpRY6Lp EVeIwfYBm+2CxT2vx05a1W29gA== X-Google-Smtp-Source: AGHT+IEbfMwPsV1+ddsYlU5zo4v/vz0HOs8tKtJXcSEehNCn/w2pxyCkp3jJlifxJr5xr/MeBny4Aw== X-Received: by 2002:a17:906:51d7:b0:a19:a19b:5608 with SMTP id v23-20020a17090651d700b00a19a19b5608mr594270ejk.152.1701787147624; Tue, 05 Dec 2023 06:39:07 -0800 (PST) Received: from otso.luca.vpn.lucaweiss.eu (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id gq18-20020a170906e25200b00a0a8b2b74ddsm6795404ejb.154.2023.12.05.06.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 06:39:06 -0800 (PST) From: Luca Weiss Date: Tue, 05 Dec 2023 15:38:55 +0100 Subject: [PATCH v6 2/3] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231205-sc7280-ufs-v6-2-ad6ca7796de7@fairphone.com> References: <20231205-sc7280-ufs-v6-0-ad6ca7796de7@fairphone.com> In-Reply-To: <20231205-sc7280-ufs-v6-0-ad6ca7796de7@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nitin Rawat , Luca Weiss X-Mailer: b4 0.12.4 From: Nitin Rawat Add UFS host controller and PHY nodes for sc7280 soc. Signed-off-by: Nitin Rawat Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # QCM6490 FP5 [luca: various cleanups and additions as written in the cover letter] Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 74 +++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 04bf85b0399a..dcb6c2004f87 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -906,7 +907,7 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <0>, <&pcie1_phy>, - <0>, <0>, <0>, + <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", @@ -2238,6 +2239,77 @@ pcie1_phy: phy@1c0e000 { status = "disabled"; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x80 0x0>; + dma-coherent; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc7280-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + + power-domains = <&rpmhpd SC7280_MX>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sc7280-ipa";