From patchwork Tue Dec 5 22:03:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 750447 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ga1ZFGZt" Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A853135; Tue, 5 Dec 2023 14:06:09 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1d08a924fcfso27332305ad.2; Tue, 05 Dec 2023 14:06:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701813969; x=1702418769; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R0Y5IM2vDue8lpCmMVrkGDpOK8xGwXyYPvY3SFd/ZFc=; b=ga1ZFGZtlKnDcTaVB5GvwjF6iQQl9xxZMIYa2WrQ6FTxCqpo5f30fE9jpyUkUrZLSj QngXHTZsZ18c9wtCJ3S5L4GiK5rW1yeU5ImoWMaMYiMFRzaQiGgRnz0DUNbVc7zj0z+4 yjnKW2q4TV940h4AW6hzVHIs5K5blGMVEDaanlt8ZXRRa3gvEo2Wk6/ecTBC6DtJw8Gk 2AYcbaSjPnYHjkcK7iSsjaFw3HebBok5VCSCUkBr+2pmF9gspIPCuROep2EEXN8DGLwi W1HUY9BPPiCoQ0sp5Nivag3tIPmo5dm/p68SqZw4krk0qw9wYY/nA7Bfa0rlSwELDV8M DiFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701813969; x=1702418769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R0Y5IM2vDue8lpCmMVrkGDpOK8xGwXyYPvY3SFd/ZFc=; b=Q2VpZ0AF+v25KV34nO98+2kr6VYPN8Phg4mSwhAbBCEMt8Hp6GSJu1fofxivz/4Njc sJEFJhDveI72P9wrYSts/9C+M88t3ocW4YZVNo4EHFkG92yYDwrM+Cg+fyoHUUQ2NEUg PQWr+Ih7fWE81qmtiMLCTHMUrp/TJ+6IkDTe4W5666Gg6JM0Rczn17LPEUBs+rG7cIu4 k3Ce3m0xxlqjC+CAXHURCj90qbNuHkoU6EEuxEiJA33RuUonGP8AHsz53MyqCG5Hd4xA +oh+J/PzyjL5M9sQMm+mSn/etFI8rOBkD0NcpJSeAlGJl/HXfDC5hehFL5WjaUEeqt5E CMbw== X-Gm-Message-State: AOJu0YyAslqsB4BwCqKp/nssZ5ndXIP2Hh5M7NcZq6PREVARD8fUo2a/ 8YCbr5vweSiIm1kRFModWtU= X-Google-Smtp-Source: AGHT+IHJG4BKY3aS3NTFxpFz+sjEXOm4ND2PiRmRLhposCzjbOXluCzkhZwcs+OLvgwAfpAu11tz+A== X-Received: by 2002:a17:902:c946:b0:1d0:7f06:1741 with SMTP id i6-20020a170902c94600b001d07f061741mr7074300pla.30.1701813968796; Tue, 05 Dec 2023 14:06:08 -0800 (PST) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id q24-20020a170902bd9800b001d1c96a0c63sm191990pls.274.2023.12.05.14.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 14:06:08 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Konrad Dybcio , Johan Hovold , Bjorn Andersson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/5] drm/msm/adreno: Split catalog into separate files Date: Tue, 5 Dec 2023 14:03:28 -0800 Message-ID: <20231205220526.417719-3-robdclark@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231205220526.417719-1-robdclark@gmail.com> References: <20231205220526.417719-1-robdclark@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rob Clark Split each gen's gpu table into it's own file. Only code-motion, no functional change. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Makefile | 5 + drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 53 ++ drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 75 +++ drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 51 ++ drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 145 ++++++ drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 285 +++++++++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 570 +-------------------- 7 files changed, 620 insertions(+), 564 deletions(-) create mode 100644 drivers/gpu/drm/msm/adreno/a2xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_catalog.c create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_catalog.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 49671364fdcf..32f2fd980452 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -7,12 +7,17 @@ ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp msm-y := \ adreno/adreno_device.o \ adreno/adreno_gpu.o \ + adreno/a2xx_catalog.o \ adreno/a2xx_gpu.o \ + adreno/a3xx_catalog.o \ adreno/a3xx_gpu.o \ + adreno/a4xx_catalog.o \ adreno/a4xx_gpu.o \ + adreno/a5xx_catalog.o \ adreno/a5xx_gpu.o \ adreno/a5xx_power.o \ adreno/a5xx_preempt.o \ + adreno/a6xx_catalog.o \ adreno/a6xx_gpu.o \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c new file mode 100644 index 000000000000..1a4d182279fc --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +const struct adreno_info a2xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x02000000), + .family = ADRENO_2XX_GEN1, + .revn = 200, + .fw = { + [ADRENO_FW_PM4] = "yamato_pm4.fw", + [ADRENO_FW_PFP] = "yamato_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a2xx_gpu_init, + }, { /* a200 on i.mx51 has only 128kib gmem */ + .chip_ids = ADRENO_CHIP_IDS(0x02000001), + .family = ADRENO_2XX_GEN1, + .revn = 201, + .fw = { + [ADRENO_FW_PM4] = "yamato_pm4.fw", + [ADRENO_FW_PFP] = "yamato_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a2xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x02020000), + .family = ADRENO_2XX_GEN2, + .revn = 220, + .fw = { + [ADRENO_FW_PM4] = "leia_pm4_470.fw", + [ADRENO_FW_PFP] = "leia_pfp_470.fw", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a2xx_gpu_init, + }, { + /* sentinal */ + } +}; + +MODULE_FIRMWARE("qcom/leia_pfp_470.fw"); +MODULE_FIRMWARE("qcom/leia_pm4_470.fw"); +MODULE_FIRMWARE("qcom/yamato_pfp.fw"); +MODULE_FIRMWARE("qcom/yamato_pm4.fw"); \ No newline at end of file diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c new file mode 100644 index 000000000000..1f1fa70c5e5e --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +const struct adreno_info a3xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS( + 0x03000512, + 0x03000520 + ), + .family = ADRENO_3XX, + .revn = 305, + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000600), + .family = ADRENO_3XX, + .revn = 307, /* because a305c is revn==306 */ + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x03020000, + 0x03020001, + 0x03020002 + ), + .family = ADRENO_3XX, + .revn = 320, + .fw = { + [ADRENO_FW_PM4] = "a300_pm4.fw", + [ADRENO_FW_PFP] = "a300_pfp.fw", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x03030000, + 0x03030001, + 0x03030002 + ), + .family = ADRENO_3XX, + .revn = 330, + .fw = { + [ADRENO_FW_PM4] = "a330_pm4.fw", + [ADRENO_FW_PFP] = "a330_pfp.fw", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + /* sentinal */ + } +}; + +MODULE_FIRMWARE("qcom/a300_pm4.fw"); +MODULE_FIRMWARE("qcom/a300_pfp.fw"); +MODULE_FIRMWARE("qcom/a330_pm4.fw"); +MODULE_FIRMWARE("qcom/a330_pfp.fw"); \ No newline at end of file diff --git a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c new file mode 100644 index 000000000000..39d92cb4bcf5 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +const struct adreno_info a4xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x04000500), + .family = ADRENO_4XX, + .revn = 405, + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x04020000), + .family = ADRENO_4XX, + .revn = 420, + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = (SZ_1M + SZ_512K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x04030002), + .family = ADRENO_4XX, + .revn = 430, + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = (SZ_1M + SZ_512K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, + }, { + /* sentinal */ + } +}; + +MODULE_FIRMWARE("qcom/a420_pm4.fw"); +MODULE_FIRMWARE("qcom/a420_pfp.fw"); \ No newline at end of file diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c new file mode 100644 index 000000000000..80d70ee8c1f2 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +const struct adreno_info a5xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x05000600), + .family = ADRENO_5XX, + .revn = 506, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_128K + SZ_8K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | + ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a506_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05000800), + .family = ADRENO_5XX, + .revn = 508, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_128K + SZ_8K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a508_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05000900), + .family = ADRENO_5XX, + .revn = 509, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + /* Adreno 509 uses the same ZAP as 512 */ + .zapfw = "a512_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05010000), + .family = ADRENO_5XX, + .revn = 510, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = SZ_256K, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .init = a5xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05010200), + .family = ADRENO_5XX, + .revn = 512, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + }, + .gmem = (SZ_256K + SZ_16K), + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a512_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x05030002, + 0x05030004 + ), + .family = ADRENO_5XX, + .revn = 530, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", + }, + .gmem = SZ_1M, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | + ADRENO_QUIRK_FAULT_DETECT_MASK, + .init = a5xx_gpu_init, + .zapfw = "a530_zap.mdt", + }, { + .chip_ids = ADRENO_CHIP_IDS(0x05040001), + .family = ADRENO_5XX, + .revn = 540, + .fw = { + [ADRENO_FW_PM4] = "a530_pm4.fw", + [ADRENO_FW_PFP] = "a530_pfp.fw", + [ADRENO_FW_GPMU] = "a540_gpmu.fw2", + }, + .gmem = SZ_1M, + /* + * Increase inactive period to 250 to avoid bouncing + * the GDSC which appears to make it grumpy + */ + .inactive_period = 250, + .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, + .init = a5xx_gpu_init, + .zapfw = "a540_zap.mdt", + }, { + /* sentinal */ + } +}; + +MODULE_FIRMWARE("qcom/a530_pm4.fw"); +MODULE_FIRMWARE("qcom/a530_pfp.fw"); +MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); +MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); \ No newline at end of file diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c new file mode 100644 index 000000000000..5c1199eab82b --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2014 Red Hat + * Author: Rob Clark + * + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. + */ + +#include "adreno_gpu.h" + +const struct adreno_info a6xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x06010000), + .family = ADRENO_6XX_GEN1, + .revn = 610, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a610_zap.mdt", + .hwcg = a612_hwcg, + /* + * There are (at least) three SoCs implementing A610: SM6125 + * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does + * not have speedbinning, as only a single SKU exists and we + * don't support khaje upstream yet. Hence, this matching + * table is only valid for bengal. + */ + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 206, 1 }, + { 200, 2 }, + { 157, 3 }, + { 127, 4 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06010800), + .family = ADRENO_6XX_GEN1, + .revn = 618, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 169, 1 }, + { 174, 2 }, + ), + }, { + .machine = "qcom,sm4350", + .chip_ids = ADRENO_CHIP_IDS(0x06010900), + .family = ADRENO_6XX_GEN1, + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 138, 1 }, + { 92, 2 }, + ), + }, { + .machine = "qcom,sm6375", + .chip_ids = ADRENO_CHIP_IDS(0x06010901), + .family = ADRENO_6XX_GEN1, + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 190, 1 }, + { 177, 2 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06010900), + .family = ADRENO_6XX_GEN1, + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 120, 4 }, + { 138, 3 }, + { 169, 2 }, + { 180, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS( + 0x06030001, + 0x06030002 + ), + .family = ADRENO_6XX_GEN1, + .revn = 630, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a630_zap.mdt", + .hwcg = a630_hwcg, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06040001), + .family = ADRENO_6XX_GEN2, + .revn = 640, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a640_gmu.bin", + }, + .gmem = SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a640_zap.mdt", + .hwcg = a640_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06050002), + .family = ADRENO_6XX_GEN3, + .revn = 650, + .fw = { + [ADRENO_FW_SQE] = "a650_sqe.fw", + [ADRENO_FW_GMU] = "a650_gmu.bin", + }, + .gmem = SZ_1M + SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a650_zap.mdt", + .hwcg = a650_hwcg, + .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ + { 3, 2 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06060001), + .family = ADRENO_6XX_GEN4, + .revn = 660, + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_1M + SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a660_zap.mdt", + .hwcg = a660_hwcg, + .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06030500), + .family = ADRENO_6XX_GEN4, + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a660_zap.mbn", + .hwcg = a660_hwcg, + .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 117, 0 }, + { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ + { 190, 1 }, + ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06080000), + .family = ADRENO_6XX_GEN2, + .revn = 680, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a640_gmu.bin", + }, + .gmem = SZ_2M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a640_zap.mdt", + .hwcg = a640_hwcg, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06090000), + .family = ADRENO_6XX_GEN4, + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_4M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a690_zap.mdt", + .hwcg = a690_hwcg, + .address_space_size = SZ_16G, + }, { + /* sentinal */ + } +}; + +MODULE_FIRMWARE("qcom/a619_gmu.bin"); +MODULE_FIRMWARE("qcom/a630_sqe.fw"); +MODULE_FIRMWARE("qcom/a630_gmu.bin"); +MODULE_FIRMWARE("qcom/a640_gmu.bin"); +MODULE_FIRMWARE("qcom/a650_gmu.bin"); +MODULE_FIRMWARE("qcom/a650_sqe.fw"); +MODULE_FIRMWARE("qcom/a660_gmu.bin"); +MODULE_FIRMWARE("qcom/a660_sqe.fw"); + +const struct adreno_info a7xx_gpus[] = { + { + .chip_ids = ADRENO_CHIP_IDS(0x07030001), + .family = ADRENO_7XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a730_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70000.bin", + }, + .gmem = SZ_2M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a730_zap.mdt", + .hwcg = a730_hwcg, + .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ + .family = ADRENO_7XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "a740_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70200.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a740_zap.mdt", + .hwcg = a740_hwcg, + .address_space_size = SZ_16G, + }, { + /* sentinal */ + } +}; \ No newline at end of file diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 36392801f929..8af921193f1e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -20,542 +20,12 @@ bool allow_vram_carveout = false; MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); -static const struct adreno_info a2xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x02000000), - .family = ADRENO_2XX_GEN1, - .revn = 200, - .fw = { - [ADRENO_FW_PM4] = "yamato_pm4.fw", - [ADRENO_FW_PFP] = "yamato_pfp.fw", - }, - .gmem = SZ_256K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a2xx_gpu_init, - }, { /* a200 on i.mx51 has only 128kib gmem */ - .chip_ids = ADRENO_CHIP_IDS(0x02000001), - .family = ADRENO_2XX_GEN1, - .revn = 201, - .fw = { - [ADRENO_FW_PM4] = "yamato_pm4.fw", - [ADRENO_FW_PFP] = "yamato_pfp.fw", - }, - .gmem = SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a2xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x02020000), - .family = ADRENO_2XX_GEN2, - .revn = 220, - .fw = { - [ADRENO_FW_PM4] = "leia_pm4_470.fw", - [ADRENO_FW_PFP] = "leia_pfp_470.fw", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a2xx_gpu_init, - }, { - /* sentinal */ - } -}; - -static const struct adreno_info a3xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS( - 0x03000512, - 0x03000520 - ), - .family = ADRENO_3XX, - .revn = 305, - .fw = { - [ADRENO_FW_PM4] = "a300_pm4.fw", - [ADRENO_FW_PFP] = "a300_pfp.fw", - }, - .gmem = SZ_256K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x03000600), - .family = ADRENO_3XX, - .revn = 307, /* because a305c is revn==306 */ - .fw = { - [ADRENO_FW_PM4] = "a300_pm4.fw", - [ADRENO_FW_PFP] = "a300_pfp.fw", - }, - .gmem = SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03020000, - 0x03020001, - 0x03020002 - ), - .family = ADRENO_3XX, - .revn = 320, - .fw = { - [ADRENO_FW_PM4] = "a300_pm4.fw", - [ADRENO_FW_PFP] = "a300_pfp.fw", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03030000, - 0x03030001, - 0x03030002 - ), - .family = ADRENO_3XX, - .revn = 330, - .fw = { - [ADRENO_FW_PM4] = "a330_pm4.fw", - [ADRENO_FW_PFP] = "a330_pfp.fw", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a3xx_gpu_init, - }, { - /* sentinal */ - } -}; - -static const struct adreno_info a4xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x04000500), - .family = ADRENO_4XX, - .revn = 405, - .fw = { - [ADRENO_FW_PM4] = "a420_pm4.fw", - [ADRENO_FW_PFP] = "a420_pfp.fw", - }, - .gmem = SZ_256K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a4xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x04020000), - .family = ADRENO_4XX, - .revn = 420, - .fw = { - [ADRENO_FW_PM4] = "a420_pm4.fw", - [ADRENO_FW_PFP] = "a420_pfp.fw", - }, - .gmem = (SZ_1M + SZ_512K), - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a4xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x04030002), - .family = ADRENO_4XX, - .revn = 430, - .fw = { - [ADRENO_FW_PM4] = "a420_pm4.fw", - [ADRENO_FW_PFP] = "a420_pfp.fw", - }, - .gmem = (SZ_1M + SZ_512K), - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a4xx_gpu_init, - }, { - /* sentinal */ - } -}; - -static const struct adreno_info a5xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x05000600), - .family = ADRENO_5XX, - .revn = 506, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_128K + SZ_8K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | - ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a506_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05000800), - .family = ADRENO_5XX, - .revn = 508, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_128K + SZ_8K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a508_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05000900), - .family = ADRENO_5XX, - .revn = 509, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_256K + SZ_16K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - /* Adreno 509 uses the same ZAP as 512 */ - .zapfw = "a512_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05010000), - .family = ADRENO_5XX, - .revn = 510, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = SZ_256K, - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .init = a5xx_gpu_init, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05010200), - .family = ADRENO_5XX, - .revn = 512, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - }, - .gmem = (SZ_256K + SZ_16K), - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a512_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x05030002, - 0x05030004 - ), - .family = ADRENO_5XX, - .revn = 530, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", - }, - .gmem = SZ_1M, - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | - ADRENO_QUIRK_FAULT_DETECT_MASK, - .init = a5xx_gpu_init, - .zapfw = "a530_zap.mdt", - }, { - .chip_ids = ADRENO_CHIP_IDS(0x05040001), - .family = ADRENO_5XX, - .revn = 540, - .fw = { - [ADRENO_FW_PM4] = "a530_pm4.fw", - [ADRENO_FW_PFP] = "a530_pfp.fw", - [ADRENO_FW_GPMU] = "a540_gpmu.fw2", - }, - .gmem = SZ_1M, - /* - * Increase inactive period to 250 to avoid bouncing - * the GDSC which appears to make it grumpy - */ - .inactive_period = 250, - .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, - .init = a5xx_gpu_init, - .zapfw = "a540_zap.mdt", - }, { - /* sentinal */ - } -}; - -static const struct adreno_info a6xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x06010000), - .family = ADRENO_6XX_GEN1, - .revn = 610, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - }, - .gmem = (SZ_128K + SZ_4K), - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a610_zap.mdt", - .hwcg = a612_hwcg, - /* - * There are (at least) three SoCs implementing A610: SM6125 - * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does - * not have speedbinning, as only a single SKU exists and we - * don't support khaje upstream yet. Hence, this matching - * table is only valid for bengal. - */ - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 206, 1 }, - { 200, 2 }, - { 157, 3 }, - { 127, 4 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06010800), - .family = ADRENO_6XX_GEN1, - .revn = 618, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 169, 1 }, - { 174, 2 }, - ), - }, { - .machine = "qcom,sm4350", - .chip_ids = ADRENO_CHIP_IDS(0x06010900), - .family = ADRENO_6XX_GEN1, - .revn = 619, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 138, 1 }, - { 92, 2 }, - ), - }, { - .machine = "qcom,sm6375", - .chip_ids = ADRENO_CHIP_IDS(0x06010901), - .family = ADRENO_6XX_GEN1, - .revn = 619, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 190, 1 }, - { 177, 2 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06010900), - .family = ADRENO_6XX_GEN1, - .revn = 619, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 120, 4 }, - { 138, 3 }, - { 169, 2 }, - { 180, 1 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x06030001, - 0x06030002 - ), - .family = ADRENO_6XX_GEN1, - .revn = 630, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a630_zap.mdt", - .hwcg = a630_hwcg, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06040001), - .family = ADRENO_6XX_GEN2, - .revn = 640, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a640_gmu.bin", - }, - .gmem = SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 1, 1 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06050002), - .family = ADRENO_6XX_GEN3, - .revn = 650, - .fw = { - [ADRENO_FW_SQE] = "a650_sqe.fw", - [ADRENO_FW_GMU] = "a650_gmu.bin", - }, - .gmem = SZ_1M + SZ_128K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a650_zap.mdt", - .hwcg = a650_hwcg, - .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 1, 1 }, - { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ - { 3, 2 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06060001), - .family = ADRENO_6XX_GEN4, - .revn = 660, - .fw = { - [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a660_gmu.bin", - }, - .gmem = SZ_1M + SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a660_zap.mdt", - .hwcg = a660_hwcg, - .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06030500), - .family = ADRENO_6XX_GEN4, - .fw = { - [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a660_gmu.bin", - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a660_zap.mbn", - .hwcg = a660_hwcg, - .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 117, 0 }, - { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ - { 190, 1 }, - ), - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06080000), - .family = ADRENO_6XX_GEN2, - .revn = 680, - .fw = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - [ADRENO_FW_GMU] = "a640_gmu.bin", - }, - .gmem = SZ_2M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06090000), - .family = ADRENO_6XX_GEN4, - .fw = { - [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a660_gmu.bin", - }, - .gmem = SZ_4M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a690_zap.mdt", - .hwcg = a690_hwcg, - .address_space_size = SZ_16G, - }, { - /* sentinal */ - } -}; - -static const struct adreno_info a7xx_gpus[] = { - { - .chip_ids = ADRENO_CHIP_IDS(0x07030001), - .family = ADRENO_7XX_GEN1, - .fw = { - [ADRENO_FW_SQE] = "a730_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70000.bin", - }, - .gmem = SZ_2M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a730_zap.mdt", - .hwcg = a730_hwcg, - .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ - .family = ADRENO_7XX_GEN2, - .fw = { - [ADRENO_FW_SQE] = "a740_sqe.fw", - [ADRENO_FW_GMU] = "gmu_gen70200.bin", - }, - .gmem = 3 * SZ_1M, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, - .init = a6xx_gpu_init, - .zapfw = "a740_zap.mdt", - .hwcg = a740_hwcg, - .address_space_size = SZ_16G, - }, { - /* sentinal */ - } -}; +extern const struct adreno_info a2xx_gpus[]; +extern const struct adreno_info a3xx_gpus[]; +extern const struct adreno_info a4xx_gpus[]; +extern const struct adreno_info a5xx_gpus[]; +extern const struct adreno_info a6xx_gpus[]; +extern const struct adreno_info a7xx_gpus[]; static const struct adreno_info *gpulist[] = { a2xx_gpus, @@ -566,34 +36,6 @@ static const struct adreno_info *gpulist[] = { a7xx_gpus, }; -MODULE_FIRMWARE("qcom/a300_pm4.fw"); -MODULE_FIRMWARE("qcom/a300_pfp.fw"); -MODULE_FIRMWARE("qcom/a330_pm4.fw"); -MODULE_FIRMWARE("qcom/a330_pfp.fw"); -MODULE_FIRMWARE("qcom/a420_pm4.fw"); -MODULE_FIRMWARE("qcom/a420_pfp.fw"); -MODULE_FIRMWARE("qcom/a530_pm4.fw"); -MODULE_FIRMWARE("qcom/a530_pfp.fw"); -MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); -MODULE_FIRMWARE("qcom/a530_zap.mdt"); -MODULE_FIRMWARE("qcom/a530_zap.b00"); -MODULE_FIRMWARE("qcom/a530_zap.b01"); -MODULE_FIRMWARE("qcom/a530_zap.b02"); -MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); -MODULE_FIRMWARE("qcom/a619_gmu.bin"); -MODULE_FIRMWARE("qcom/a630_sqe.fw"); -MODULE_FIRMWARE("qcom/a630_gmu.bin"); -MODULE_FIRMWARE("qcom/a630_zap.mbn"); -MODULE_FIRMWARE("qcom/a640_gmu.bin"); -MODULE_FIRMWARE("qcom/a650_gmu.bin"); -MODULE_FIRMWARE("qcom/a650_sqe.fw"); -MODULE_FIRMWARE("qcom/a660_gmu.bin"); -MODULE_FIRMWARE("qcom/a660_sqe.fw"); -MODULE_FIRMWARE("qcom/leia_pfp_470.fw"); -MODULE_FIRMWARE("qcom/leia_pm4_470.fw"); -MODULE_FIRMWARE("qcom/yamato_pfp.fw"); -MODULE_FIRMWARE("qcom/yamato_pm4.fw"); - static const struct adreno_info *adreno_info(uint32_t chip_id) { /* identify gpu: */ From patchwork Tue Dec 5 22:03:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 750446 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aixCNeFl" Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 428B6D7F; Tue, 5 Dec 2023 14:06:27 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1d06d42a58aso35403955ad.0; Tue, 05 Dec 2023 14:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701813986; x=1702418786; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZfGTVvgq7n98tDeI+oB8ofi/GtnZCvkbAjomQZwW1cY=; b=aixCNeFlOCSTmzD9kQrJG3xq6cCThT0N6x42oaGvYQVX62Xc1b2Y/4HqVQf8SgWYgQ ZV7Fi2HgwYEjCiJ2vIekn4I8Y/qOeACfEmMnGAlBzYDFpS1G6J6pP528tDbKALRvh9vL dlk0ut2/iiaU/UoIP3xTXibstUoB2DiuvbDi7PipChTBGfLyI9e2cio619KAGdanH/fZ 0nMOmR7LT7pbf4qWK3NLk5qXB1SXWV/ky12/EJNr/Dpj/+Z0gN2JyDEuTg898a2HrIXx UA7i0wOfBHGFmX3Fc262SZ5BIgbNe9rH03Ob7gy3ZhXnVl6+eulTJrE3qk7cBdjQ3d4O YAAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701813986; x=1702418786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZfGTVvgq7n98tDeI+oB8ofi/GtnZCvkbAjomQZwW1cY=; b=iQhpd0SLySrE6Io3Az5PgoX3coLr+FY+bUoZG5FJveM28EbJRLOUU6PkW16A2s+j3a 3gyzoZYBo73MC5bL+OQWVgp26K/zjN3uVBxM5vMZJYOrObB6tW3EV5vtHpxvxzW6ky0D m+mtJ22MiBI0aaIfKI48ibIvCaKSVjPiu/v3OJYrkLLbGeNNqf/jpI1PONWfVXECWJhG IQNYDZQjVHCkYfNJJK6l/hPEQVWb1n/m2L8PFGE9wGfA3L7xxyMoLcq9oJOQGIWIyDde fJyB6gmGMVAtONgG8xNr6G9Yovq/Cz473cj6YNGpodl0Uz/Ng6nUIhDzBAT6S0DnCayn Hy7g== X-Gm-Message-State: AOJu0Yx2+c6RwN7PLrICUwBAV6b+W+sx1vZbxV6Qit02nuDPDgiQQ9tI Z6oNMVvl2z5U0/yB8p7oIepP+0KwhhM= X-Google-Smtp-Source: AGHT+IETLfRI/+vuaoElPPv+EjDm+Sp72Ua1AScWFXqXsgoOIGdLwWdKpoXF/M6bbHYTOeLLye0xfw== X-Received: by 2002:a17:902:eccd:b0:1d0:c906:f5e0 with SMTP id a13-20020a170902eccd00b001d0c906f5e0mr1345297plh.72.1701813986187; Tue, 05 Dec 2023 14:06:26 -0800 (PST) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id mi7-20020a17090b4b4700b00286a708cd07sm4189353pjb.57.2023.12.05.14.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 14:06:25 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Konrad Dybcio , Akhil P Oommen , Douglas Anderson , Bjorn Andersson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Date: Tue, 5 Dec 2023 14:03:30 -0800 Message-ID: <20231205220526.417719-5-robdclark@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231205220526.417719-1-robdclark@gmail.com> References: <20231205220526.417719-1-robdclark@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rob Clark Introduce a6xx_info where we can stash gen specific stuff without polluting the toplevel adreno_info struct. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +++++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++- 4 files changed, 58 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index a35d4c112a61..3fb9e249567a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -7,6 +7,7 @@ */ #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" @@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", - .hwcg = a612_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a612_hwcg, + }, /* * There are (at least) three SoCs implementing A610: SM6125 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does @@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + .a6xx = &(struct a6xx_info) { + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 169, 1 }, @@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 138, 1 }, @@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 190, 1 }, @@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 120, 4 }, @@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", - .hwcg = a630_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a630_hwcg, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06040001), .family = ADRENO_6XX_GEN2, @@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a640_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 1, 1 }, @@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", - .hwcg = a650_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a650_hwcg, + }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", - .hwcg = a660_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a660_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x06030500), @@ -642,7 +661,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", - .hwcg = a660_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a660_hwcg, + }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -663,7 +684,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a640_hwcg, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06090000), .family = ADRENO_6XX_GEN4, @@ -677,7 +700,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", - .hwcg = a690_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a690_hwcg, + }, .address_space_size = SZ_16G, }, { /* sentinal */ @@ -822,7 +847,9 @@ const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a730_zap.mdt", - .hwcg = a730_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a730_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ @@ -837,7 +864,9 @@ const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", - .hwcg = a740_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a740_hwcg, + }, .address_space_size = SZ_16G, }, { /* sentinal */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index e0414d0753ad..a064eb42eedd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!adreno_gpu->info->a6xx->hwcg) return; if (adreno_is_a630(adreno_gpu)) @@ -434,7 +434,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); - for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) + for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 34822b080759..1840c1f3308e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,15 @@ extern bool hang_debug; +/** + * struct a6xx_info - a6xx specific information from device table + * + * @hwcg: hw clock gating register sequence + */ +struct a6xx_info { + const struct adreno_reglist *hwcg; +}; + struct a6xx_gpu { struct adreno_gpu base; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 5d094c5ec363..cba53203de98 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -81,6 +81,8 @@ struct adreno_speedbin { uint16_t speedbin; }; +struct a6xx_info; + struct adreno_info { const char *machine; /** @@ -97,7 +99,9 @@ struct adreno_info { struct msm_gpu *(*init)(struct drm_device *dev); const char *zapfw; u32 inactive_period; - const struct adreno_reglist *hwcg; + union { + const struct a6xx_info *a6xx; + }; u64 address_space_size; /** * @speedbins: Optional table of fuse to speedbin mappings