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Sun, 3 Dec 2023 07:40:34 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:31 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 2/8] ARM: dts: rockchip: rv1126: Serial aliases Date: Sun, 3 Dec 2023 23:39:58 +1100 Message-Id: <20231203124004.2676174-3-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add serial aliases for uart nodes so that serial devices are created Signed-off-by: Tim Lunn --- Changes in v3: - Add missing serial5 alias arch/arm/boot/dts/rockchip/rv1126.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 9ccd1bad6229..adb11a43c5db 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -21,6 +21,12 @@ / { aliases { i2c0 = &i2c0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; }; cpus { From patchwork Sun Dec 3 12:40:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 750179 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=feathertop.org header.i=@feathertop.org header.b="cYzz9sjT"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="Yo4Qtbuc" Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A11FBC2 for ; Sun, 3 Dec 2023 04:40:57 -0800 (PST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 1763A5C00C7; Sun, 3 Dec 2023 07:40:57 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); 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Sun, 3 Dec 2023 07:40:52 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:49 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 4/8] ARM: dts: rockchip: rv1126: Add i2c2 nodes Date: Sun, 3 Dec 2023 23:40:00 +1100 Message-Id: <20231203124004.2676174-5-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add i2c2 node and i2c2_xfer pinctrl for Rockchip RV1126 Signed-off-by: Tim Lunn --- (no changes since v1) arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 10 ++++++++++ arch/arm/boot/dts/rockchip/rv1126.dtsi | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 4f85b7b3fc4c..167a48afa3a4 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -87,6 +87,16 @@ i2c0_xfer: i2c0-xfer { <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + i2c2 { + /omit-if-no-ref/ + i2c2_xfer: i2c2-xfer { + rockchip,pins = + /* i2c2_scl */ + <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sda */ + <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; pwm2 { /omit-if-no-ref/ pwm2m0_pins: pwm2m0-pins { diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index adb11a43c5db..bb603cae13df 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -21,6 +21,7 @@ / { aliases { i2c0 = &i2c0; + i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -237,6 +238,20 @@ i2c0: i2c@ff3f0000 { status = "disabled"; }; + i2c2: i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@ff410000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff410000 0x100>; From patchwork Sun Dec 3 12:40:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 750178 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=feathertop.org header.i=@feathertop.org header.b="r7zE6P8J"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="oqf5Wclf" Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C549C2 for ; Sun, 3 Dec 2023 04:41:14 -0800 (PST) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 035975C0136; Sun, 3 Dec 2023 07:41:14 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); 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Sun, 3 Dec 2023 07:41:09 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:41:06 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 6/8] ARM: dts: rockchip: Add rv1109 SoC Date: Sun, 3 Dec 2023 23:40:02 +1100 Message-Id: <20231203124004.2676174-7-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Rockchip rv1109 SoC is a dual core version of the rv1126. It is otherwise identical and shares the same device tree config. This patch introduces a dtsi file to drop the additional cpu nodes. Taken from Rockchip BSP kernel. Signed-off-by: Tim Lunn --- (no changes since v2) Changes in v2: - new patch arch/arm/boot/dts/rockchip/rv1109.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip/rv1109.dtsi diff --git a/arch/arm/boot/dts/rockchip/rv1109.dtsi b/arch/arm/boot/dts/rockchip/rv1109.dtsi new file mode 100644 index 000000000000..9cbaa08ab1b8 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1109.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1126.dtsi" + +/ { + compatible = "rockchip,rv1109"; + + cpus { + /delete-node/ cpu@f02; + /delete-node/ cpu@f03; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; From patchwork Sun Dec 3 12:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 750177 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=feathertop.org header.i=@feathertop.org header.b="PUrUdvlu"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="A07QQXgV" Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 633EBC2 for ; Sun, 3 Dec 2023 04:41:32 -0800 (PST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id CB26A5C015B; Sun, 3 Dec 2023 07:41:31 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sun, 03 Dec 2023 07:41:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=feathertop.org; h=cc:cc:content-transfer-encoding:content-type:date:date:from :from:in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1701607291; x= 1701693691; bh=Vn2Ued8QnK1Z3h42bOuO5aQ4ZuaH4mGAuUy6STjbYSk=; b=P UrUdvlue4hY6gYJ2LvWLRtK4qnKsrUYXO+doNoJ2vglB1VKtTUVc0ED6i+I3fTzT 49BW5oApPpql2aVmbKLQm2rOQmOusCqBpOIzyUJsQ3CgY1KCaqPLO2cjT0UdtoGX 42flvIfgHaKGvXu6w/VEnqRavHVavf7/lMYbWt/p0naiebNLwvd7MwoZ0Hkr3z6t u15eM/uoBiCT9wa/1UQI2k6KXoBsxBZFWQnivj1ZGKVQaMKOZDfrxM7DYhKwMmpk XIIZdwmgn+F4n06vtc4yyLHS16p2icgZsrWT2v3v7DR9zE1N62NC+8hueTT/yVO9 86B2dVkYN1/bQ42zKaQfg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1701607291; x= 1701693691; bh=Vn2Ued8QnK1Z3h42bOuO5aQ4ZuaH4mGAuUy6STjbYSk=; b=A 07QQXgVTZeiDFt3CsDK6vwYKchZZHsHU6jJJ3KxdDxd4oKsQ/8Mur0Agrvs1z2mf tonQWtm7bmMcW4GapprD8QcjCzFYPmlTfN2dsJenZ4ZWXb1rXzxdGTSoLtWmIG5p od2A8L5zcMUUobtT3OTVrppR5WRP0YB5pehAiYjXx2dWe3tcJW3ivD/KIX4u7N4Z N0+0V3X7LsITLCWhS1aymoJyI5ap8+G5e37DGARN0b/Ye3Q+771NatCXXBzqTTgx pwrzq4lTzsKTpTpGI9yxgxOfWsBeUTjnKATFZDwf8FcqeGzaSMcI8W368/6X/swG fmkdn7LgkkNxs77aPo+oA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrudejgedggeefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepvfhimhcu nfhunhhnuceothhimhesfhgvrghthhgvrhhtohhprdhorhhgqeenucggtffrrghtthgvrh hnpeefffeuhfetgeeikeejvefgtdefteehgfdvhfetfeeuffeuhffhfeekgfekgeehieen ucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehtihhmse hfvggrthhhvghrthhophdrohhrgh X-ME-Proxy: Feedback-ID: i1f8241ce:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 3 Dec 2023 07:41:26 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:41:23 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn , Rob Herring Subject: [PATCH v3 8/8] dt-bindings: arm: rockchip: Add Sonoff iHost Date: Sun, 3 Dec 2023 23:40:04 +1100 Message-Id: <20231203124004.2676174-9-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sonoff iHost is a smart home hub with built in radios for wifi/bt and Zigbee. It is based off the Rockchip RV1126 (or RV1109) SoC. Signed-off-by: Tim Lunn Acked-by: Rob Herring --- (no changes since v2) Changes in v2: - Collect Robh Ack for dt-bindings patch Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 5f7c6c4aad8f..a26bbcd00deb 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -922,6 +922,13 @@ properties: - const: rockchip,rk3568-bpi-r2pro - const: rockchip,rk3568 + - description: Sonoff iHost Smart Home Hub + items: + - const: itead,sonoff-ihost + - enum: + - rockchip,rv1126 + - rockchip,rv1109 + additionalProperties: true ...