From patchwork Thu Aug 22 22:09:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 172063 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1488527ily; Thu, 22 Aug 2019 15:09:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjyV5UAkN4SR9Fb8gpwLlHzuKfl0ymFGsjorFHOm+SORwoy/jY2prSe++qAfV6TvTpCKMH X-Received: by 2002:a17:902:7581:: with SMTP id j1mr1076337pll.289.1566511766518; Thu, 22 Aug 2019 15:09:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566511766; cv=none; d=google.com; s=arc-20160816; b=jEDoPGb+YQzLFZ3WI1LY1O4d4JmxBD8KkgMLIDmbVrT3Q5AVWmZ0Ci6/oiBXucp/NN 17wkTn24/uNF+uyZb2rFy9V/fIg3zk3UTs73j3PKdL5URs29eAdW/rRq8yYEjJg6pjDW Y5nVe5v7dYo/IIHkbKbPSYBQwqeYyfHD1rEmCg896xPmIra+/b1VZzZ6XKlLHUeI5lsi RQ+0KITcBDINgKVZ0FToS17VpH5XL0SYhaxxzkcU90jq3dkuIo5HghdML+lXB2ffaxfs mFyaS/2G9gWdH//cWUAgpcCSmIrOgtPXm6Ix1ndm/jbOrn4d27rkLPxpj8CRhQhhTeCN 1gWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=vEgIQCU90XTwHLlVQoE1B9Sv6mWqmfOra2UuJPbbnMA=; b=ZJehprIB/WjXqDEJRKIzGJ2f2QY9GhW/PwmPlgSL6d9YdsH8ZVszFuA3TkCwl3/ZLk Z2rKLM+s0VaAICUhoO5P/nmkufDLEq9ww1UpsvpDwuDM9UmrK0RcaMg7d5IForfRNx9T n36h2aLwn4dh9LDOdeToSVrYN1SQ7kz9VxdLWuACsJMNnJecVu6onI/nwCepjNJbDPFr CT4P2T9fU5xDqI9HXX9z4ZUbaqWrpOyHMWfai6MFAOnT4lcXTvUn8PtXNtlNJxNkd9GL MAfNo+5ROdUeb207ah9Bs2vk5AgztBLG5NBZvjpvodmYW4X0J6kbND1T73Ja6TDcAFcn r3ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s0bI2oyU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id s7sm377432pfb.138.2019.08.22.15.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2019 15:09:18 -0700 (PDT) From: Mathieu Poirier To: yabinc@google.com, suzuki.poulose@arm.com, leo.yan@linaro.org Cc: mike.leach@arm.com, alexander.shishkin@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] coresight: tmc: Make memory width mask computation into a function Date: Thu, 22 Aug 2019 16:09:14 -0600 Message-Id: <20190822220915.8876-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190822220915.8876-1-mathieu.poirier@linaro.org> References: <20190822220915.8876-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make the computation of a memory ask representing the width of the memory bus into a function so that it can be re-used by the ETR driver. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etf.c | 23 ++------------- drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 3 files changed, 31 insertions(+), 21 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 23b7ff00af5c..807416b75ecc 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, * traces. */ if (!buf->snapshot && to_read > handle->size) { - u32 mask = 0; - - /* - * The value written to RRP must be byte-address aligned to - * the width of the trace memory databus _and_ to a frame - * boundary (16 byte), whichever is the biggest. For example, - * for 32-bit, 64-bit and 128-bit wide trace memory, the four - * LSBs must be 0s. For 256-bit wide trace memory, the five - * LSBs must be 0s. - */ - switch (drvdata->memwidth) { - case TMC_MEM_INTF_WIDTH_32BITS: - case TMC_MEM_INTF_WIDTH_64BITS: - case TMC_MEM_INTF_WIDTH_128BITS: - mask = GENMASK(31, 4); - break; - case TMC_MEM_INTF_WIDTH_256BITS: - mask = GENMASK(31, 5); - break; - } + u32 mask = tmc_get_memwidth_mask(drvdata); /* * Make sure the new size is aligned in accordance with the - * requirement explained above. + * requirement explained in function tmc_get_memwidth_mask(). */ to_read = handle->size & mask; /* Move the RAM read pointer up */ diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 3055bf8e2236..1cf82fa58289 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata) writel_relaxed(0x0, drvdata->base + TMC_CTL); } +u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) +{ + u32 mask = 0; + + /* + * When moving RRP or an offset address forward, the new values must + * be byte-address aligned to the width of the trace memory databus + * _and_ to a frame boundary (16 byte), whichever is the biggest. For + * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four + * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must + * be 0s. + */ + switch (drvdata->memwidth) { + case TMC_MEM_INTF_WIDTH_32BITS: + /* fallthrough */ + case TMC_MEM_INTF_WIDTH_64BITS: + /* fallthrough */ + case TMC_MEM_INTF_WIDTH_128BITS: + mask = GENMASK(31, 4); + break; + case TMC_MEM_INTF_WIDTH_256BITS: + mask = GENMASK(31, 5); + break; + } + + return mask; +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret = 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 9dbcdf453e22..71de978575f3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); +u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); /* ETB/ETF functions */ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); From patchwork Thu Aug 22 22:09:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 172062 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1488496ily; Thu, 22 Aug 2019 15:09:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqyfw6T+RT8+6qGGu24Qm2fF1qy/i9XTAFZbddVXIkaPlZhVaDApjR2ZY8cSKP2yP4Qgswyr X-Received: by 2002:a17:90a:d593:: with SMTP id v19mr1913814pju.1.1566511764175; Thu, 22 Aug 2019 15:09:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566511764; cv=none; d=google.com; s=arc-20160816; b=AIl5eiD0fAVysk4Xzj5oAckn9udGHKIWbbFi2y3ZHMBwThYM0S+2yArww51hHKsr+J 8Quv8FKRBCVe/Pzb11+ZsOAOSQkLlaHm/2LtjHxz23Lw+pmrE9IFxufvY+RUKytvpR6u itxl/RGN9ZiLEN13p4bXvDQiB4uauTQbJ6qnipBOg4NWINZVbupgxl0hsxYkHcux3U0K rrBXGqVY7eHVWJFxpE0PZ6jciU0XAZ+G4VU9h/2EqiQx106Whjr3SwpPbzYQ40UvrQIY HdkopSZMRz7qOcFFkU/zLkZt+vjM0fJAu4qT5TPVsmbZvm6yWza5V0pErsDx5zx9ABKi rPkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=9zuadHq2oNAonLqdCJokcmV7Tuo9vqcylSnraeruuq0=; b=kGlpW190rFI0gfAVu9jhpIySu76CRux9Qjc9jEa9dFIGXX81UGciSTA44k8Hocsqwb ceATrr0hpzSNvMHaFsDZiPDgoJhoNgFHIvhH/i18Tx7DnyxnZInhzovY2tGaqP8ndTm/ DOmfuGYx6yvXSz0EnvbbgKzp3rdZ02rU5EKPWNw13wXDdIlGHX7lOM3P6eHTiAwFHp1p aHR1Bgy1XPgxJpi3UDXy1VVPCcDVVnczSaesYF4ZMG75kysv62fy6NKIYZNFz1Ekwi55 e3RFWrmak47krztRM2EnBUEn+joEAEfYAl/B/0QufqxLBJB9+re3BnmYDWXbSsMhNbFd 0g4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kpr3QTAH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id s7sm377432pfb.138.2019.08.22.15.09.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2019 15:09:19 -0700 (PDT) From: Mathieu Poirier To: yabinc@google.com, suzuki.poulose@arm.com, leo.yan@linaro.org Cc: mike.leach@arm.com, alexander.shishkin@linux.intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] coresight: tmc-etr: Add barrier packet when moving offset forward Date: Thu, 22 Aug 2019 16:09:15 -0600 Message-Id: <20190822220915.8876-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190822220915.8876-1-mathieu.poirier@linaro.org> References: <20190822220915.8876-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds barrier packets in the trace stream when the offset in the data buffer needs to be moved forward. Otherwise the decoder isn't aware of the break in the stream and can't synchronise itself with the trace data. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etr.c | 43 ++++++++++++++----- 1 file changed, 33 insertions(+), 10 deletions(-) -- 2.17.1 Tested-by: Yabin Cui diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 4f000a03152e..0e4cd6ec5f28 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -946,10 +946,6 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) WARN_ON(!etr_buf->ops || !etr_buf->ops->sync); etr_buf->ops->sync(etr_buf, rrp, rwp); - - /* Insert barrier packets at the beginning, if there was an overflow */ - if (etr_buf->full) - tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset); } static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) @@ -1415,10 +1411,11 @@ static void tmc_free_etr_buffer(void *config) * buffer to the perf ring buffer. */ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, + unsigned long src_offset, unsigned long to_copy) { long bytes; - long pg_idx, pg_offset, src_offset; + long pg_idx, pg_offset; unsigned long head = etr_perf->head; char **dst_pages, *src_buf; struct etr_buf *etr_buf = etr_perf->etr_buf; @@ -1427,7 +1424,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf, pg_idx = head >> PAGE_SHIFT; pg_offset = head & (PAGE_SIZE - 1); dst_pages = (char **)etr_perf->pages; - src_offset = etr_buf->offset + etr_buf->len - to_copy; while (to_copy > 0) { /* @@ -1475,7 +1471,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, void *config) { bool lost = false; - unsigned long flags, size = 0; + unsigned long flags, offset, size = 0; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etr_perf_buffer *etr_perf = config; struct etr_buf *etr_buf = etr_perf->etr_buf; @@ -1503,11 +1499,39 @@ tmc_update_etr_buffer(struct coresight_device *csdev, spin_unlock_irqrestore(&drvdata->spinlock, flags); size = etr_buf->len; + offset = etr_buf->offset; + lost |= etr_buf->full; + + /* + * The ETR buffer may be bigger than the space available in the + * perf ring buffer (handle->size). If so advance the offset so that we + * get the latest trace data. In snapshot mode none of that matters + * since we are expected to clobber stale data in favour of the latest + * traces. + */ if (!etr_perf->snapshot && size > handle->size) { - size = handle->size; + u32 mask = tmc_get_memwidth_mask(drvdata); + + /* + * Make sure the new size is aligned in accordance with the + * requirement explained in function tmc_get_memwidth_mask(). + */ + size = handle->size & mask; + offset = etr_buf->offset + etr_buf->len - size; + + if (offset >= etr_buf->size) + offset -= etr_buf->size; lost = true; } - tmc_etr_sync_perf_buffer(etr_perf, size); + + /* + * Insert barrier packets at the beginning, if there was an overflow + * or if the offset had to be brought forward. + */ + if (lost) + tmc_etr_buf_insert_barrier_packet(etr_buf, offset); + + tmc_etr_sync_perf_buffer(etr_perf, offset, size); /* * In snapshot mode we simply increment the head by the number of byte @@ -1518,7 +1542,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev, if (etr_perf->snapshot) handle->head += size; - lost |= etr_buf->full; out: /* * Don't set the TRUNCATED flag in snapshot mode because 1) the