From patchwork Thu Nov 30 01:10:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748556 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RPbLdFCJ" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2070.outbound.protection.outlook.com [40.107.244.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D9A8D7F; Wed, 29 Nov 2023 17:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XXFEYKsOQXGSHNx/lvA5mDO//TOdy7bfcifppRBhtOk3lMlTDZXyLuLUyQOM0sInG48Z1OH8gbAkvmd60w3QitMNrobafMPtoRw0PPwpX4p33zTo8QxaXbEFi226AxFq/kiv4luxEAOZ4WkOd3jIlFMZJRUwn6/Q9ULPtirlOCof6oPb9P4kHsFc9+RL4YDUCWA8Qytcrwyfkf+/bxw3LffLrYW7fYBK5qJS+ZlkZK95hhwxEj1a+jHXEjXfZ6DIsBEfMvpMUNw+xSPNslmMfFCAAZwDhTcyDmi71Ys1Ofz5o0T1N7M1xB4S/y+IlUY9gmEOEDre/Hwm5tX2eIHDdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TeNlyomNkLn0vDrMhnXRZEG4tXI6kjRAm58pilBJJWY=; b=J9v0skXnxpK9wrcH0+M+LX/agrU7B+TBYzOCgWwnrkMPJ2GSxp1CeR90bsQSa63Laebo8gZpo36vDmvI8FS1C0ZMfyc7zcLPSZV4nEfBW7HRuIN83wHvlx+QXgOpXWEQXAjcAugw8q+hLl6mkhYMKUmzmiC69zBv/UYCiDpIRasdfpqolxiE6i8zF9++cvyiDZfBg7T1q7q3F8cCwRKpDjsz2jwWKXoJ75G8TzFy/izBfNPP56tXwAHjDpjJDP/lILvMdDmNqnY7Ucz2XdM+OBVu1/cFv5lfbJf9hxhjtQxShGfD6sBSkvkrQP2/wQRVkewrz8sEbJJ9T1PWnVEhWg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TeNlyomNkLn0vDrMhnXRZEG4tXI6kjRAm58pilBJJWY=; b=RPbLdFCJzmrVks0WTIxkHSvZFDRokh9D3A7VdSiGc2sYySwYag6Kfpx6OI7CAo3CqIn6jXsG21Y8YRvyXFy+tdLhxLrOHdwOttpmFN2k3hgwf4gmYYCzFHkgR6cMhMkJb4lZjoNRvphOb5NpNAC83xrXtFPs6WphKkcWll8pTgm1KKuquyWYvBVWG4e234AsGUGQ1Sq+wrQlXJhmeWlU+bzrrzkbiydliXllW2XLkRA35Ukrffo3A6F7mna9xp8ko5K3ztkX1chvOAy2y9gvwBL4TTxIajqFkVUt5ypfeQpAaOgaGp8X+9uhO/4FoIF53ojtO2Bo+d8NLuTNq2gYTA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DM6PR12MB4484.namprd12.prod.outlook.com (2603:10b6:5:28f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.23; Thu, 30 Nov 2023 01:10:56 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:55 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 03/30] ACPI: IORT: Make a iort_iommu_for_each_id() Date: Wed, 29 Nov 2023 21:10:10 -0400 Message-ID: <3-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR11CA0128.namprd11.prod.outlook.com (2603:10b6:806:131::13) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DM6PR12MB4484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d5393b6-bc80-4b4e-b90c-08dbf1412d33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WACztOEs8ClSQyQdofD6SX2bBXzfuSg2e7e3+uDtfk99ONwwvVbPkCjQh7TK2zT3OKVQESNy+e3Z51zhWf81cOrl5Nu3GL5sNi79w7k59rEbqA/JAmG5Vm2LmlvvBgBZz0HQsoc2FPIh0dnp5AdiZaPFjFf7RmKKjldH/SQCrDt+2VWUFGj/vL2oMzXtI3GD+KFiX8KXxwCq7cTLou4caG3KSGsVuLRswSfT3CZw+2BdW2kNB6SDpjw4yTSizCpVsXSF90tNhXTBLEJ25WXYjfRhXkgy/7XZWBs3jXJxucSdcjN488G0WclTa0TqryykNvp1Y+bZBzwpeEFxLZPzeZcpetiH+2EPn8f2Uj3KihUdoxyrmqvkkopqrexACNFWjcl5lnv+7sZHAZGGFnT9B2nbKyR4oGHkf/1azWtq2rVxEPnIGkeY6DSMShC58tqlrfcsq5NHsQd+eKj0CHP3EWJSvo9Yg0b3g0GMoqGpRgwhjBfS+G6rX9+1t/ru1JQNVT4oGTUybHWfS7gbOiHzn7hvaWbhHVHyP8WCOqsrwdbMIRO6wzJNPKGiODXjHBpDcNaq9dQQO6u00YNzR1hGvc+6jdHppRN7yorUJl8bBf5QcfUhih0WFb8koHc2LtjqtBQRuuRnW7Uh6d1dYzJsl0bhk5jFOJJlnTLNdUpn9U0= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(376002)(366004)(396003)(136003)(346002)(39860400002)(230922051799003)(1800799012)(451199024)(186009)(64100799003)(83380400001)(1191002)(2616005)(26005)(921008)(66476007)(66946007)(66556008)(7406005)(7366002)(7416002)(110136005)(2906002)(8676002)(4326008)(8936002)(86362001)(5660300002)(41300700001)(6506007)(6666004)(6512007)(36756003)(316002)(478600001)(6486002)(202311291699003)(38100700002)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jbOz4qPPEyiOOTp5vSMtAdERSp4SLZpY5rsvqdaXGkZetG8bfl5rmfpr/jibgOqs/O+W3tXSVdFUlV7d52t8GJt7XGeakPRSsUutrfHLe/HReDathpx+nlzHTnV8Nr+O1L25XeMDMFb2/JP82vgQ07DF/uV76YUZUW8KTPqsh9CdgzJRG4GNCk9OBf5YLuFynV7gr+HInimMfbobXW8UfD7p3q4zUapr6rArgHsn6KAwPL7UzZrwvOx1vsXnkcxEkKKqW27tHYGj/MKNJaALJpDDyJk9HZ19BvmAyybXsSpsfLqGjezKayT+3VagLHNtMdyVeed0ux857Ymg5k/xU9bHUluBx374QGxoPaPvsWJi/k87uw/N+AgouafHOObrLrmW2TW1U9pDMnCCo6pU7upfHWHxu7ZY2DBNyaLkb0EusqHviqde9tq+uPhjhc6NNrTuSkyEMc1dPnzANU6WFiJlFdW1ZaNxpLJAUJ0nnUqRTCZ1+f2AVkbBn7tyta8cKWvM343hDQNy8q6MKICys+bp5JzL30camvF8studYCoGEvG9hi7iRVFRuShf7Yu8XHfQv45ftoW2KhO7oxiX2MeIwWSUPK89byMgXH6EGaRuDgEYNAFAQHY7FHMaB+jOCGY+2EUWtpFm+lPZy0C5WD6I64CjmNm5SPXuhckTmqOMMOdVoIELYZQWJTvspap4uLY5wILPfaqMg7C/lPiQbEx1pxZ4W+GinXfKom4ou43Kk/19ZQFtZKog6Zr7SvUo/uaNaP/D5bC13IOOD/+qGmD7kHxpeSvnZs+lVkgMUXRDYd8XGoR2meMKKERnXxS+o9674npHTmS6yzEZTOgU5Dkw7xOCj0mwa7trt1YAK/8bDRcOUxNhhztSlYXDB9lNJAH0SzOSkxf9U+A2vWEVtgIZ+2uGeWIyis33W6ifAolk6goH+3sqLRGV77psDnrVbcm8GJsuxmnSC+QtzUMDGoBsdKUIFuxS9Dmf++6UWY+K+zAnsw2ToF3vzE+HOOL23bkDVxVZhnjyi+fOZl+/G3YDTQkxWPLGdrZbTCOtSy1fqqCHkhLAy+gO7FpmJrN3SOfCdk9Cgx3SEHdqGDNqZirux0idGI2EXnev8Av4c5vAvDk22LMBzGFg39qsbJlpZm5vueasytknE2aL+nyF2d4FzTei2bg301kupvqwynViN5PFUUH2+QJBodisS/dwZRWeYoqnE8RV+AcsSlRbAH6jvSoHyFrcl8Nl6LIXd9ya7qKyLjahOuoim4ME3oBJKPXxCO2q0oRVNqtnUD3LhUmd1FK2KoAOMVdmlEHdT9a7Ek25F22/K3T4CLTDaKWR6pq8deXZyMsqZBAI0NY1sBC4QI5pf+T5i3AQyB7EhJRyDtSYeN/B74YWRTsGjyXZ4K+HqopGBtEzaDK3GtpABJOGXFDFqRzjRHkhnSnAmsduT4eHtuQVLYIGavpxwJQ1kvnkDeqo0ICuKWqwjXtlgiEflWWJh/V3AcDk8NHzd0NZwq4iQEQDAU0nLX/FzAMRIVgIxQGgI/PArMr6ak81G1VI9PftkTde/kUz8rIuTaXCYLK1O+KyX+0kSGwLRp6Q X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d5393b6-bc80-4b4e-b90c-08dbf1412d33 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:43.8387 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pF7veoymWuGvxp3HCnmKxo4u/Evh7vjWDzMhm1eLL0GoG6jimlV8Bbu2oexvxU3B X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4484 Similar to of_iommu_for_each_id() this parses the IORT ACPI description and invokes a function over each entry in the table. Have iort_iommu_configure_id() use the new function to call iort_iommu_xlate(). Signed-off-by: Jason Gunthorpe Acked-by: Rafael J. Wysocki --- drivers/acpi/arm64/iort.c | 118 ++++++++++++++++++++++++-------------- include/linux/acpi_iort.h | 12 ++++ 2 files changed, 86 insertions(+), 44 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index bdaf9256870d92..5c9b4c23f96a87 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1218,9 +1218,10 @@ static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED; } -static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, - u32 streamid) +static int iort_iommu_xlate(struct acpi_iort_node *node, u32 streamid, + void *info) { + struct device *dev = info; const struct iommu_ops *ops; struct fwnode_handle *iort_fwnode; @@ -1250,9 +1251,11 @@ static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, struct iort_pci_alias_info { struct device *dev; struct acpi_iort_node *node; + iort_for_each_fn fn; + void *info; }; -static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) +static int __for_each_pci_alias(struct pci_dev *pdev, u16 alias, void *data) { struct iort_pci_alias_info *info = data; struct acpi_iort_node *parent; @@ -1260,7 +1263,7 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) parent = iort_node_map_id(info->node, alias, &streamid, IORT_IOMMU_TYPE); - return iort_iommu_xlate(info->dev, parent, streamid); + return info->fn(parent, streamid, info->info); } static void iort_named_component_init(struct device *dev, @@ -1280,7 +1283,8 @@ static void iort_named_component_init(struct device *dev, dev_warn(dev, "Could not add device properties\n"); } -static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node) +static int __for_each_platform(struct acpi_iort_node *node, iort_for_each_fn fn, + void *info) { struct acpi_iort_node *parent; int err = -ENODEV, i = 0; @@ -1293,27 +1297,71 @@ static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node) i++); if (parent) - err = iort_iommu_xlate(dev, parent, streamid); + err = fn(parent, streamid, info); } while (parent && !err); return err; } -static int iort_nc_iommu_map_id(struct device *dev, - struct acpi_iort_node *node, - const u32 *in_id) +int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, + struct iort_params *params, iort_for_each_fn fn, + void *info) { - struct acpi_iort_node *parent; - u32 streamid; + struct acpi_iort_named_component *nc; + struct acpi_iort_node *node; + int err = -ENODEV; - parent = iort_node_map_id(node, *in_id, &streamid, IORT_IOMMU_TYPE); - if (parent) - return iort_iommu_xlate(dev, parent, streamid); + memset(params, 0, sizeof(*params)); + if (dev_is_pci(dev)) { + struct pci_bus *bus = to_pci_dev(dev)->bus; + struct iort_pci_alias_info pci_info = { .dev = dev, + .fn = fn, + .info = info }; - return -ENODEV; + node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, + iort_match_node_callback, &bus->dev); + if (!node) + return -ENODEV; + + pci_info.node = node; + err = pci_for_each_dma_alias(to_pci_dev(dev), + __for_each_pci_alias, &pci_info); + + if (iort_pci_rc_supports_ats(node)) + params->pci_rc_ats = true; + return 0; + } + + node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, + iort_match_node_callback, dev); + if (!node) + return -ENODEV; + + if (id_in) { + struct acpi_iort_node *parent; + u32 streamid; + + parent = iort_node_map_id(node, *id_in, &streamid, + IORT_IOMMU_TYPE); + if (!parent) + return -ENODEV; + err = fn(parent, streamid, info); + } else { + err = __for_each_platform(node, fn, info); + } + if (err) + return err; + + nc = (struct acpi_iort_named_component *)node->node_data; + params->pasid_num_bits = FIELD_GET(ACPI_IORT_NC_PASID_BITS, + nc->node_flags); + if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED) + params->dma_can_stall = true; + + iort_named_component_init(dev, node); + return 0; } - /** * iort_iommu_configure_id - Set-up IOMMU configuration for a device. * @@ -1324,40 +1372,22 @@ static int iort_nc_iommu_map_id(struct device *dev, */ int iort_iommu_configure_id(struct device *dev, const u32 *id_in) { - struct acpi_iort_node *node; - int err = -ENODEV; + struct iort_params params; + int err; - if (dev_is_pci(dev)) { + err = iort_iommu_for_each_id(dev, id_in, ¶ms, &iort_iommu_xlate, + dev); + if (err) + return err; + + if (params.pci_rc_ats) { struct iommu_fwspec *fwspec; - struct pci_bus *bus = to_pci_dev(dev)->bus; - struct iort_pci_alias_info info = { .dev = dev }; - - node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, - iort_match_node_callback, &bus->dev); - if (!node) - return -ENODEV; - - info.node = node; - err = pci_for_each_dma_alias(to_pci_dev(dev), - iort_pci_iommu_init, &info); fwspec = dev_iommu_fwspec_get(dev); - if (fwspec && iort_pci_rc_supports_ats(node)) + if (fwspec) fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; - } else { - node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, - iort_match_node_callback, dev); - if (!node) - return -ENODEV; - - err = id_in ? iort_nc_iommu_map_id(dev, node, id_in) : - iort_nc_iommu_map(dev, node); - - if (!err) - iort_named_component_init(dev, node); } - - return err; + return 0; } #else diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 1cb65592c95dd3..5423abff9b6b09 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -29,6 +29,18 @@ void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); +struct iort_params { + unsigned int pasid_num_bits; + bool dma_can_stall : 1; + bool pci_rc_ats : 1; +}; + +typedef int (*iort_for_each_fn)(struct acpi_iort_node *iommu, u32 streamid, + void *info); +int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, + struct iort_params *params, iort_for_each_fn fn, + void *info); + #ifdef CONFIG_ACPI_IORT u32 iort_msi_map_id(struct device *dev, u32 id); struct irq_domain *iort_get_device_domain(struct device *dev, u32 id, From patchwork Thu Nov 30 01:10:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748551 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XUtkMqgI" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B04F910DD; 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Thu, 30 Nov 2023 01:10:54 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:54 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 08/30] iommu/of: Add iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:15 -0400 Message-ID: <8-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR13CA0001.namprd13.prod.outlook.com (2603:10b6:806:130::6) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2af03d14-c665-4974-408c-08dbf1412c44 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /p7yVX5PvhbJhf+jSbA+Lp4ito6qpWC6FnoepOt4fRU5t47ibWxL7mKVhMdvVdnpoEZ4tvcCMBBuwCovgUZ0f6yy6UubmKuhDDnkNcRDIz8fBGQRIEBUoXGtJJt9xLQSux0Ibc28YJGlgt6xPc2xj/xfnJwO7jh2kozedCunqXH5SgULqr6ZiSMgsi8mmeXqJWa+sCWdCWjfa5FR+CPAgQ/S49LH1DSUD/dPBc3r1PbOtCJKjh7DDnpcTHXzPYibyp5OqSJzrrc4PhMdEpzHPL2PBwYMDSuSTtc0T1Kk/zzfBXBU3CL5SQpJJdqBDkwonZkDNbPQq46VIL1Hb0fH3XXWtggoNkuj18bsoy0djpaFs8/yt9DnDfMkw3Iwiwes/K0t76HydzDO1YD0aT6bG/2p+RmgS3SAvCieMkfwPq1JqO+851N8UfIj7wtrtfEoa3B1i62FZyyCL4PWPGHK+L3d78IaclUK6xpwnonmACW4K+ElAx6qcbe1VbI9aMkWGD3RJr1CteN/NLoyfmecgiHSbISPZJOtEgociMYJJrb9SVji974A6yLlEM6aRn4iK+FsCQu8XQv/mBOfDAoCk3o7LJ8qSBjL8SkpWwQfikkLSF/POblBw5gQJLTuaeY355WH64D54M9TbbnogTDG1YDY8sgaLvFfZh0GIpUKF5A= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QCwBEix9KdHo9LRLkFEksaEnE1WvxAmGv8Vwjg+oX8rpqxnYUNmOHHKN7ILgSBK8kxGJLoT7nh5SJUq1WgXeFsrNQT1O5Jpp2jYvOAwlmyhb2oRxaEc7JGZ/szraGxa4XFHHdvih4kGr3zs5C5jDKRVuFX2RF8/WWqWJJa78ofIqnItMakLoWDAqPs/8NfwCkTGv7UF0zbrntBJNzsYwxmTdl62V+SxDBx1pOQbhKDIougJp8nUMduriGDcKlpkwhZIZs3UlafUgJgrBgTMBIteOb2E2mvBww29l6oxaAmNOOYQ0a6o52wR/FzfoLzze9PgInnbEPYcoAcW0/TWsW2ffbMpbRGFx6NwbmgaRW8Q6Gthmt+JL1ofKxDTlh9J1ON8q30trpwA97USMPKki5HV0d5RAk0XQtKIFNUF5H/KUk3g2MqSG8wi2OSVX6j/uJshVgPdt1LwdClpa4RrleDD/BOs8vOakTS7lIcspopO8ONkBXwki2GDQ0tV9QJxwlUkzZaqh2NaCZwqxTLDK43U/5a++kEpSO8y9zS5bOST43bxMyNBeRYlgdTiQcF8R46BKub8AUK1rNFeckhYyvWqbOhVaiU3Nu9USjkoUI3TVKcYkEurbTqn7pcYhdsj3jVU14U9IJuxKreunOBx3ukKw4s2zhSUPA+ELJ+aBbtfxOX37Tcd1Of3pge3aYt/5c/2F68FPfxXpiv25Jj2eK3/0DMXqGNFpqDElV60E1dF/lV3HiGh9DN2d6xGMDlSmdBnAIMk9Zkd7bHLbnybYltUcgVQ2gkRba1W5TniN9lruGB17YGtgljrE1QJ7SQU5TNJBEe78GAKZ3rtba/p9BHmiYHK66UITBfkFPK2Wrsq17rBEB28lshRb08i9F7OYCkI5EQPjt2qcIZb0m04GFKFYdSx8bKXZ5kXsM7nNhNv1noCbKl5ivgpRS+ppHtN+9CwJpgGhXLg9QEra0iS46pEuG+VutDMPnBgpQU/3U/JcJnv+tAD+U2VmLGamJmu6u55vBR6D7TzdEmu984czixNe/9w8SkWIXEn2twIQTlNSk+dRi28hXN7HOmbxulLkx21utdxfu9F8Gwu3b1s7fQeeBwQCYoOZKptT4GvwrNwjoSE11adzSXvOTF1iemvUzjyNL0KKtGYjja9qLoSUZ1rn5ojrD756zQKFFlbJw2SwTSq6cpkM7PNro/zGhVxbhpyAG7D2sOxo2KQaOMsM9a8CrgjHV1OVaz6p45790y5QGmmNuklwPxOBUXWw0biQzI5P5oOPazXda+bUIRgNCXdLvIKhpTSpOJ34o2CfbhUQYmuBjumFN37hpLt9RkpZoej4+gGNoGZHuF/q25VFdET7/e/F0v58Wxx3PKs4QxHJGUup/bRznmrtiLNOh47htWo0k6cOUMxceiVXzEnhpZwOr56g7stforgZFK5kFWmqRs1Qk7EtHrBxOh36OMcQp1AVOPVa5jKmihDx3rE5+dS4MJnN73z18Y1eIXHb9cFaCT2CkMhRqdA+SqqQNeicHpK0dTrvNIs9eMbmufRDj1deL9qhHSE6eqxxeVijkHJ04Gme0Ap+b0rEgm7Ne1S3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2af03d14-c665-4974-408c-08dbf1412c44 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.2995 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NR5cfhMwLhdbnNuFdehhk6uCBjt3FpxSFXTHhABOZa+SD093yMXE4FbPKcL1P5sg X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This function can be called by drivers in their probe function to return a single iommu_device instance associated with the current probe. All drivers need a way to get the iommu_device instance the FW says the device should be using. Wrap the function with a macro that does the container_of(). The driver indicates what instances it accepts by passing in its ops. num_cells is provided to validate that the args are correctly sized. This function is all that is required by drivers that only support a single IOMMU instance and no IDs data. Driver's should follow a typical pattern in their probe_device: iommu = iommu_of_get_single_iommu(pinf, &rk_iommu_ops, -1, struct rk_iommu, iommu); if (IS_ERR(iommu)) return ERR_CAST(iommu); data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) return ERR_PTR(-ENOMEM); [..] dev_iommu_priv_set(dev, data); return &iommu->iommu; Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 1 + drivers/iommu/iommu.c | 52 ++++++++++++++++++++++ drivers/iommu/of_iommu.c | 59 +++++++++++++++++++++++++ include/linux/iommu-driver.h | 85 ++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9c13df632aa5e0..de36299c3b75bf 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1570,6 +1570,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) const struct iommu_ops *ops; struct iommu_probe_info pinf = { .dev = dev, + .is_dma_configure = true, }; /* Serialise to make dev->iommu stable under our potential fwspec */ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 45e6543748fd46..ca411ad14c1182 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3015,6 +3015,58 @@ struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode) return NULL; } +/* + * Helper for FW interfaces to parse the fwnode into an iommu_driver. This + * caches past search results to avoid re-searching the linked list and computes + * if the FW is describing a single or multi-instance ID list. + */ +struct iommu_device * +iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct fwnode_handle *fwnode) +{ + struct iommu_device *iommu = pinf->cached_iommu; + + if (!pinf->num_ids) + pinf->cached_single_iommu = true; + + if (!iommu || iommu->fwnode != fwnode) { + iommu = iommu_device_from_fwnode(fwnode); + if (!iommu) + return ERR_PTR( + driver_deferred_probe_check_state(pinf->dev)); + pinf->cached_iommu = iommu; + if (pinf->num_ids) + pinf->cached_single_iommu = false; + } + + /* NULL ops is used for the -EPROBE_DEFER check, match everything */ + if (ops && iommu->ops != ops) { + if (!pinf->num_ids) + return ERR_PTR(-ENODEV); + dev_err(pinf->dev, + FW_BUG + "One device in the FW has iommu's with different Linux drivers, expecting %ps FW wants %ps.", + ops, iommu->ops); + return ERR_PTR(-EINVAL); + } + return iommu; +} + +struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf) +{ + if (WARN_ON(!pinf->num_ids || !pinf->cached_iommu)) + return ERR_PTR(-EINVAL); + if (!pinf->cached_single_iommu) { + dev_err(pinf->dev, + FW_BUG + "The iommu driver %ps expects only one iommu instance, the FW has more.\n", + pinf->cached_iommu->ops); + return ERR_PTR(-EINVAL); + } + return pinf->cached_iommu; +} + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 20266a8edd5c71..37af32a6bc84e5 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -138,6 +138,9 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, { struct iommu_probe_info pinf = { .dev = dev, + .of_master_np = master_np, + .of_map_id = id, + .is_dma_configure = true, }; struct iommu_fwspec *fwspec; int err; @@ -277,3 +280,59 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) #endif } EXPORT_SYMBOL(of_iommu_get_resv_regions); + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + int num_cells; +}; + +static struct iommu_device *parse_iommu(struct parse_info *info, + struct of_phandle_args *iommu_spec) +{ + if (!of_device_is_available(iommu_spec->np)) + return ERR_PTR(-ENODEV); + + if (info->num_cells != -1 && iommu_spec->args_count != info->num_cells) { + dev_err(info->pinf->dev, + FW_BUG + "Driver %ps expects number of cells %u but DT has %u\n", + info->ops, info->num_cells, iommu_spec->args_count); + return ERR_PTR(-EINVAL); + } + return iommu_device_from_fwnode_pinf(info->pinf, info->ops, + &iommu_spec->np->fwnode); +} + +static int parse_single_iommu(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + struct iommu_device *iommu; + + iommu = parse_iommu(info, iommu_spec); + if (IS_ERR(iommu)) + return PTR_ERR(iommu); + info->pinf->num_ids++; + return 0; +} + +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells) +{ + struct parse_info info = { .pinf = pinf, + .ops = ops, + .num_cells = num_cells }; + int err; + + if (!pinf->is_dma_configure || !pinf->of_master_np) + return ERR_PTR(-ENODEV); + + iommu_fw_clear_cache(pinf); + err = of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index c572620d3069b4..597998a62b0dd6 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -13,25 +13,110 @@ #endif #include +#include +#include +struct of_phandle_args; struct fwnode_handle; +struct iommu_device; +struct iommu_ops; + +/* + * FIXME this is sort of like container_of_safe() that was removed, do we want + * to put it in the common header? + */ +#define container_of_err(ptr, type, member) \ + ({ \ + void *__mptr = (void *)(ptr); \ + \ + (offsetof(type, member) != 0 && IS_ERR(__mptr)) ? \ + (type *)ERR_CAST(__mptr) : \ + container_of(ptr, type, member); \ + }) struct iommu_probe_info { struct device *dev; struct list_head *deferred_group_list; + struct iommu_device *cached_iommu; + struct device_node *of_master_np; + const u32 *of_map_id; + unsigned int num_ids; bool defer_setup : 1; + bool is_dma_configure : 1; + bool cached_single_iommu : 1; }; +static inline void iommu_fw_clear_cache(struct iommu_probe_info *pinf) +{ + pinf->num_ids = 0; + pinf->cached_single_iommu = true; +} + int iommu_probe_device_pinf(struct iommu_probe_info *pinf); struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode); +struct iommu_device * +iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct fwnode_handle *fwnode); +struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); #if IS_ENABLED(CONFIG_OF_IOMMU) void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); + +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells); #else static inline void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) { } +static inline +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells) +{ + return ERR_PTR(-ENODEV); +} #endif +/** + * iommu_of_get_single_iommu - Return the driver's iommu instance + * @pinf: The iommu_probe_info + * @ops: The ops the iommu instance must have + * @num_cells: #iommu-cells value to enforce, -1 is no check + * @drv_struct: The driver struct containing the struct iommu_device + * @member: The name of the iommu_device member + * + * Parse the OF table describing the iommus and return a pointer to the driver's + * iommu_device struct that the OF table points to. Check that the OF table is + * well formed with a single iommu for all the entries and that the table refers + * to this iommu driver. Integrates a container_of() to simplify all users. + */ +#define iommu_of_get_single_iommu(pinf, ops, num_cells, drv_struct, member) \ + container_of_err(__iommu_of_get_single_iommu(pinf, ops, num_cells), \ + drv_struct, member) + +/** + * iommu_of_num_ids - Return the number of iommu associations the FW has + * @pinf: The iommu_probe_info + * + * For drivers using iommu_of_get_single_iommu() this will return the number + * of ids associated with the iommu instance. For other cases this will return + * the sum of all ids across all instances. Returns >= 1. + */ +static inline unsigned int iommu_of_num_ids(struct iommu_probe_info *pinf) +{ + return pinf->num_ids; +} + +/* + * Used temporarily to indicate drivers that have moved to the new probe method. + */ +static inline int iommu_dummy_of_xlate(struct device *dev, + struct of_phandle_args *args) +{ + return 0; +} + #endif From patchwork Thu Nov 30 01:10:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748559 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bt72uduo" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD75E10D7; Wed, 29 Nov 2023 17:10:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EHviIIoeYGnFvTiRuP4hmMzCpBC1erusmHD//dURo3osiQ0nIWcAKYj9QktHk8QAD2528PE6Iaxr0rh9kusTlu3cBF8VFa59X3Wj42yihuiNCwpWbW6W130YmiWjCyJeiEqFYehK4RJ7VPUoYTybGq54JsezFl2Uy3GwyvtkZNSyDdbiSKVDmzka53QMJ/HpXaephtgKiHH984q/H4snhUys/o20JceuJuzLb6ulbknWu48dUiTjtbWWTtclouSu9sIPcmTtfVrVaRJAh9S3xE2L55WiruJhYGLJ+kXULIQAecnXF1hUTVNa/jnPxJrYmZh+SG10g8DQBH5V5Ly68g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pH0gW84gOXxliY71EzUBCEAqil4815K+q+c+KD8Jig0=; b=grpc2QHgqMoqmavTtArDjqOThLx6m0b+fwvSpt11L5rBUQ8m1b8/GVNTbYKtmE6mPpFengzd+x5wQdW9h6kVe11lj602EQ4Ob8e8FqHJTRiv+XBttyFoCRC0hvs2D4eH944nijo6/aY6SAUHdPXGDsd7fRpoBZ82QKHsS4dDNdtvMMkAsOKe17dj+j1cCXYmpZh/njJxZqoWaPq6OycqUQMq4BVt99lCuwu0wgmCgEvwul8HxYE2GFiGYXJWrgJ8W9ct+C/U3XLWARtDPQdnj/OU9On9inFcXVWWT+QTKR+FK2sRHC1WdzX7+Jgm1F8L25R+XspdXz+hJQiP2ZzsZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pH0gW84gOXxliY71EzUBCEAqil4815K+q+c+KD8Jig0=; b=bt72uduozeMkhtIrVviUsicUctr6C6o5YJ0GvT3SQhYkQAZN+9Sz3IVs7fJ0MsiXt8wQ0+PGWpczdvbt92fHpO8F1JMaivnwyVFT5dGfxCHUNPPvL3tcQQjP4MIhuJvKKNLdPcxUtaHKUGbL4KJxSk1PKnBfD18lweBTSV2MSIzwmdLycn0lo9RagI5nHtZQB24eZzsnfYINr8I2YVMqhSnT8Ua36PUdIU7XZCtAnfcoikbWOSWPKEBNY2WC/dMR7nEqoXKOC1et/tsDB4zwGwSZ1kOdDIYf6LsGYruWtiwurhiyLOnKOBI+f4+XsgTlmErQrA/bnOnzpLkMYWLfaQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:47 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:47 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 09/30] iommu/rockchip: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:16 -0400 Message-ID: <9-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0043.namprd16.prod.outlook.com (2603:10b6:805:ca::20) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: fc7ed155-37f1-4855-5c7a-08dbf1412b4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: umO1ddYmJzHiPe/jglh3QVymxKzgOl3MVjcBhSWQDjWMRKWR8HZVwrI79C7ISCJr9SqH/28vyXDldPiqHoxK4wjKpDqIRfITgrO1HNCUqi+cqE3NfriRJMPlCMD737cdyI2IywQiD2HW2l3RV06Axv5ENsUPcDtd7WeW+PRLqh0p4Nyj9tMR5O+U/kK3lfsVhijwxxPkdyxR6FByxCIN6XssDr1ncHGfbXl+fvaiyBwVQGWCYvzBcJ4EH3og85kOP6+YebkGlapaQNdMEWDR5fUine7h0o57M8K+ZTYLHBJN3tSlX0S5qlvIfQXBmptAjdqq76AXo+if7d1cXg/Vi1F2AmIRlwvgNEO/Vbxi/byaz9tfWho0USuyrmtjec0a8Cu6tbCRAOm/cBZRAgUaIrzgkA/iCyy9NtHqunAVHrE0XsEXfhUj8OzKPrY6z85T6BYeJJFyAeXTuzAUR2fMPieYLQDs2kqEjay3aW0cV3rgNDDdapLoHCY6UnDIJV9EUyOHbKNPHChT2S/rUdFuR7b0aTjrXaghzPn4wGtyUS8i6fKHUiy6ZDX4BoT8zGcKvjierkteLZ9f8wpmxqG49KIf1byjgxkK8cQD7QtFttKijq/LkAW6mjLVdhWMGOCW/6Jh6gpuEmpOpDGc8pOav6AnI+iJvTCV6sNT467zjMs= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RvweIR4IeBPVT59G+mnbsZU6UEVqLrPN3J6FlzJYjO7J+iz1H9Ah/TTZnpLVbzzXdnsYfu73hOvVyIhyFFy2Y9iAVTmQOGBNtfiNqHatKLecwWkvRnGucJYl6ayVdDsEhu6c09vb6JX0jl/6ylYdM5BnKZHVZMExj+31UkSpqyN2FuU5uT2Xr90Ueo0jXA2Z03kTEU8ch32Daa+DHzVEBQgRavFpjPYfxw5GRN2DMKctlHfmDFTmqw1mRmxXrKmQxuow1xsXgnt6IVv2HLHLfEV6J5u1iWc3eX0RFwewgApDZKmbxceJxhnuc0WMwnkzRKtis8NmuvwPf0/iTYocY1FXnBQMmQZVDu1YYw0bgiWqcbhhxouju/phOCCPrif2M0x8xucKxsDN1fjHrSKbJIrsyfaPlYahaJAdhgdvt0N+bbbSCcud2mG3QNAxEyZZiJ4aL184Yk4Zd88dgS6DA6T9o2uGWdhQLG/bOKomviLNB5exuz9DaGsBlXCQs7430xqlvDvrGsZ1/mQ1zoqyunFnNfny8Kou2tXkB3/vYaQ4/qTYAVWVuWsF+QGKpktcPneGCR5n7RGeeB4xV1Yh1m4b9hz5c23dJhHEA5a7RqEWhMMm2GNBSKL+tczXWR7OJYloObO47zOY3IBp+qWaoIXXLAmE7e7yqh1h+lVJUgGWuF35ywfY+uhqb/44D8xTB/TnYBIE4yoeiq1AjP9XQzew3lYb47TrHhWG7a57SHpabRxwdHJzlLFsCp6qWdS7TTjMYgp3Mb5TiYlRclucUXccEh/OhDKbShwAgWkBcCO6R4OCxIwWsSdVhYtaUiBkwAoGZY1sb0fD0Bq9TpDj7oyB4j6Nkm1uCcdbtCaz9GNCAOGCKHmogx610igV0IfQfp8uknMZkaDo6EcP4BHPC0/jdpMfRNgvvgMwSyqAwJQj/v7JQXXQ1l19Fp8hOKI/hYJMhq0+B3t4WbpGYuKWyrOEtTzE7hNq1vUJeLfVejwY710Xd4mb2UZrmrZyL+e35o8YcnGMnCwakua1HE94aRpW0sTilCvXyoTZGMkFmJXMUvTF7YJ2nYBRnzgeGrgcmaKpbL3tqtPt1HtwwNPnOyR7e1sFaip6WXk84n9Ci5NiYzdpKxo5ycWSzfSmeVlfe7p+yaYLSWVmH5/0GKCH+Td3zX2OXiEc4yK0DBYRQNfPww5KCYBUfMPTn+jTaGAjyXunmxpKxKVL8qkexOOVeEIOrp9RhbO0qRfnjH2yuZaEL2Ex85uF1huZMYmdsAym1TA5/HArddMm8fheg5PcwfD23SIPODEvBaumCKG2tTTFWcCdcCZ6B/BVKf0yXNzelhSF1EUIPbM3a1VaRWG1jK9wY12IIqkypXGcsARUQ8cBzBvRpn3OnspuU7z4+nV0P7vklV94icGGoExM5hxz/RShanrOe5mUGc8dt1fPi/77DPNR8ksydGyBX/CSpVWg+KLHtR/u++VBpfPB95h/3vBI9iMbswdR4273IB0fw9RKasdHtw+MqMsJjdI0idrWTtSQIdXIqD5yz+7fuL9KptqecViBCNaE4iZQwJTPGd8D5aTKbWX3FPdzKxCVvKbl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc7ed155-37f1-4855-5c7a-08dbf1412b4e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.7378 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PVtzl/qCMXCu7rm7n3eTwSdj/9QrQ5oeVSrwEHZuO+Yjour4vrdh6fDtSjtcF5io X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 rockchip supports a single iommu instance and does not support multiple IDs. Move the per-device allocation from rk_iommu_of_xlate() and completely delete rk_iommu_of_xlate(). The iommu instance is obtained via iommu_of_get_single_iommu(). Don't use devm to manage the lifetime of the per-device data, this just results in memory leaking if there are probe error/retry paths. Use the normal lifecycle with alloc in probe_device and free in release_device. The comment about "virtual devices" seems out of date. With today's code the core will not call attach_device/detach_device unless dev->iommu is set and has an ops. This can only happen if probe_device was done. Remove the checks. Signed-off-by: Jason Gunthorpe --- drivers/iommu/rockchip-iommu.c | 74 +++++++++++----------------------- 1 file changed, 24 insertions(+), 50 deletions(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 2685861c0a1262..4cff06a2a24f74 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -123,6 +124,7 @@ struct rk_iommudata { static struct device *dma_dev; static const struct rk_iommu_ops *rk_ops; static struct iommu_domain rk_identity_domain; +static const struct iommu_ops rk_iommu_ops; static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, unsigned int count) @@ -896,13 +898,6 @@ static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, return unmap_size; } -static struct rk_iommu *rk_iommu_from_dev(struct device *dev) -{ - struct rk_iommudata *data = dev_iommu_priv_get(dev); - - return data ? data->iommu : NULL; -} - /* Must be called with iommu powered on and attached */ static void rk_iommu_disable(struct rk_iommu *iommu) { @@ -958,16 +953,12 @@ static int rk_iommu_enable(struct rk_iommu *iommu) static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct rk_iommu *iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); + struct rk_iommu *iommu = data->iommu; struct rk_iommu_domain *rk_domain; unsigned long flags; int ret; - /* Allow 'virtual devices' (eg drm) to detach from domain */ - iommu = rk_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; - rk_domain = to_rk_domain(iommu->domain); dev_dbg(dev, "Detaching from iommu domain\n"); @@ -1003,19 +994,12 @@ static struct iommu_domain rk_identity_domain = { static int rk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct rk_iommu *iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); + struct rk_iommu *iommu = data->iommu; struct rk_iommu_domain *rk_domain = to_rk_domain(domain); unsigned long flags; int ret; - /* - * Allow 'virtual devices' (e.g., drm) to attach to domain. - * Such a device does not belong to an iommu group. - */ - iommu = rk_iommu_from_dev(dev); - if (!iommu) - return 0; - dev_dbg(dev, "Attaching to iommu domain\n"); /* iommu already attached */ @@ -1115,20 +1099,30 @@ static void rk_iommu_domain_free(struct iommu_domain *domain) kfree(rk_domain); } -static struct iommu_device *rk_iommu_probe_device(struct device *dev) +static struct iommu_device *rk_iommu_probe_device(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; struct rk_iommudata *data; struct rk_iommu *iommu; - data = dev_iommu_priv_get(dev); - if (!data) - return ERR_PTR(-ENODEV); + iommu = iommu_of_get_single_iommu(pinf, &rk_iommu_ops, -1, + struct rk_iommu, iommu); + if (IS_ERR(iommu)) + return ERR_CAST(iommu); + if (iommu_of_num_ids(pinf) != 1) + return ERR_PTR(-EINVAL); - iommu = rk_iommu_from_dev(dev); + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return ERR_PTR(-ENOMEM); + data->iommu = iommu; + data->iommu->domain = &rk_identity_domain; data->link = device_link_add(dev, iommu->dev, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + dev_iommu_priv_set(dev, data); + return &iommu->iommu; } @@ -1137,37 +1131,17 @@ static void rk_iommu_release_device(struct device *dev) struct rk_iommudata *data = dev_iommu_priv_get(dev); device_link_del(data->link); -} - -static int rk_iommu_of_xlate(struct device *dev, - struct of_phandle_args *args) -{ - struct platform_device *iommu_dev; - struct rk_iommudata *data; - - data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - iommu_dev = of_find_device_by_node(args->np); - - data->iommu = platform_get_drvdata(iommu_dev); - data->iommu->domain = &rk_identity_domain; - dev_iommu_priv_set(dev, data); - - platform_device_put(iommu_dev); - - return 0; + kfree(data); } static const struct iommu_ops rk_iommu_ops = { .identity_domain = &rk_identity_domain, .domain_alloc_paging = rk_iommu_domain_alloc_paging, - .probe_device = rk_iommu_probe_device, + .probe_device_pinf = rk_iommu_probe_device, .release_device = rk_iommu_release_device, .device_group = generic_single_device_group, .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, - .of_xlate = rk_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = rk_iommu_attach_device, .map_pages = rk_iommu_map, From patchwork Thu Nov 30 01:10:17 2023 Content-Type: text/plain; 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R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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Parse it directly using iommu_of_get_single_iommu() and remove sprd_iommu_of_xlate(). It stores the iommu, not a per-driver struct in the dev_iommu_priv(), keep it that way for now. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sprd-iommu.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index 537359f109979b..f1b87f8661e199 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -383,32 +384,27 @@ static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain, return pa; } -static struct iommu_device *sprd_iommu_probe_device(struct device *dev) +static struct iommu_device *sprd_iommu_probe_device(struct iommu_probe_info *pinf) { - struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); + struct sprd_iommu_device *sdev; + + sdev = iommu_of_get_single_iommu(pinf, &sprd_iommu_ops, -1, + struct sprd_iommu_device, iommu); + if (IS_ERR(sdev)) + return ERR_CAST(sdev); + if (iommu_of_num_ids(pinf) != 1) + return ERR_PTR(-EINVAL); + + dev_iommu_priv_set(pinf->dev, sdev); return &sdev->iommu; } -static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct platform_device *pdev; - - if (!dev_iommu_priv_get(dev)) { - pdev = of_find_device_by_node(args->np); - dev_iommu_priv_set(dev, platform_get_drvdata(pdev)); - platform_device_put(pdev); - } - - return 0; -} - - static const struct iommu_ops sprd_iommu_ops = { .domain_alloc_paging = sprd_iommu_domain_alloc_paging, - .probe_device = sprd_iommu_probe_device, + .probe_device_pinf = sprd_iommu_probe_device, .device_group = generic_single_device_group, - .of_xlate = sprd_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Thu Nov 30 01:10:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748553 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:53 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:53 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 11/30] iommu/sun50i: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:18 -0400 Message-ID: <11-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0012.namprd08.prod.outlook.com (2603:10b6:805:66::25) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 202f467c-ccd0-4067-7ecf-08dbf1412c4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wDaTT+ItBQkwfzcOkVg2Mm6eY2SM6MzCUmBpSQHf6eTxjKudDQ3FJrLtC7843i5IRrcwn8Wp3kyfu6/Yh11FUDQgsLe09RbqFC9c2+iHarhPjCgkaI2RwUCtNnHyx1f2GX4soqsXrPW3tZjeHuhABq1xMhcgDnPvrLZmLnuXL2YUzE6qEmHYTRhSCwDecEzEQqk3k0mZwtI9954N7vcDEfs3+s9793mSLR4FCD88WcYY3N9tSP7mTocrA7xWY9eF6jrtozd+HQst/hJospZz6+END6XGVPatK4VBOXB+imY7adaFenJ0MD1QGaumMJitErYRDwzrgCZmy418ZXqH30+cb/9zNzH/WcPrjxVK6W3kB0g6I70noY3NnRRyoT+NB7EWk3sYMVTq8fa6KlOPD9Pdxw/aOkJBCKwhLrM7al2n1j/5h3LbnyhJv+auY8lm0VOMlHMs97bHEXNDGBCVdGQcdHjui/H76ko5oarfbYDoF1fWy3AMooL7COYFS0X0YRtuzPAU+5RhjGp++wmJmXcNTrW38ZWCR1NwdSydhfmm8OyAUTknpAzEaWoLPV75JG8gvtcRUxLH8XQmiu9vkE7ux9a9ykBt+G4RepwDKzVS2XNyaYMOAz4Zl7eop97FzmS+T70+iRR9y9s9Oo4HCw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wWcuxQ+bqZ5gr7soEwznyBgBycyNZqXKcFDlwc7STj6auYzuzroGafPTSpivIwLxcXuyAoaQVLZ6IfPMCSvSqVvc+2/M0h6wJLXdgA9MQBYFSH+z/3Evzra7w2Aqf3rzO82n4GtdJo5pb0Eq1lCLtr/+m0yPelra2eVek7ZBOxGFOrDvAsLk89czFKtigbQw3ogWsAgRjTlhJsLudryGaq97tLfKg+GvnVP3aqsxJvMJGR1Ti7Ky2fr+8RoRNWeDguYNt7XHSrsnCzy4oGVUHJFPsaa4rmt51GZ6/BLrhv5o+0/B37CBhFKeLNT6Y72w8hkl7sMZ1Qf+lpZOW0dSNxXnS/Fd7nLg0wfFe6BgFjUfo8grRg2Vik/WiqLn6mQnvMvWvkFac0l9Vww722EeE/Nm1W4+q/OEurTFfwrw2qldfQL5up6pTVSGf1tH+6Ppx1DFeXBd93LkHUb6bCddqBslvFnev1DhIc+t6rSPBiiM0wo8cXd+4mVrV582BsXOfvXucezKbMBNAc6qMH+SmEioDZSPJbCRJTkiA1lb3hfhH6Lq/Zivt2j8DugFo7YyFOXu8/JZDd2sgUonx0LqVPmIhxq6sC43aMFfoDNB4sB0VYfHE6ZcuEWDEszyrahpHYVlcSAPvL5VNHi1In/X9EiFfaDGEGgVSo7++9gG0iuPro3R566N3C8ftrSJtrOmpbzTmRxeNfzAB5rnhxyfwxaYxvAkFL1ST4d1+4FjfYWJEDiDNGRQ/AkgiRb5e93aPtRQ6eWAtFsl9mTmtbcvc0WR2WJ95frA0979Zjmch18U7McnZ+4CthhaHY8uHBWuwq2/q2T/CtdfxFtbjx/7zD6eAMoUQ0E+1klw9aFI4pTv8bsev37W24cWlQAD5ntr9IxlfEGWWe3Es1c1zpCWeMjmAKi/3Yz2dEk9DGKyjfuzzYdO/bIY8RcmvzfylpnHKVsIqdSm863AKsFlR7UC93lbZsHYDepY3BZFmFVhYwdxDGp28dfW9luiELXOa+j0ZyaMK3J/9/14i3VaH6sULWA1dZoqy0YJBAMgOpcKD9GZ63TzlLG1Z9s36cUvswWBuYOrUEtfaN69cnXinClrdVVr1nK13HJSIgpP1OkiIpGPr7PZo+FaxwU0wDIVJtl9slL8E1pDe3fnelSGlGSfuA8fvLNbnl5trv+hgofCTicScRguIIQvEV0XS/gCsnKj944zUANMLSugalmGuGAuLHTE5kCWQPI4BHaiShXbAemH+QBVCNNWaFI+5YotCOVM3721IVlPIQWd25ANil9kSiX7IyXalWLP6O88+YoTgbG6+mrUS0oQFffU+R9YXI62lfgmd9Uk1HzljQm4tn6nCCc/FmROrOo/Ueqz6Im6pDAO7mPOQKT4ToaPakFOfgJEUVTe0n1CBZSHwzug5Qjmkc5dTRG+W5TrWQA/oa7bn6YYSV/Wr9iJSWVmGVVPAng+YHBcOpQJ4MYNTHNeBh6vumTi0y6mdUtAD9KPgo3I0eBCtQpAwBP8EdehOjkdPFIOMX39FvxKwZjRaIKs9+alpM5iW5h9pqHqgw2wb2g7IPGhxJ5hW1GLk/3ZOdArN+Vp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 202f467c-ccd0-4067-7ecf-08dbf1412c4e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.2642 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iBIHLWUjNcLd7jknHW9Ss0txa1WTmqIItJzPMglQflJMXkc9yvM+62hk/Nml2vr3 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 sun50i uses a simple binding where a the OF iommus's can describe a single iommu instrance with a single ID, reflecting the master, on it. The driver ignores the ID from the OF, it looks like the instance can only do a single translation as the entire thing is managed with generic_single_device_group(). Since there is a single translation the ID presumably doesn't matter. Allocate a sun50i_iommu_device struct during probe to be like all the other drivers. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sun50i-iommu.c | 60 +++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 41484a5a399bb1..84038705cf657d 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,8 @@ #define SPAGE_SIZE 4096 +static const struct iommu_ops sun50i_iommu_ops; + struct sun50i_iommu { struct iommu_device iommu; @@ -110,6 +113,10 @@ struct sun50i_iommu { struct kmem_cache *pt_pool; }; +struct sun50i_iommu_device { + struct sun50i_iommu *iommu; +}; + struct sun50i_iommu_domain { struct iommu_domain domain; @@ -128,11 +135,6 @@ static struct sun50i_iommu_domain *to_sun50i_domain(struct iommu_domain *domain) return container_of(domain, struct sun50i_iommu_domain, domain); } -static struct sun50i_iommu *sun50i_iommu_from_dev(struct device *dev) -{ - return dev_iommu_priv_get(dev); -} - static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) { return readl(iommu->base + offset); @@ -760,7 +762,8 @@ static void sun50i_iommu_detach_domain(struct sun50i_iommu *iommu, static int sun50i_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct sun50i_iommu *iommu = dev_iommu_priv_get(dev); + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); + struct sun50i_iommu *iommu = sdev->iommu; struct sun50i_iommu_domain *sun50i_domain; dev_dbg(dev, "Detaching from IOMMU domain\n"); @@ -786,12 +789,9 @@ static struct iommu_domain sun50i_iommu_identity_domain = { static int sun50i_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain); - struct sun50i_iommu *iommu; - - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; + struct sun50i_iommu *iommu = sdev->iommu; dev_dbg(dev, "Attaching to IOMMU domain\n"); @@ -807,26 +807,37 @@ static int sun50i_iommu_attach_device(struct iommu_domain *domain, return 0; } -static struct iommu_device *sun50i_iommu_probe_device(struct device *dev) +static struct iommu_device * +sun50i_iommu_probe_device(struct iommu_probe_info *pinf) { + struct sun50i_iommu_device *sdev; struct sun50i_iommu *iommu; - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return ERR_PTR(-ENODEV); + iommu = iommu_of_get_single_iommu(pinf, &sun50i_iommu_ops, 1, + struct sun50i_iommu, iommu); + if (IS_ERR(iommu)) + return ERR_CAST(iommu); + /* + * The ids are ignored because the all the devices are placed in a + * single group and the core code will enforce the same translation for + * all ids. + */ + + sdev = kzalloc(sizeof(*sdev), GFP_KERNEL); + if (!sdev) + return ERR_PTR(-ENOMEM); + sdev->iommu = iommu; + + dev_iommu_priv_set(pinf->dev, sdev); return &iommu->iommu; } -static int sun50i_iommu_of_xlate(struct device *dev, - struct of_phandle_args *args) +static void sun50i_iommu_release_device(struct device *dev) { - struct platform_device *iommu_pdev = of_find_device_by_node(args->np); - unsigned id = args->args[0]; + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); - dev_iommu_priv_set(dev, platform_get_drvdata(iommu_pdev)); - - return iommu_fwspec_add_ids(dev, &id, 1); + kfree(sdev); } static const struct iommu_ops sun50i_iommu_ops = { @@ -834,8 +845,9 @@ static const struct iommu_ops sun50i_iommu_ops = { .pgsize_bitmap = SZ_4K, .device_group = generic_single_device_group, .domain_alloc_paging = sun50i_iommu_domain_alloc_paging, - .of_xlate = sun50i_iommu_of_xlate, - .probe_device = sun50i_iommu_probe_device, + .of_xlate = iommu_dummy_of_xlate, + .probe_device_pinf = sun50i_iommu_probe_device, + .release_device = sun50i_iommu_release_device, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = sun50i_iommu_attach_device, .flush_iotlb_all = sun50i_iommu_flush_iotlb_all, From patchwork Thu Nov 30 01:10:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748557 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:47 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:47 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 12/30] iommu/of: Add iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:19 -0400 Message-ID: <12-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0006.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::19) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f806ee4-4326-45e2-79e6-08dbf1412b63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TIZFqfzvtr2YcYNETFF/PTb94RNIUhTKxEEbcXysqAEzMAQoDXWV8aJFOi75zFaI0Il5TP4NPzByEX5F4XAhxGeE4tISihfjAz+eiHGxeNjT5XRrLukZy5iM2DLqlBNBSsBLqaXUUoO+tKjMsDsTVHkav75R34Yu1u5OQnfWYlp65PLg4mvIH4VJTfqV2FSsvPoEj1TASVrSAOkWsi1BMTHSMvlpSMReWwo5cDJoyzm6GcwrCmzB+zdkAxAP9htTkvIfi2vwU6Zw3jTV1A8/81ee52LNiTs6vtGNG0uuAJW7DGu+c+rmLV8pfxCiYjOL4p7wWpCN4wqDPYny4RUkKhxPRGhx1kGJnnQsViyHw6NxLspRbntoCnW7xEImAmedCqwHbZMngmgII4hR7G319RNBMiGxoCIv0BVsr19KkObtLnQOStGLEsSYVLRNU8qATn3Zn6wBiYaAnr1DIk47DQIdGs3l1h36pYGLA6RHiwM+6mm+G+ZB3SN7nOAy6P6KOHYrQlt3ptvtb5bN4dg+NZ2EOOf802I9EEbRwRjgYIeE8QTE/QcykFH/p+EkZez9d1lrBHCKQKAE9dtlxUPjBQ4trFIjKwjAT5H3dNvQJazHUc8/+NQhK2vYHdRsJXH20357ODwmeYDRCPFUicWPNw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HkGVBSCT9IGS1U/algNjEDu00nCBkERPgTh2ZudgjMK8/qB6HPEgafNREsBlG/4vTMnQ2uEbm33HKDHnsBzo2gHoqRyCyTKwrTiy7KuuEvxyJ9fnW5NrYqgGMVMTzIgR/TbZ5Es1Yp6KrUHGYmDTdfcfOzmMLiatRNaprFWGMXwruJWUhsDc97Fkdk/NgN+nl2HdEXVqrWJ7um1bn0sTa4MtAsTlcXTJI6XX3ZtJtW44YsPtA8paIVNJOp62CnVpeCufgbEx0Z9qfvLOMHWVnCcza5gMdxA0Yz9/adQkhU36+6wZR13bY+97HyPMaKhQLytgld10nHj3k+ToGH+n3c5CJ+VNlK3Qs+YcNJzFwGPa1wJrA9FFg/o3M2pTJSXpE+GiLVJNLSbd89RZBYFOsRESPH62svGVBTeLaupliGjznLkHf7hCR2FYm0W6RgoIi522IzjJuayYKq/leLq28CN8+L1lTyujvAiMDbuVg+7UxXH63FmuX2jFoN+U92G+W3Mgs2TrpMROhIllFkRqKeJjCH21+KAbZREINMDlNME3LO0W8ITTDcqT30lHRvb+bJFEts0y7y2knmVBJEZf5WAxoganc61AncBesmxvrOm/ByG2ZCzZYzE8tmZCS3A2qsvf4CcaYoEKGF3HWZghnjeJJwJT2VbfUAA+Z/gRu4wsekJZ8Pd2eUEQDiXHJhXnANp6hK4Tl4uJXui9fH/sNS7lUVNs55ukLC2lioLTNlRH0RFKT9wH8i4iMhqzpnMnaZ6KhSXh5LmPW+yOeTiSvUWZ8wH6ISJOvv5k3rforInSAFHs/k7YjTaCGn5Iu0dwvk1dfFw7cREWbdkx3iict5BWt0zfdnn7KQv4msGTSPKLouj4YtkS1TA5CoT4vUwOf1gWvPZlwVkIXjMDxYakxxsjrNf5RPkZkDRXeQOtZmqruseceH+xS02Pc3xFboBjciTW4G78EYMdHz2YgveI5cN5qlMuvNHg6u5H9CP8AWVr5YhHiaLYCG5qR6mV0Pns850dXm/wl5MDaV6qQgatKQTo7bD5lwyY7V4znNnAMEvCyuILT9BGlZcgOF42a4nKeftmaiElEK+wTWoLzNbSWj89X6yA35n6UoKqNNtUf4qCGvUFzgaJU2owZNycMrYws4k8aQ/zV38tu/+3ue9ZTI9GexHRYdJln3hxM0/J/PWFjji6BuTfDaM72ZTovBPeNJa7RgXZgru217vUnpUSQarBCG2TKMdesqeQlgOB2bPFVu9iHOnUeLtEIugulnONacvWYvPmtf5xlzUqf8yCeeEIGrax8xM28YXBgn3hMhVIl5P10WFM3bBIMMb0oKcG4KxdSuTLrlnGeD/T/IDYfvGxuNk8rxuXuiylpRcvv0t/NQ//gbJurtiIBVoSzEYKDaigCwVWNgy5zA8286mdTkYk5BqGaZ2USznxpIhd/eVfUF3CAxzkYWbzScdVtZvSr9XfPLPEE05aN03mDvoz+tH4A6CLxKRgiFLWzTsJi2eegK2zXIx0x2tKWQT33djZzavCGPecHCoN0ZznnjQ1Yj2uutamU7fneNgVD2rWJbpV5NxW+XyYVflFPKa529Hn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f806ee4-4326-45e2-79e6-08dbf1412b63 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.7736 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wqSzRYknoJdjHiGX0z3ucmQf7nPG+CbmvO67yHZIMSADsmvKJUkHoPYZETTpR9Ko X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This function can be called by drivers in their probe function if they want to parse their own ID table, almost always because the driver supports a multi-instance configuration and needs to extract the list of iommu_driver's and data from the ID into some internal format. The core code will find the iommu_driver for each ID table entry and validate that it matches the driver's ops. A driver provided function is called to handle the (iommu_driver, ID) tuple. Before calling this function the driver should allocate its per-driver private data and pass it through the opaque cookie priv argument. Driver's should follow a typical pattern in their probe_device: static int apple_dart_of_xlate(struct iommu_device *iommu, struct of_phandle_args *args, void *priv); [..] cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); if (!cfg) return ERR_PTR(-ENOMEM); ret = iommu_of_xlate(pinf, &apple_dart_iommu_ops, 1, &apple_dart_of_xlate, cfg); if (ret) goto err_free; dev_iommu_priv_set(dev, cfg); return &??->iommu; // The first iommu_device parsed Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 58 ++++++++++++++++++++++++++++++++++++ include/linux/iommu-driver.h | 13 ++++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 37af32a6bc84e5..9c1d398aa2cd9c 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -285,6 +285,8 @@ struct parse_info { struct iommu_probe_info *pinf; const struct iommu_ops *ops; int num_cells; + iommu_of_xlate_fn xlate_fn; + void *priv; }; static struct iommu_device *parse_iommu(struct parse_info *info, @@ -336,3 +338,59 @@ struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, return iommu_fw_finish_get_single(pinf); } EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); + +static int parse_of_xlate(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + struct iommu_device *iommu; + + iommu = parse_iommu(info, iommu_spec); + if (IS_ERR(iommu)) + return PTR_ERR(iommu); + info->pinf->num_ids++; + return info->xlate_fn(iommu, iommu_spec, info->priv); +} + +/** + * iommu_of_xlate - Parse all OF ids for an IOMMU + * @pinf: The iommu_probe_info + * @ops: The ops the iommu instance must have + * @num_cells: #iommu-cells value to enforce, -1 is no check + * @fn: Call for each Instance and ID + * @priv: Opaque cookie for fn + * + * Drivers that support multiple iommu instances must call this function to + * parse each instance from the OF table. fn will be called with the driver's + * iommu_driver instance and the raw of_phandle_args that contains the ID. + * + * Drivers that need to parse a complex ID format should also use this function. + */ +int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, + int num_cells, iommu_of_xlate_fn fn, void *priv) +{ + struct parse_info info = { .pinf = pinf, + .ops = ops, + .num_cells = num_cells, + .xlate_fn = fn, + .priv = priv }; + + pinf->num_ids = 0; + return of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_of_xlate, &info); +} +EXPORT_SYMBOL_GPL(iommu_of_xlate); + +/* + * Temporary approach to allow drivers to opt into the bus probe. It configures + * the iommu_probe_info to probe the dev->of_node. This is a bit hacky because + * it mutates the iommu_probe_info and thus assumes there is only one op in the + * system. Remove when we call probe from the bus always anyhow. + */ +void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf) +{ + if (pinf->is_dma_configure) + return; + pinf->of_master_np = pinf->dev->of_node; + pinf->is_dma_configure = true; +} +EXPORT_SYMBOL_GPL(iommu_of_allow_bus_probe); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 597998a62b0dd6..622d6ad9056ce0 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -60,9 +60,16 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, struct fwnode_handle *fwnode); struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); +typedef int (*iommu_of_xlate_fn)(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); +void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf); + #if IS_ENABLED(CONFIG_OF_IOMMU) void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, + int num_cells, iommu_of_xlate_fn fn, void *priv); + struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, int num_cells); @@ -71,6 +78,12 @@ static inline void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) { } +static inline int iommu_of_xlate(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, int num_cells, + iommu_of_xlate_fn fn, void *priv) +{ + return -ENODEV; +} static inline struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, From patchwork Thu Nov 30 01:10:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748565 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ChwDYoAE" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C0C8122; Wed, 29 Nov 2023 17:10:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ny8U4BXRGrjsTjqBDBev9XGufVXNkkea80vTxOxuuAskL2MghKThfFf2Aylc3OJ0K0o0eKKyWJTe++DWtyA0oMauMb27O6fXZpAX1ToeEsv88hkVDDbT0xU/rjvcDiQ1Xsj84hSrUnlrSUAip8IiYRXSLcIAWe04l1FwSJG3Vz82cneGUL4DwlRJoa7JIjHdwvrqAdrMGbdUildZAcH9aBWuoEDg45UKTpd3VZH1cOzH1Kd0fau+SxxskPO2bPsangqmdfBVdID/aDYT8akKT/RwnNJwzuxw2z4i9VCitDsQr8NFPKp9nZbHnR8ym4xFeYcbmqyXHxx7VbxJuZUpkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aSoBvw6bu/xIaykTkLxhOIj0UNzTY38fiGKG2fa6Hhc=; b=g8NWH1EKqXATOdoLLEsykmZ/aR+i6jj5yPbcd731zAy2K5RaeGm580LMhImyW3Y+izpdgDXM2foFwi/obQ8/CRBX5brySchiOt/Uzf70di5XHmvknTfm1h/4V1bge8TF+VUZeMoEviyeqXV1ElcgmLPITjX7yWy4zBPdNipMRn+1NzvSKwTbfyQpQcdkL1YVlK/x7lpthPHs40t5QpMX5wQLTE6Kq+L101nZQap6+1AnvGq+m+A8Av6gM+0xt1jXxgkBSfEiGnk3rUWmDMhPXaUKbp+9T/b1egF6tTaQgPJ5EUnZN3aRm4yX9H9ZTh/VQ1wGCPgqz00QA8D/glvKlQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aSoBvw6bu/xIaykTkLxhOIj0UNzTY38fiGKG2fa6Hhc=; b=ChwDYoAEExL5k8t7Bdhf33CtKVr5qwJwDio8HL3c0XNprZEp3Q1yQ+qcM+SMXYLQKR4kOFYjUglbOzDEAxJ1c9OkD6F3OdmD7Y49Fe0iXj803VoqMW+YOMCUinXXqZpadxtfnpg4gvW55ySDuE+bZGf4fMRdWQpf9UGoYeN3UX4km8gKm5A03QYql85TT3fJxaGgcjBpF6tl2vREqbFlNYemgi+ZulQ9nV6oJ23pDL7Lz9y31FLiax58ANYpLQuPkCgTkbgcxQ60i24zg+J2VngqUflaC5p5EBo7g82gK4hKSpJl+D65J9J/RRZjPeGnDaOjMIQNhzUhw3W5WxX6Jg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:38 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:38 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 14/30] iommu/exynos: Move to iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:21 -0400 Message-ID: <14-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0010.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::33) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f9142ec-ed01-441c-9964-08dbf1412a25 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5/KQURr1SqdpVFCpIzQqkc3bWuhgfsoIg3eAY1j6KzGuEap6fFGi5AGHmNU7LaTrc8ikZlfTNDO4/6tkiP6kz0dA48rXEop51rHHDvEbvmaqVbDRzZBC+xX1vbVvlIFq9DGCFH2R3K9y9c2JeEFMxfKmeQUJ4RR0Dqb7haCjKshrSCpfYndyflzAjegs5lOZgpsT6rc0pz2+MrBo5B8H+YCQGI/W5cqmwhk9EsCavV1+RsNQj/wgb9DBKF4A8p2p89Wk1Yzh94hrGo8P5LfjVHuVlRwfNn/8Gyz6QecoSIXNpqvIzjnXQzw97mTLQfX86ahtoA8vmuy3T8aKX8Mp28Mo+j7Ibr9ZTbW1KPLiBvvivimiwcYUi5/uKnE78TJUfb+Dqwd0hckN+MHj2aeu0U8KKWXX1AF3zW92Zf53wGbTz0a7Nld6HE6SEorY5LP27EalIVRXZFc0ndOV/iMOWYILYDvqS6KVwGqMJr+v6gvoUqrbVxmFyZf/zbfz5bqT+G+5afwbD/vbt8A/enjn+tcA8t8bEGrF55nzKC77HIlB0WTbcqzMOW8za4Rpmf+5hPQNYcS7475CpPcRuZyqKCLKq9MkW1+h8AZ5LjLmtDmSWbyzncGOXyMisufSdO8FzJBcGFLaixh6AjLKCbwqCA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +ZWXqKIWHWInPTY+5qeAm9OIgYb0NNVUk/pxR1RhzdMYjOc0c7+IJF9kBckDcs+mO2DyRJaW4eGlY5tZhutxPasw0s+uhytnC9rxCV+IkM1HYawCjObohj8xX6o+rgFCHVKv5n2oTvmcQ18En4+5r4Fg1QV9HAG2topLuHjPob9Bb3ZmAaEbHLNEBdAshrm+/PFw5NFD8GkONmu/AwcgSpfEFw4kTZ7W4Ib6Vmq17RzJKuP9Tsq+lyr9HN5AODI9cIiYK6R+xXDbEWKVLp6/Nim/Ckn7sR45c6Kvelqm77Y3prexvCak7S7CfTalkcmXPuBzt0VpKVb10MFQP6VG63Rw8VFa9uJLKfEvq+dmfsmQ1PVHCp7oQjuSH2j4yBGguPNqBCULOnQc+fRwU4PJpVWFwdc6B28DB6Irg1PfcLF4AEDguqs5Nhl8KIXzcBGwoBWjvPoB6C3cK7S6jIs6/UAv9mZ5U+AU1AVm8CXPRp6FT4n/Coj2wGczYsm3EYFB4EtJ/1ZO3AXdaPqApw4q0Bg/zj6RKXk5D2H0YjHPpGLwGl4Z2auJY4BUYc6ty191f0pwsNsyNb85ayIBLnmaNbRJbmAsX/YN8iwKvNthe7/xBcg/WRHfl+uEdBYgsw2gfeVme+Wo4VslXX4R1sAwvUjCkz1XYAgjhMF3xSPGnnAyyKFCYcMaxN1vsAL6LBky1odhviPk6czL306lVwh0PczHsji3RUbOY9sHY9HplpQnerkbSQfh4cDi6BC269XpTyRM/eGnxjJxjsQdTxYAfiYVn2BPHgBKCT/w52Dh+ZPqsMOAP15snJpE9/tglUGNPJ9rWQ1w3HDdiKC/nNrFFFy1mCXG7i36+otWFqDIxuqgaaH2wqkhY8PhFIEDdncebRRasM2M1Ytu7jRd6T+QoGT8Oz76/0erqbepdr1wb3Vd6FIWanaFh/plBjgo5ApD8tqQz069aKje7zNpB26Q3Loqietcd5jhv0tPrVFQKMHrYPEFXePWkam1UuGjPxQNUce6Qw3rdntQfHO9D6aJ6UoJ0oDGRUCazUk5ssSULgaQnMcxMNa9blEP7h5En91z+h9BqD6PAHgTaDzWbEI4EKFfpzQ7wpMs4+gXRQNP5mU/UejntI8aC69vcgGAe1bJW+1X4TPm+gTUv8e1wdQwtwpRFEVb/5o5xwkYDCXejI5KFz8wkxXdOS5XwhwBboBaQFKgJboIxCRDzzFba0I+xUSL5luxVpQKKXWu0Wk0f0cK8ezxJMBSVNUMXYqOr5/LmBuo7jGEYVjYpbl3291YSTa1Qbjmq5VltJBc7RnZ2vo/lS85YdXJ17tATnL4woIdI/4eXouROA2dRA1KC0qx0dKR3WQfcGJWU3q7A1TFi+7NJ/ruq2bcUO0TsyBo/VLPqY7pj7mvo5IpnZdg/MEznO/zAL5wjwBMvS0Ik0LB7C/ivAcsM2t0DDIJBhSxD75kdDCgtsSZcBFWZxUIQzRz4glq1loAFxRk/Q+I27GJZW0CBp8GUOPnKBdKvyI+17nOpM/D8RfEo+/XjqfyI8US7WblD+/iAwQ2KHPi9thiZZHWAZeMO/tYA5NTJt/QQV5p X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6f9142ec-ed01-441c-9964-08dbf1412a25 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:38.7896 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Deblvtu+OhvbUyusQHTkQo0j4X2I8nR8y/aO6w+mQBX6yk8ZVJSGI5i6Bge1KT4A X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 exynos allocates a per-device struct in the of_xlate() that can point to multiple instances of the iommu. It looks like each iommu instance can point to only one device however. Move the allocation of the per-device struct to the top of probe and use iommu_of_xlate() to fill in the linked list. Rely on the core code to locate the iommu. Solve a few issues: - A bus probe was failing by accident because the of_xlate not being called left a NULL owner in the priv, and other code tended to free the dev->iommu. iommu_of_xlate() will fail bus probe directly - Missing validation that the node in the iommus instance is actually pointing at this driver - Don't leak the owner. It is allocated during probe, freed on probe failure, and freed in release_device() on probe success. Previously it would allocate it in of_xlate and leak it in some possible error flows. Signed-off-by: Jason Gunthorpe --- drivers/iommu/exynos-iommu.c | 79 +++++++++++++++++------------------- 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 2c6e9094f1e979..c301aa87fe0ff0 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ typedef u32 sysmmu_iova_t; typedef u32 sysmmu_pte_t; static struct iommu_domain exynos_identity_domain; +static int exynos_iommu_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); + /* We do not consider super section mapping (16MB) */ #define SECT_ORDER 20 #define LPAGE_ORDER 16 @@ -168,8 +172,6 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V7_CAPA1 0x874 #define REG_V7_CTRL_VM 0x8000 -#define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) - static struct device *dma_dev; static struct kmem_cache *lv2table_kmem_cache; static sysmmu_pte_t *zero_lv2_table; @@ -779,8 +781,6 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) if (ret) return ret; - platform_set_drvdata(pdev, data); - if (PG_ENT_SHIFT < 0) { if (MMU_MAJ_VER(data->version) < 5) { PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; @@ -1393,15 +1393,29 @@ static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, return phys; } -static struct iommu_device *exynos_iommu_probe_device(struct device *dev) +static struct iommu_device * +exynos_iommu_probe_device(struct iommu_probe_info *pinf) { - struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); + struct exynos_iommu_owner *owner; + struct device *dev = pinf->dev; struct sysmmu_drvdata *data; + int ret; - if (!has_sysmmu(dev)) - return ERR_PTR(-ENODEV); + owner = kzalloc(sizeof(*owner), GFP_KERNEL); + if (!owner) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&owner->controllers); + mutex_init(&owner->rpm_lock); + owner->domain = &exynos_identity_domain; + + ret = iommu_of_xlate(pinf, &exynos_iommu_ops, -1, + &exynos_iommu_of_xlate, owner); + if (ret) + goto err_free; list_for_each_entry(data, &owner->controllers, owner_node) { + data->master = dev; /* * SYSMMU will be runtime activated via device link * (dependency) to its master device, so there are no @@ -1412,11 +1426,17 @@ static struct iommu_device *exynos_iommu_probe_device(struct device *dev) DL_FLAG_PM_RUNTIME); } - /* There is always at least one entry, see exynos_iommu_of_xlate() */ + /* iommu_of_xlate() fails if there are no entries */ data = list_first_entry(&owner->controllers, struct sysmmu_drvdata, owner_node); + dev_iommu_priv_set(dev, owner); + return &data->iommu; + +err_free: + kfree(owner); + return ERR_PTR(ret); } static void exynos_iommu_release_device(struct device *dev) @@ -1430,42 +1450,19 @@ static void exynos_iommu_release_device(struct device *dev) device_link_del(data->link); } -static int exynos_iommu_of_xlate(struct device *dev, - struct of_phandle_args *spec) +static int exynos_iommu_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv) { - struct platform_device *sysmmu = of_find_device_by_node(spec->np); - struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); - struct sysmmu_drvdata *data, *entry; - - if (!sysmmu) - return -ENODEV; - - data = platform_get_drvdata(sysmmu); - if (!data) { - put_device(&sysmmu->dev); - return -ENODEV; - } - - if (!owner) { - owner = kzalloc(sizeof(*owner), GFP_KERNEL); - if (!owner) { - put_device(&sysmmu->dev); - return -ENOMEM; - } - - INIT_LIST_HEAD(&owner->controllers); - mutex_init(&owner->rpm_lock); - owner->domain = &exynos_identity_domain; - dev_iommu_priv_set(dev, owner); - } + struct sysmmu_drvdata *data = + container_of(iommu, struct sysmmu_drvdata, iommu); + struct exynos_iommu_owner *owner = priv; + struct sysmmu_drvdata *entry; + /* FIXME this relies on iommu_probe_device_lock */ list_for_each_entry(entry, &owner->controllers, owner_node) if (entry == data) return 0; - list_add_tail(&data->owner_node, &owner->controllers); - data->master = dev; - return 0; } @@ -1473,10 +1470,10 @@ static const struct iommu_ops exynos_iommu_ops = { .identity_domain = &exynos_identity_domain, .domain_alloc_paging = exynos_iommu_domain_alloc_paging, .device_group = generic_device_group, - .probe_device = exynos_iommu_probe_device, + .probe_device_pinf = exynos_iommu_probe_device, .release_device = exynos_iommu_release_device, .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, - .of_xlate = exynos_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = exynos_iommu_attach_device, .map_pages = exynos_iommu_map, From patchwork Thu Nov 30 01:10:22 2023 Content-Type: text/plain; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:39 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:39 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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The insert_iommu_master(), especially the list_empty(), doesn't make a lot of sense. Based on the dtsi this supports an iommu instance that has exactly one device attached it. However each device may be connected to multiple instances with multiple stream ids. The iommus list must be sorted by instance or it will not parse correctly. Ideally this driver would work more like dart where each master allocates memory for dev_iommu_priv and records a list of the all the iommus and stream ids in that struct. That is too big of a change for this patch. Keep things basically the same, but rely on the core code to discover the iommu_device and stop confusingly using dev_iommu_priv to join SIDs into the same master when processing the assumed-to-be-sorted iommus list. Signed-off-by: Jason Gunthorpe --- drivers/iommu/msm_iommu.c | 93 ++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 56 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index f86af9815d6f98..6f21eec857c7d7 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -37,6 +38,15 @@ static DEFINE_SPINLOCK(msm_iommu_lock); static LIST_HEAD(qcom_iommu_devices); static struct iommu_ops msm_iommu_ops; +struct msm_xlate_args { + struct device *dev; + struct msm_iommu_ctx_dev *master; + struct msm_iommu_dev *iommu; +}; + +static int msm_iommu_of_xlate(struct iommu_device *core_iommu, + struct of_phandle_args *args, void *priv); + struct msm_priv { struct list_head list_attached; struct iommu_domain domain; @@ -357,38 +367,17 @@ static int msm_iommu_domain_config(struct msm_priv *priv) return 0; } -/* Must be called under msm_iommu_lock */ -static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev) +static struct iommu_device * +msm_iommu_probe_device(struct iommu_probe_info *pinf) { - struct msm_iommu_dev *iommu, *ret = NULL; - struct msm_iommu_ctx_dev *master; + struct msm_xlate_args args = { .dev = pinf->dev }; + int ret; - list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { - master = list_first_entry(&iommu->ctx_list, - struct msm_iommu_ctx_dev, - list); - if (master->of_node == dev->of_node) { - ret = iommu; - break; - } - } - - return ret; -} - -static struct iommu_device *msm_iommu_probe_device(struct device *dev) -{ - struct msm_iommu_dev *iommu; - unsigned long flags; - - spin_lock_irqsave(&msm_iommu_lock, flags); - iommu = find_iommu_for_dev(dev); - spin_unlock_irqrestore(&msm_iommu_lock, flags); - - if (!iommu) - return ERR_PTR(-ENODEV); - - return &iommu->iommu; + ret = iommu_of_xlate(pinf, &msm_iommu_ops, -1, &msm_iommu_of_xlate, + &args); + if (ret) + return ERR_PTR(ret); + return &args.iommu->iommu; } static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) @@ -596,22 +585,26 @@ static void print_ctx_regs(void __iomem *base, int ctx) GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); } -static int insert_iommu_master(struct device *dev, - struct msm_iommu_dev **iommu, - struct of_phandle_args *spec) +static int insert_iommu_master(struct msm_xlate_args *args, + struct msm_iommu_dev *iommu, + struct of_phandle_args *spec) { - struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev); + struct msm_iommu_ctx_dev *master = args->master; + struct device *dev = args->dev; int sid; - if (list_empty(&(*iommu)->ctx_list)) { + if (!args->iommu) + args->iommu = iommu; + + if (list_empty(&iommu->ctx_list)) { master = kzalloc(sizeof(*master), GFP_ATOMIC); if (!master) { dev_err(dev, "Failed to allocate iommu_master\n"); return -ENOMEM; } master->of_node = dev->of_node; - list_add(&master->list, &(*iommu)->ctx_list); - dev_iommu_priv_set(dev, master); + list_add(&master->list, &iommu->ctx_list); + args->master = master; } for (sid = 0; sid < master->num_mids; sid++) @@ -625,28 +618,16 @@ static int insert_iommu_master(struct device *dev, return 0; } -static int qcom_iommu_of_xlate(struct device *dev, - struct of_phandle_args *spec) +static int msm_iommu_of_xlate(struct iommu_device *core_iommu, + struct of_phandle_args *args, void *priv) { - struct msm_iommu_dev *iommu = NULL, *iter; + struct msm_iommu_dev *iommu = + container_of(core_iommu, struct msm_iommu_dev, iommu); unsigned long flags; int ret = 0; spin_lock_irqsave(&msm_iommu_lock, flags); - list_for_each_entry(iter, &qcom_iommu_devices, dev_node) { - if (iter->dev->of_node == spec->np) { - iommu = iter; - break; - } - } - - if (!iommu) { - ret = -ENODEV; - goto fail; - } - - ret = insert_iommu_master(dev, &iommu, spec); -fail: + ret = insert_iommu_master(priv, iommu, args); spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -690,10 +671,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) static struct iommu_ops msm_iommu_ops = { .identity_domain = &msm_iommu_identity_domain, .domain_alloc_paging = msm_iommu_domain_alloc_paging, - .probe_device = msm_iommu_probe_device, + .probe_device_pinf = msm_iommu_probe_device, .device_group = generic_device_group, .pgsize_bitmap = MSM_IOMMU_PGSIZES, - .of_xlate = qcom_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = msm_iommu_attach_dev, .map_pages = msm_iommu_map, From patchwork Thu Nov 30 01:10:23 2023 Content-Type: text/plain; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:55 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:55 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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The function allows such units, only for tegra, to get the IDs they are supposed to program. The tegra HW that needs this function only supports tegra-smmu and arm-smmu, so implement the function there. This makes way to moving the id list into the private memory of the driver. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 11 +++++++++++ drivers/iommu/of_iommu.c | 18 ++++++++++++++++++ drivers/iommu/tegra-smmu.c | 11 +++++++++++ include/linux/iommu.h | 21 +++++++-------------- 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index adc7937fd8a3a3..02b8dc4f366aa9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1551,6 +1551,16 @@ static int arm_smmu_def_domain_type(struct device *dev) return 0; } +static bool arm_smmu_get_stream_id(struct device *dev, u32 *stream_id) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec->num_ids != 1) + return false; + *stream_id = fwspec->ids[0] & 0xffff; + return true; +} + static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, @@ -1561,6 +1571,7 @@ static struct iommu_ops arm_smmu_ops = { .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .def_domain_type = arm_smmu_def_domain_type, + .tegra_dev_iommu_get_stream_id = arm_smmu_get_stream_id, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 9c1d398aa2cd9c..8d5495f03dbbcb 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -8,6 +8,7 @@ #include #include #include +#include "iommu-priv.h" #include #include #include @@ -281,6 +282,23 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(of_iommu_get_resv_regions); +#if IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) || IS_ENABLED(CONFIG_ARM_SMMU) +/* + * Newer generations of Tegra SoCs require devices' stream IDs to be directly + * programmed into some registers. These are always paired with a Tegra SMMU or + * ARM SMMU which provides an implementation of this op. + */ +bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) +{ + const struct iommu_ops *ops = dev_iommu_ops(dev); + + if (!ops || !ops->tegra_dev_iommu_get_stream_id) + return false; + return ops->tegra_dev_iommu_get_stream_id(dev, stream_id); +} +EXPORT_SYMBOL_GPL(tegra_dev_iommu_get_stream_id); +#endif + struct parse_info { struct iommu_probe_info *pinf; const struct iommu_ops *ops; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 310871728ab4b6..cf563db3e3b48d 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -989,6 +989,16 @@ static int tegra_smmu_def_domain_type(struct device *dev) return IOMMU_DOMAIN_IDENTITY; } +static bool tegra_smmu_get_stream_id(struct device *dev, u32 *stream_id) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec->num_ids != 1) + return false; + *stream_id = fwspec->ids[0] & 0xffff; + return true; +} + static const struct iommu_ops tegra_smmu_ops = { .identity_domain = &tegra_smmu_identity_domain, .def_domain_type = &tegra_smmu_def_domain_type, @@ -996,6 +1006,7 @@ static const struct iommu_ops tegra_smmu_ops = { .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, .of_xlate = tegra_smmu_of_xlate, + .tegra_dev_iommu_get_stream_id = tegra_smmu_get_stream_id, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = tegra_smmu_attach_dev, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f0aaf55db3c09b..0ba12e0e450705 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -412,6 +412,9 @@ struct iommu_ops { int (*def_domain_type)(struct device *dev); void (*remove_dev_pasid)(struct device *dev, ioasid_t pasid); + bool (*tegra_dev_iommu_get_stream_id)(struct device *dev, + u32 *stream_id); + const struct iommu_domain_ops *default_domain_ops; unsigned long pgsize_bitmap; struct module *owner; @@ -1309,26 +1312,16 @@ static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_m #endif /* CONFIG_IOMMU_DMA */ -/* - * Newer generations of Tegra SoCs require devices' stream IDs to be directly programmed into - * some registers. These are always paired with a Tegra SMMU or ARM SMMU, for which the contents - * of the struct iommu_fwspec are known. Use this helper to formalize access to these internals. - */ #define TEGRA_STREAM_ID_BYPASS 0x7f +#if IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) || IS_ENABLED(CONFIG_ARM_SMMU) +bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id); +#else static inline bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) { -#ifdef CONFIG_IOMMU_API - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (fwspec && fwspec->num_ids == 1) { - *stream_id = fwspec->ids[0] & 0xffff; - return true; - } -#endif - return false; } +#endif #ifdef CONFIG_IOMMU_SVA static inline void mm_pasid_init(struct mm_struct *mm) From patchwork Thu Nov 30 01:10:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748555 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="INXWqdqc" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FA3DD54; Wed, 29 Nov 2023 17:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MdI03JHoSpNb6wfkhxmvINBZ5QE3A1X7JT0qNXTCqxTSnw9/G5qjD1TxxRyE8cnk0mU4W05J9+24jseiY0nLbPcz226Z/UXgtcHZUUll7xgF9HMqiBw4Ns8weogdaYbAMFZj3bRt4nIjxx7+c5A14sRbSytt9kP/7LoL/2HZRDMv/j5aOtxz19rPmXjRlZ1MdJqvqna8vUS+FMRpBkwzjrJjPKe5XdvIx6YmHaIuYoUSL8WlhhGY4bHqn9zxuygVF/l+JOXg8QMem/w3QkdSFj0GGnDAKa0bKDDPkhyYL/cSj8XgGzVKrQ9TqXX5dFEeA/Xd1Z8cHQyJuz3Cjrlx1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mNc0i8b19f67qGg7jaCMO7gIkmzVDan6cC8FlSSYH2o=; b=PVFYPcyxvDMzXhe1i/g0aqirYRrbXjl7/xMmKcK3yWNwrjaHQMe/Q9MvRBUnMrR9lKrMwHW/z4pgj2ikNbQGZUGtQKz2SdJM8aX3ZZz8yXJgWf0RHx7LnDbviOQwHIslqon/FK5+CC9qhj5DtjNVrZVpsJQ2kBSmvfkY2Z8KTXsdbUcrQZQlrwevWAC/GT2PMMUmFUr5VsIsAFyrhQVJM4wnyQqrd1Le5RD/wXslCDWrrPVwoiP0BPFMRIzqtfnQYVwoKI1WoKG1TxvQtB3/JI53UGmYDhKi9ETC/DqnrPx8kmE0xFB57LvGprjMnImIJRjiRt6+IFX6OaJtEKleaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mNc0i8b19f67qGg7jaCMO7gIkmzVDan6cC8FlSSYH2o=; b=INXWqdqclBICUJjjXFuMPgFLO24Al4fug/47pDUXnE+dt1EFdrhWsovH259yZyK99z8XSxR4I1TkDubuSn4KmxnLbYUuSqkFYH0U6lNYIGg1A4wJErBXg8VA0c3CFT4XSnTEepmicUaBzj37Xa1J+JY1UfIH4R3tFnSskHMB/uHbAIQIkfSKEZ4W1Fka1eEqpHqjfb+3D1FPWxUb5jnMrjrEHYByhvZDEAhvLmGD+wIXq0Ofr0EXtTb80ygvF75xkmQ8oAZa/O01ND5rfMm/3Pb2LnZ2tn57AAJUt33N6cPKlEq936U3CUKjiPmBatbxI9D1yj7RWPYqM1tC2rR8jA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:48 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:48 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 19/30] iommu/mtk: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:26 -0400 Message-ID: <19-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0004.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::18) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d3c6e54-176d-498f-da95-08dbf1412b79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EXY2ttH4pyhsm2YJc/WuQ+XxNnXTnWaCedP+qxpCDaXJuBY7Tnu6X3q/091tlNCC51kpIbTaV+RhcD0QTjd9Wn31YcPOcpLPqPFZ2idU9CL24yyyLpMxYkxNIjqawWiQJfWFzsKlC+0cStc9n7I7OFBViRdl7j3L1TFzbKltsBS0yN3nwdpzkDFkOR05+zo2V+9kWqmk/tCTPetycKAUMb+k6uoVs9HIMiMJnWGBkSDm3Q3+0fmyD4y8Q5osfIPiOzvEcY54fo5SEd2EYrKtrH6/UQTsTvtQjKzYbxcRf25toMrpwSgvung13rUy657rXuy0YLCCYOqwM5naOAf2Jgj1ldhmcWLjtLHIlh0yTZHOn6XofOzXdv+yN3yrzfuh3i0mpY6r4tLI4zw4r3Ca3RGIPRgR/k7/r4H7OZg65TMBsx1j08VyZ/t1ELExLLCG4FjJylPecIfH1Fw/QgRxmNm/GfUEHUNx6kdmAprvP2NNKtH4UFpchmT01d40+nEaxXlXfgjRvHiAIYliKu5HY4ilGKQjFyaRMlTbAowRCHO6L/TGuwqvf9MVkygm9SGIpxqzS6RoXFCRcSdAkIxOBYZNfwf6swBYZnf/H4Znb/SQhHLfreFkaiYHM7vKzKx0Kt6GxYsj2RdD1xCZpQoMrg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(30864003)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m/tpZQKcluujheAqzGnsfhypUuiVioZwVqtFoS6Q8reZVg9Zvx1h+ck+rqme/IFQXOPfDArHdTxbN5Qka4omTa/liI0RQTbxtrQiH9h7KjMpn7Q46tLjqL35V3QoIp2OVmHeX0zUV0lexS7xuwH3jodV6j2wBf7Y48ARZEwHR1ndObPARt5DvoqLcEV7proUdCQtWgXqoOuAN96KOifHDPX0jbMx3I+ee5idllzMTlQaHzECbJbWzQBzcEQoDKGeSiTYBhbwXHkQNm0jJu36TucLgk88rpLncdj9/IzvnAaFT+NMTTAdg/2RJfNLJjO0giloleI05kNDngZ6sCxTVY5csnFPwX0l5c0Jr3KDPUy7YUx85Jzq9G9FjhZ8L2b0u09ZXt8BXwGEl556I8ca5BVcfdfE7gGWxe3JlgVorbhV2kG0hxDsYVzs7eUIhQPaXfMmq+dQzi3yI6Pz+1cDEoAVONG9/MkbJEkGIyUJCjBKcwDl3WC6/CmONsaCpzcLgyam+GYbKDJ/Xwz4Wdxl039/i+X+BgP5u6YndVo58649BClQx9i8jDfTlpqTLEF5pwJA1mA5g7XUgziOga06oymnUbybEPCiOxyMIQG256kegwt/x2YyfEQSFBqDxsSZZ+O9mBrH5VBrZRfPks57jb4n57JK39llHLHGjpAbrI9L/HthwY7Gwi+S7P5Qfzgg5kZnNxYZ3PD/fPUpCvv/shtva1wsV0e3W1W56v/9hMbwyL8x42Zru8/y2qlavaP9Aqgs9eETqasDhcRVFFShTGN9rRcTlYD6UnzLaTOcOeASXFQ01RsjJn3h+CbKXlH+RqXA2JtrdIBPGVi5AqpyT12aC5q+9ce1P0WnNkreDaawWIs8cuKjv5oXMpq0D9j8eYlodJwq0SetltIwuMbX3cPJo+1zZRm972yo7JHsj0B0CjvSl/uE1F8yNXC/vMSnmC6Ko9d3eZ4nwuYX/1sH0r4pYs2mghmt3QPuCS5RT6SK16tBaifBr4MC7sQqtF9KvcUb0EAzw5n8JsSg4Dfs6zX4I2VUD5fDfgXVK4tXAAobuS/ZH8JjDzwrss/KYsy24HniPbN/sqR0VOK/jmN0P1mDhCWO3zIW5LVilY1ZelPqQ1KIU54peTMiDpzZ5JkyBKwRTU0KM3eh9KRdWrLXhDi6qNDxn40E60HtuMDaNP4dQbwt27NbK87+MrR8cCM+WG8xgjhNjZ2ZhJnZBaOz4QcIVSKcIhxaoKMtQQNiL4eELSvLc/8YnE6y7dSlR4Uzdpz2PTIX64jy/X/8VxI7M+O92spUPjKEmuZQ2Il14f/jeP6239QQ8iehu+v/KIqtdWsVezVpdY6FpREB4866WE2I7QkWAuVWR9S3JTUOeU9FLEAcTyPdfkctEpfcnelFPTpwr6wgOHgrMqzj22KRo3JYJbzuAZBcNufjsPruG6rg4K8rp5GM0Vhvv44yOhYagbJlhlVJ1CwSFipPCtf5KOupaqaw558DhHJIdqLQNEN9DGppCNN30Oi6DwHjpSPoEJl17j6/twzaVcaH9jPaGYfP7goRcjFeKuBAqkSUooyq1SO+J5Rv7WWdj2YW4DOQ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d3c6e54-176d-498f-da95-08dbf1412b79 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.9319 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5iQCpGHG8rrK0heO2B4CQgapUNp1ZK85FyWiYHYC54oG2yQrFPC3AxQeYD/nYFkY X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 mtk was doing a lot of stuff under of_xlate, and it looked kind of like it might support multi-instances. But the dt files don't do that, and the driver has no way to keep track of which instance the ids are for. Enforce single instance with iommu_of_get_single_iommu(). Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove mtk_iommu_of_xlate(). Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Covnert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/mtk_iommu.c | 116 ++++++++++++++++++++------------------ 1 file changed, 62 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7abe9e85a57063..477171e83eaa6e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -277,6 +278,12 @@ struct mtk_iommu_data { struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; }; +struct mtk_iommu_device { + struct mtk_iommu_data *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct mtk_iommu_domain { struct io_pgtable_cfg cfg; struct io_pgtable_ops *iop; @@ -526,14 +533,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) static unsigned int mtk_iommu_get_bank_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); unsigned int i, portmsk = 0, bankid = 0; if (plat_data->banks_num == 1) return bankid; - for (i = 0; i < fwspec->num_ids; i++) - portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); + for (i = 0; i < mtkdev->num_ids; i++) + portmsk |= BIT(MTK_M4U_TO_PORT(mtkdev->ids[i])); for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { if (!plat_data->banks_enable[i]) @@ -550,7 +557,7 @@ static unsigned int mtk_iommu_get_bank_id(struct device *dev, static int mtk_iommu_get_iova_region_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); unsigned int portidmsk = 0, larbid; const u32 *rgn_larb_msk; int i; @@ -558,9 +565,9 @@ static int mtk_iommu_get_iova_region_id(struct device *dev, if (plat_data->iova_region_nr == 1) return 0; - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); - for (i = 0; i < fwspec->num_ids; i++) - portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); + for (i = 0; i < mtkdev->num_ids; i++) + portidmsk |= BIT(MTK_M4U_TO_PORT(mtkdev->ids[i])); for (i = 0; i < plat_data->iova_region_nr; i++) { rgn_larb_msk = plat_data->iova_region_larb_msk[i]; @@ -579,22 +586,22 @@ static int mtk_iommu_get_iova_region_id(struct device *dev, static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, bool enable, unsigned int regionid) { + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); struct mtk_smi_larb_iommu *larb_mmu; unsigned int larbid, portid; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); const struct mtk_iommu_iova_region *region; unsigned long portid_msk = 0; struct arm_smccc_res res; int i, ret = 0; - for (i = 0; i < fwspec->num_ids; ++i) { - portid = MTK_M4U_TO_PORT(fwspec->ids[i]); + for (i = 0; i < mtkdev->num_ids; ++i) { + portid = MTK_M4U_TO_PORT(mtkdev->ids[i]); portid_msk |= BIT(portid); } if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { /* All ports should be in the same larb. just use 0 here */ - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); larb_mmu = &data->larb_imu[larbid]; region = data->plat_data->iova_region + regionid; @@ -618,7 +625,7 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, } else { /* PCI dev has only one output id, enable the next writing bit for PCIe */ if (dev_is_pci(dev)) { - if (fwspec->num_ids != 1) { + if (mtkdev->num_ids != 1) { dev_err(dev, "PCI dev can only have one port.\n"); return -ENODEV; } @@ -708,7 +715,9 @@ static void mtk_iommu_domain_free(struct iommu_domain *domain) static int mtk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; + struct mtk_iommu_data *frstdata; struct mtk_iommu_domain *dom = to_mtk_domain(domain); struct list_head *hw_list = data->hw_list; struct device *m4udev = data->dev; @@ -777,12 +786,12 @@ static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); if (domain == identity_domain || !domain) return 0; - mtk_iommu_config(data, dev, false, 0); + mtk_iommu_config(mtkdev->iommu, dev, false, 0); return 0; } @@ -860,14 +869,28 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, return pa; } -static struct iommu_device *mtk_iommu_probe_device(struct device *dev) +static struct iommu_device * +mtk_iommu_probe_device(struct iommu_probe_info *pinf) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev; + struct device *dev = pinf->dev; + struct mtk_iommu_data *data; struct device_link *link; struct device *larbdev; unsigned int larbid, larbidx, i; + data = iommu_of_get_single_iommu(pinf, &mtk_iommu_ops, 1, + struct mtk_iommu_data, iommu); + if (IS_ERR(data)) + return ERR_CAST(data); + + mtkdev = iommu_fw_alloc_per_device_ids(pinf, mtkdev); + if (IS_ERR(mtkdev)) + return ERR_CAST(mtkdev); + mtkdev->iommu = data; + + dev_iommu_priv_set(dev, mtkdev); + if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) return &data->iommu; @@ -876,42 +899,46 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) * The device that connects with each a larb is a independent HW. * All the ports in each a device should be in the same larbs. */ - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); if (larbid >= MTK_LARB_NR_MAX) - return ERR_PTR(-EINVAL); + goto err_out; - for (i = 1; i < fwspec->num_ids; i++) { - larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); + for (i = 1; i < mtkdev->num_ids; i++) { + larbidx = MTK_M4U_TO_LARB(mtkdev->ids[i]); if (larbid != larbidx) { dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", larbid, larbidx); - return ERR_PTR(-EINVAL); + goto err_out; } } larbdev = data->larb_imu[larbid].dev; if (!larbdev) - return ERR_PTR(-EINVAL); + goto err_out; link = device_link_add(dev, larbdev, DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); if (!link) dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); return &data->iommu; + +err_out: + kfree(mtkdev); + return ERR_PTR(-EINVAL); } static void mtk_iommu_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; struct device *larbdev; unsigned int larbid; - data = dev_iommu_priv_get(dev); if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); larbdev = data->larb_imu[larbid].dev; device_link_remove(dev, larbdev); } + kfree(mtkdev); } static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) @@ -931,7 +958,9 @@ static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_pla static struct iommu_group *mtk_iommu_device_group(struct device *dev) { - struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *c_data = mtkdev->iommu; + struct mtk_iommu_data *data; struct list_head *hw_list = c_data->hw_list; struct iommu_group *group; int groupid; @@ -957,32 +986,11 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev) return group; } -static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct platform_device *m4updev; - - if (args->args_count != 1) { - dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", - args->args_count); - return -EINVAL; - } - - if (!dev_iommu_priv_get(dev)) { - /* Get the m4u device */ - m4updev = of_find_device_by_node(args->np); - if (WARN_ON(!m4updev)) - return -EINVAL; - - dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); - } - - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static void mtk_iommu_get_resv_regions(struct device *dev, struct list_head *head) { - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; const struct mtk_iommu_iova_region *resv, *curdom; struct iommu_resv_region *region; @@ -1012,10 +1020,10 @@ static void mtk_iommu_get_resv_regions(struct device *dev, static const struct iommu_ops mtk_iommu_ops = { .identity_domain = &mtk_iommu_identity_domain, .domain_alloc_paging = mtk_iommu_domain_alloc_paging, - .probe_device = mtk_iommu_probe_device, + .probe_device_pinf = mtk_iommu_probe_device, .release_device = mtk_iommu_release_device, .device_group = mtk_iommu_device_group, - .of_xlate = mtk_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = mtk_iommu_get_resv_regions, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .owner = THIS_MODULE, From patchwork Thu Nov 30 01:10:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748563 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:42 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:42 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 20/30] iommu/ipmmu-vmsa: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:27 -0400 Message-ID: <20-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0047.namprd16.prod.outlook.com (2603:10b6:805:ca::24) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e29a214-41ce-4329-91e6-08dbf1412a6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /RJ2KekhIZ/9FvZTbwgp3tGsaW2gq7WODqPGvmzeDxCk+0v0u/c+Y89nkoST/WWkvPvCw7SkEPScltSJiufLl47hdBiukrGJY2Z1yDudK8eAL0LJyiPad3WxmLLzrcOubvSAK1c1MuVqPcVWGIqSRJ0kiIabj32gv+7TlGvPFElgqC7JOaHXTvlWqUxcARkiQS0z6serUy2ChPT5HNJZWeyRhAw2mXwnw0uzGy5Cw4DYZJMbIhOeZHUE8oDMo9nKwRnPcuhYSogcdGq9xMoWNuX1qCOorYwlRZB0atcD3xytrcHGBNi+GVvBKWkaPYnHTzM33B1Vm/GMqeERd4N6inrSJzeIJkR/aEgsUHrQny0z/1SFYdZwfUnqWdIqyuNaTcDvx6cjyToqnKF9zIfNMaDawLV3rWzPCc4YMsQn3qGBW21RakgZlXjlyKcswcJYJsozWZh3n1gvN8r03yg8Px4+svQ39E9dnlYUhozPpLZh3ZC4ONIQyn6/GJQtlMIKv7rWgDg466eD/7pSmO45S5ra9tdb4dh2aroXjSfOXrLZ1PEUYnelXd+7MEHNK5u2jMgmuy7b8QxptGJEchwu2fSus+ZNFSj5kK/83+eClCfKH3nRjafLNSmj+Aya97MntnoQMSkwKhdvVDAyTFCOXQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mbImv2xeatnCFPsd9Do35WSABEP6L5JyzhkK9KNTExS80+lNlERWh60T46o08+1tBoKrM/maC37DnacXdjqL//8bPhH19ucd82MKskkSGgjoSDxjg3AfuDtuFCM0Q0/7+h9UGVjexvBp1MVrxS1N+xVVQRnMwximw6LuswtoTDxCcP4McOhn2OeufuizSoO7lnmvZ2E9GOUNcGTQEkXDdWO3zv4DPMQ1ZDFMidS9qVL31DKdV/EgKgC22fYRW5Nhw74BhuCuE4W0ODM/LgupUzmsgBm2+cmnDvvkd7FKV7vDBYJ6RonLsrR20nm2NW4tH6W9OiOgy3wC25/7Xba7jaHnT7DhhVu/TThZbiyy5DYIQIpyIme2EQKVf2CMH4bF6ypVshgUSh9bEc8Ku32zZ4IRGXLR8sCu+P3q7tJbBc2Q6aEE0+Y2pHRiHMzvtZt+tM48s7KKVUyMzdio2lBHWeKdLY1TOm9PJDhVOXhJ3eGHN2M2XGtqr+HneC3mo1nJDOfLk97OrtVL+bbffZ7w3BX22P25+DM9ePBSb02PeuNLEe94why6eP13hpjXz7AoFd7rCDGKAGcVxmwHL5JneTe3dO7Dkd5Qw0YP3Ddb/7tNRWAfgR9GgGAIvIDOG6kjFnZMhzntzwy5+wukj2tyX2ELazEGa+Kd8aMqL9RLOAV4a1c0c70jJawRWOxlBrbRf7eQyns2yxn1VCHa3XpS6EUUYsvM0nrChxiXVL52xCGleUamUon6dsyUO9xAxzLVj4Uz94fq9Ezj7OMzdQvupPhrfWz+TOP56A+YWgEJbKSg2SxNri032dje8VBrhsLYi3eXZO+oevJld/uNwT7/Q6QZl0A7AFjpeBxHn7uuwN70s8xIfYds9Oytbh8myqwT4nk1rXhciM4rXn1m28pFYwXNsv4wN/UjEMhb5+YAT3fPukQfBs05ZAsZ5n16Qs2++Bzif8RFG/QlxF71rYLGh5FZq/D1+uD2q7rdvEQECx1242W0BR4SD9skg7V56t4A76rEgf5diPUro21F6+GaTNmrUhSoSPaYFddcTxUi0y4dmdkHSSNIpY+N1JCpEXFwPuLKnn/UbRp1K4Knxl//dTXGDgCA9Gq76Nw232FCy+fcXA2YUmVpPLoMXUNxt+Hka/slaumbCk64R+G6St7OpLptWdByI8ux2iXAi0CKJK5meEJ0pJGHB3uQR1rPYpQy66HVyN1iCoSLD9skLca3PPWlJTW/HcnWOfpMCfbYuXP9fqP+CIY+IwKJ07V99f6YyTLNDJBEvoed8KWBZxQBhr8r5+q3Hy64R4XyuPDAp9atbM+aGceMBhPsWNZNSOrhJr2gPvkMoWLcmDskiCSZ6DdIy5hb35lnwvm5kjx3pFVCInuBxdfcsQM7REmRVeS6pmE8VsBEx/h7cjw5qw9yuZIf0PQN5hYVzI75RP7k7xiZNmZTdW9ElxXSRBXVW/6OV6wbl70fk2bquV3dSOXGoI/IMjEpBcRzYYfaHL4y8nfvzBwMIkcBWaXcwj2m3b2DjR1c+5Y3WBNnuySl9NkumIRRBr1UN5+J2vcDahmj34GFZeiQQPjeYzG0IOSRgBR9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8e29a214-41ce-4329-91e6-08dbf1412a6b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.1998 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xPEmXM+q46raBIV/5oEHOHBYtvZgcViHkkaCMolPMmkVRH+fJO7gv4pqjqkrRr/x X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 ipmmmu-vmsa supports a single instance with multiple ids. It has a special check if the device is permitted, move that to the top of probe. Use iommu_of_get_single_iommu() to check and obtain the iommu device. Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove ipmmu_of_xlate(), ipmmu_init_platform_device(), and to_ipmmu(). Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Convert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/ipmmu-vmsa.c | 96 +++++++++++++++++--------------------- 1 file changed, 42 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index ace1fc4bd34b0f..ba984017065f98 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,8 @@ #define IPMMU_UTLB_MAX 64U +static const struct iommu_ops ipmmu_ops; + struct ipmmu_features { bool use_ns_alias_offset; bool has_cache_leaf_nodes; @@ -67,6 +70,12 @@ struct ipmmu_vmsa_device { struct dma_iommu_mapping *mapping; }; +struct ipmmu_vmsa_master { + struct ipmmu_vmsa_device *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct ipmmu_vmsa_domain { struct ipmmu_vmsa_device *mmu; struct iommu_domain io_domain; @@ -83,11 +92,6 @@ static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) return container_of(dom, struct ipmmu_vmsa_domain, io_domain); } -static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) -{ - return dev_iommu_priv_get(dev); -} - #define TLB_LOOP_TIMEOUT 100 /* 100us */ /* ----------------------------------------------------------------------------- @@ -591,9 +595,9 @@ static void ipmmu_domain_free(struct iommu_domain *io_domain) static int ipmmu_attach_device(struct iommu_domain *io_domain, struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); + struct ipmmu_vmsa_device *mmu = master->iommu; unsigned int i; int ret = 0; @@ -629,8 +633,8 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, if (ret < 0) return ret; - for (i = 0; i < fwspec->num_ids; ++i) - ipmmu_utlb_enable(domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; ++i) + ipmmu_utlb_enable(domain, master->ids[i]); return 0; } @@ -639,7 +643,7 @@ static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { struct iommu_domain *io_domain = iommu_get_domain_for_dev(dev); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); struct ipmmu_vmsa_domain *domain; unsigned int i; @@ -647,8 +651,8 @@ static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain, return 0; domain = to_vmsa_domain(io_domain); - for (i = 0; i < fwspec->num_ids; ++i) - ipmmu_utlb_disable(domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; ++i) + ipmmu_utlb_disable(domain, master->ids[i]); /* * TODO: Optimize by disabling the context when no device is attached. @@ -708,20 +712,6 @@ static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, return domain->iop->iova_to_phys(domain->iop, iova); } -static int ipmmu_init_platform_device(struct device *dev, - struct of_phandle_args *args) -{ - struct platform_device *ipmmu_pdev; - - ipmmu_pdev = of_find_device_by_node(args->np); - if (!ipmmu_pdev) - return -ENODEV; - - dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev)); - - return 0; -} - static const struct soc_device_attribute soc_needs_opt_in[] = { { .family = "R-Car Gen3", }, { .family = "R-Car Gen4", }, @@ -772,24 +762,10 @@ static bool ipmmu_device_is_allowed(struct device *dev) return false; } -static int ipmmu_of_xlate(struct device *dev, - struct of_phandle_args *spec) -{ - if (!ipmmu_device_is_allowed(dev)) - return -ENODEV; - - iommu_fwspec_add_ids(dev, spec->args, 1); - - /* Initialize once - xlate() will call multiple times */ - if (to_ipmmu(dev)) - return 0; - - return ipmmu_init_platform_device(dev, spec); -} - static int ipmmu_init_arm_mapping(struct device *dev) { - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); + struct ipmmu_vmsa_device *mmu = master->iommu; int ret; /* @@ -831,16 +807,27 @@ static int ipmmu_init_arm_mapping(struct device *dev) return ret; } -static struct iommu_device *ipmmu_probe_device(struct device *dev) +static struct iommu_device *ipmmu_probe_device(struct iommu_probe_info *pinf) { - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct device *dev = pinf->dev; + struct ipmmu_vmsa_master *master; + struct ipmmu_vmsa_device *mmu; - /* - * Only let through devices that have been verified in xlate() - */ - if (!mmu) + if (!ipmmu_device_is_allowed(dev)) return ERR_PTR(-ENODEV); + mmu = iommu_of_get_single_iommu(pinf, &ipmmu_ops, -1, + struct ipmmu_vmsa_device, iommu); + if (IS_ERR(mmu)) + return ERR_CAST(mmu); + + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); + master->iommu = mmu; + + dev_iommu_priv_set(dev, master); + return &mmu->iommu; } @@ -857,24 +844,25 @@ static void ipmmu_probe_finalize(struct device *dev) static void ipmmu_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); + struct ipmmu_vmsa_device *mmu = master->iommu; unsigned int i; - for (i = 0; i < fwspec->num_ids; ++i) { - unsigned int utlb = fwspec->ids[i]; + for (i = 0; i < master->num_ids; ++i) { + unsigned int utlb = master->ids[i]; ipmmu_imuctr_write(mmu, utlb, 0); mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; } arm_iommu_release_mapping(mmu->mapping); + kfree(master); } static const struct iommu_ops ipmmu_ops = { .identity_domain = &ipmmu_iommu_identity_domain, .domain_alloc_paging = ipmmu_domain_alloc_paging, - .probe_device = ipmmu_probe_device, + .probe_device_pinf = ipmmu_probe_device, .release_device = ipmmu_release_device, .probe_finalize = ipmmu_probe_finalize, /* @@ -884,7 +872,7 @@ static const struct iommu_ops ipmmu_ops = { .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) ? generic_device_group : generic_single_device_group, .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, - .of_xlate = ipmmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = ipmmu_attach_device, .map_pages = ipmmu_map, From patchwork Thu Nov 30 01:10:29 2023 Content-Type: text/plain; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:50 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:50 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 22/30] iommu/qcom: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:29 -0400 Message-ID: <22-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN1PR12CA0110.namprd12.prod.outlook.com (2603:10b6:802:21::45) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 724c4ab5-7a07-4e75-5bae-08dbf1412b96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: O+TTURoAd06a5nhc1hEqPMI3UF8xNQp/QEVs/OUUBk0iMdto60WmWpf0sfwLRxPgM1BswcDjOFzMZx/5EE0DCvqWUNUGIP7cP+8bGBieThqSlPuA7qKb3DdTBxPgZzWsZ2ad4o0usd2s0iGKLXdw6Duqld/uNibwRtS10IRhkVxe8pgTKJ6pThePbAAEHB0fEYNbAWAlFKa9O1+jrjKeYWMvt4cxZeW0Z8fuoV3BmuRIYGYy+YNxYJs3vp2iJsmrKj5gm5hVv8/yMhSH/6OteNodtVk5QWub0hg2h5ZAZv+h+jh0GrLCYG5ZKTs6g2rB/1Lxc/+enNHqRU7Q8EOiF9+Gz7Q9LJ4MzLcH+7lI6NuuK8pK0V0pytzM1220Y0lkDfjhkEfVl9KVlKDTJVozKo2kF6vsiKI1Ge9F2dNdGYQULwTsrwWExe4do2X2vmy96DkOrRTU88xIqPrYguEMepRXMes+ZNJFZxi6uvTl14mdPgjlnA20EWX4kSQ4Ju8Z+JCotFAx7NmaYU48A3HT4bImxGGSX3ucqu1HrY7cLGw2POV7xR26GUCGvUy+AbU0+LGp+FdyU432yfHwR+G2oWxy5QQqEPD1HvuDmcdEKqEdH8TSnDlyUCBdWo1xi40I6gAo8qPCbXlrfA7NClCCsw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(30864003)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vEIPybqBLOiEuo3wsynDBlSBXaFbdYbgJaHD2oWwfj+LAKucVu0ZJpP3YhRqX0PGwcQOcTzO5ihXrB46zlTwSqguYit90dUKLwjVdoOuNPzhYAipOMOb+4LmbE0pnGXxEQ7sSmcBHtNYr/wSFjYvmXSSpY/CPvf+pIaJqcWB0MRWc8Ma+og2CipW+bze01eNmWb2JZOqUCMNh9CPFRwj1xsIHzSzGcZ84ssKj4GRrUaKkTAW/mdOvwdX8PmdvTffsjNZqJJe5bJA5vjCSupEE6aHODwB5JLf9A1v4t7Xo17oM2GFVMZQw3Bpvrcj+0CNIeukF+KDsWsCTTNb+iFBg2UbKoOl1gDNqjkt+VJujaOWwaD5xtiA2Ud56vA1e7aXFU/+NDM/DvCmhRweJ2FV3B6UQVoPPqBG5Fhp2sUygZqUVZ1HWIW3/UE/JhYvhRB943UGO3GrfWleyY/qmCBLKc5tI08eukC3hPpxiWKs3umDUHQeIM4VZvSOzOXVDEm/gNGFBtCGRoGOcF29Ozfx3dqFL80zw/Qic4xYFBR0qUdA+uS/RL62GwEO0wU5WwJRfyj9d5kY5+o3wIPp0c0+xTJgpbJ9L7HMdoruiBRaQos9Bmi0pE9TQbANrJ8i0sEZ0smGeiKKKLNOrzPT5mQktpEXGyacpSS+uqiCr0sAITBBn9oWYVZgdejrnDodhliZ6qWn0cyBKp0huiJswQclonOJV9Gr7Swx8QvXH1TC9WCO8KWOC6R+Qe52ZBq+LI47S92ccuchTKTqORKcf+l8GkZRDKUv9sSs1NsTtvOU4k/M48X2txz3i5Ertm2YS/GOi99/Rzzu6FFjMNHV2R5amjd+AaRYTM7VEdwpqrU6aD5xRbsJMHKJZj/CKHf6yYKeCMRLSfSb/X5cLern8NsVvR8eLxy/WZx5vbo3SfjUFqah8S2sjf7D0qRBcUwnKf0iIh+dwPV+pUhtcqjIflfYC9NhKKBqBl1g2Y2AGIqXnWdYzQVvkor7o5kj/h9hczJC1QlS7xSm2F9GUIaCy4AxLlqtc9Pz3nE9EiULD/Ppe+bXceBRf6GHnvuTd+bxm23VJ8UYRwouOsQyzhEN3CRgHc1ipRERxmhyUn77WAI+HtusSeofn3kiRcKiEnKqMSWiwdLl7f5xbhi7n1CudL5CiuvGhn5DQMGlgZ+8kBqw/bzF2GgtV3uCe9V7V2U1HjZvgNblTMReqd/QlWVc+AfPaONwwXLSKdKR8Y8Iwxk/Ag8GkYOODVGlRFrITOj4h7G56UM8K6oqkpuxIso+bQO6CuIowpCLZnnSgUb6H5O/uXaBlpPQb/9QKo8qw/C3FB/Q6oQ4BDa6DQTOQ8oFWfvLVTDHoCxeIFWqDVIQBNBGymISE3KF2l4w3lfMWhfyzIiH8A6oB3Ml4V5SE4OeEJyWFvETCMvJQZmgGSfp90tVOPQvuMLPIk5XA6scj++xIh2Y3wj9TY7cqgEmSfWlM6B9MaOkItm/PIbls66OU8DWYA1+WVwMevvxeDZ/fwpURfbyjeqfadUKrdMV+E+9i5l8M7SLrznQxtKTDoqjeyh2iEKdjK5Q2Csv0oqrHtMYzXp5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 724c4ab5-7a07-4e75-5bae-08dbf1412b96 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:41.1568 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iHNY0/XFKudzaiQDGPMOffWaW/5YTl7Yg2HEy+dh2h1S10ihP0NQa7LaOTuM9PsT X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 qcom supports a single iommu instance with multiple ids. Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove qcom_iommu_of_xlate(). This already was checking that all instances are the same, it is now done in common code. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Store the per-dev data in the qcom_iommu_domain instead of the iommu and fwspec pointers. Convert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Remove to_iommu(). Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 161 ++++++++++++------------ 1 file changed, 81 insertions(+), 80 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 33f3c870086cea..4baca45df99971 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,12 @@ struct qcom_iommu_dev { struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */ }; +struct qcom_iommu_master { + struct qcom_iommu_dev *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct qcom_iommu_ctx { struct device *dev; void __iomem *base; @@ -68,8 +75,7 @@ struct qcom_iommu_domain { spinlock_t pgtbl_lock; struct mutex init_mutex; /* Protects iommu pointer */ struct iommu_domain domain; - struct qcom_iommu_dev *iommu; - struct iommu_fwspec *fwspec; + struct qcom_iommu_master *master; }; static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom) @@ -81,7 +87,7 @@ static const struct iommu_ops qcom_iommu_ops; static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) { - struct qcom_iommu_dev *qcom_iommu = d->iommu; + struct qcom_iommu_dev *qcom_iommu = d->master->iommu; if (!qcom_iommu) return NULL; return qcom_iommu->ctxs[asid]; @@ -114,11 +120,11 @@ iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) static void qcom_iommu_tlb_sync(void *cookie) { struct qcom_iommu_domain *qcom_domain = cookie; - struct iommu_fwspec *fwspec = qcom_domain->fwspec; + struct qcom_iommu_master *master = qcom_domain->master; unsigned i; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); unsigned int val, ret; iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0); @@ -133,11 +139,11 @@ static void qcom_iommu_tlb_sync(void *cookie) static void qcom_iommu_tlb_inv_context(void *cookie) { struct qcom_iommu_domain *qcom_domain = cookie; - struct iommu_fwspec *fwspec = qcom_domain->fwspec; + struct qcom_iommu_master *master = qcom_domain->master; unsigned i; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); } @@ -148,13 +154,13 @@ static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, size_t granule, bool leaf, void *cookie) { struct qcom_iommu_domain *qcom_domain = cookie; - struct iommu_fwspec *fwspec = qcom_domain->fwspec; + struct qcom_iommu_master *master = qcom_domain->master; unsigned i, reg; reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); size_t s = size; iova = (iova >> 12) << 12; @@ -218,14 +224,14 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, struct device *dev) { struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); struct io_pgtable_ops *pgtbl_ops; struct io_pgtable_cfg pgtbl_cfg; int i, ret = 0; u32 reg; mutex_lock(&qcom_domain->init_mutex); - if (qcom_domain->iommu) + if (qcom_domain->master) goto out_unlock; pgtbl_cfg = (struct io_pgtable_cfg) { @@ -236,8 +242,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, .iommu_dev = qcom_iommu->dev, }; - qcom_domain->iommu = qcom_iommu; - qcom_domain->fwspec = fwspec; + qcom_domain->master = master; pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain); if (!pgtbl_ops) { @@ -251,8 +256,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; domain->geometry.force_aperture = true; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); if (!ctx->secure_init) { ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); @@ -316,7 +321,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, return 0; out_clear_iommu: - qcom_domain->iommu = NULL; + qcom_domain->master = NULL; out_unlock: mutex_unlock(&qcom_domain->init_mutex); return ret; @@ -345,16 +350,16 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain) { struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); - if (qcom_domain->iommu) { + if (qcom_domain->master) { /* * NOTE: unmap can be called after client device is powered * off, for example, with GPUs or anything involving dma-buf. * So we cannot rely on the device_link. Make sure the IOMMU * is on to avoid unclocked accesses in the TLB inv path: */ - pm_runtime_get_sync(qcom_domain->iommu->dev); + pm_runtime_get_sync(qcom_domain->master->iommu->dev); free_io_pgtable_ops(qcom_domain->pgtbl_ops); - pm_runtime_put_sync(qcom_domain->iommu->dev); + pm_runtime_put_sync(qcom_domain->master->iommu->dev); } kfree(qcom_domain); @@ -362,7 +367,8 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain) static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) { - struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); + struct qcom_iommu_dev *qcom_iommu = master->iommu; struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); int ret; @@ -382,7 +388,7 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev * Sanity check the domain. We don't support domains across * different IOMMUs. */ - if (qcom_domain->iommu != qcom_iommu) + if (qcom_domain->master->iommu != qcom_iommu) return -EINVAL; return 0; @@ -393,20 +399,20 @@ static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain, { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct qcom_iommu_domain *qcom_domain; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); + struct qcom_iommu_dev *qcom_iommu = master->iommu; unsigned int i; if (domain == identity_domain || !domain) return 0; qcom_domain = to_qcom_iommu_domain(domain); - if (WARN_ON(!qcom_domain->iommu)) + if (WARN_ON(!qcom_domain->master)) return -EINVAL; pm_runtime_get_sync(qcom_iommu->dev); - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); /* Disable the context bank: */ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); @@ -461,11 +467,11 @@ static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova, * cannot rely on the device_link. Make sure the IOMMU is on to * avoid unclocked accesses in the TLB inv path: */ - pm_runtime_get_sync(qcom_domain->iommu->dev); + pm_runtime_get_sync(qcom_domain->master->iommu->dev); spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); ret = ops->unmap_pages(ops, iova, pgsize, pgcount, gather); spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); - pm_runtime_put_sync(qcom_domain->iommu->dev); + pm_runtime_put_sync(qcom_domain->master->iommu->dev); return ret; } @@ -478,9 +484,9 @@ static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain) if (!qcom_domain->pgtbl_ops) return; - pm_runtime_get_sync(qcom_domain->iommu->dev); + pm_runtime_get_sync(qcom_domain->master->iommu->dev); qcom_iommu_tlb_sync(pgtable->cookie); - pm_runtime_put_sync(qcom_domain->iommu->dev); + pm_runtime_put_sync(qcom_domain->master->iommu->dev); } static void qcom_iommu_iotlb_sync(struct iommu_domain *domain, @@ -523,13 +529,38 @@ static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap) } } -static struct iommu_device *qcom_iommu_probe_device(struct device *dev) +static struct iommu_device * +qcom_iommu_probe_device(struct iommu_probe_info *pinf) { - struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + struct qcom_iommu_dev *qcom_iommu; + struct qcom_iommu_master *master; + struct device *dev = pinf->dev; struct device_link *link; + int ret; + int i; - if (!qcom_iommu) - return ERR_PTR(-ENODEV); + qcom_iommu = iommu_of_get_single_iommu(pinf, &qcom_iommu_ops, 1, + struct qcom_iommu_dev, iommu); + if (IS_ERR(qcom_iommu)) + return ERR_CAST(qcom_iommu); + + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); + + for (i = 0; i != master->num_ids; i++) { + u32 asid = master->ids[i]; + + /* + * Make sure the asid specified in dt is valid, so we don't have + * to sanity check this elsewhere: + */ + if (WARN_ON(asid > qcom_iommu->max_asid) || + WARN_ON(qcom_iommu->ctxs[asid] == NULL)) { + ret = -EINVAL; + goto err_free; + } + } /* * Establish the link between iommu and master, so that the @@ -540,63 +571,33 @@ static struct iommu_device *qcom_iommu_probe_device(struct device *dev) if (!link) { dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", dev_name(qcom_iommu->dev), dev_name(dev)); - return ERR_PTR(-ENODEV); + ret = -ENODEV; + goto err_free; } + dev_iommu_priv_set(dev, master); return &qcom_iommu->iommu; + +err_free: + kfree(master); + return ERR_PTR(ret); } -static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) +static void qcom_iommu_release_device(struct device *dev) { - struct qcom_iommu_dev *qcom_iommu; - struct platform_device *iommu_pdev; - unsigned asid = args->args[0]; + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); - if (args->args_count != 1) { - dev_err(dev, "incorrect number of iommu params found for %s " - "(found %d, expected 1)\n", - args->np->full_name, args->args_count); - return -EINVAL; - } - - iommu_pdev = of_find_device_by_node(args->np); - if (WARN_ON(!iommu_pdev)) - return -EINVAL; - - qcom_iommu = platform_get_drvdata(iommu_pdev); - - /* make sure the asid specified in dt is valid, so we don't have - * to sanity check this elsewhere: - */ - if (WARN_ON(asid > qcom_iommu->max_asid) || - WARN_ON(qcom_iommu->ctxs[asid] == NULL)) { - put_device(&iommu_pdev->dev); - return -EINVAL; - } - - if (!dev_iommu_priv_get(dev)) { - dev_iommu_priv_set(dev, qcom_iommu); - } else { - /* make sure devices iommus dt node isn't referring to - * multiple different iommu devices. Multiple context - * banks are ok, but multiple devices are not: - */ - if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) { - put_device(&iommu_pdev->dev); - return -EINVAL; - } - } - - return iommu_fwspec_add_ids(dev, &asid, 1); + kfree(master); } static const struct iommu_ops qcom_iommu_ops = { .identity_domain = &qcom_iommu_identity_domain, .capable = qcom_iommu_capable, .domain_alloc_paging = qcom_iommu_domain_alloc_paging, - .probe_device = qcom_iommu_probe_device, + .probe_device_pinf = qcom_iommu_probe_device, + .release_device = qcom_iommu_release_device, .device_group = generic_device_group, - .of_xlate = qcom_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = qcom_iommu_attach_dev, From patchwork Thu Nov 30 01:10:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748562 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="oTWOZQwI" Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2053.outbound.protection.outlook.com [40.107.100.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD8B3D7D; Wed, 29 Nov 2023 17:10:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hmKwT6bexloyKBzeBinohdFYv0WwZUO9rnEZLicr75WLrlczS3hQeMqCbSiFw3ShpEhZ7PXv0nb2qDJVqo4/u1iawKSV8LAVK1nYEb0J0ebSiWoqp9dfZR9z6NVl3bzFLRYD3THvaiTixgZKqLc0YUyq/gYJskVfYwj3pRuN/F9vmlIB4gLmmxW1Eoyyq9/rW6N83l6sm0rTXA3ouKYadJsudqxTVdTymvSBuwCfNHkmgkhgzXXYRmV7Sa+kp7P+JRQOWfayOk4F4B1bvAwn1g3SFIW9e8mH27L2mkr81GZU7gq40YEGFahgJxG7hbVRoAVnFuX5Yx7joST9Q3RfQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n7aJKu7BohUpFcYIdwpDeid+Mzh23OW02rRcztcHd+0=; b=fcXLs3QALOfSwmxljqVm2JObO59htJiL0MrAcI2p8xb0lFsY8T6Fh4al49GD++RA3rRO4WkzN+75h4cWt9dMCymB+kaHtO5Moz0hnpYgLFMDMs1Yq55cEh5cJhfIJBxJnZxw1QsX9e+s28l0xGrKt8KTCjJ2mwsXe70QCps8fDYRcwg9rptArc4KRbxqzrdA53YNpCI0VfGpqWsDOf4KSWKhi64SsvF9Re0+taEpSYE6iiSUVvddhKjZBIT2s7zwo59M2+jCxtDmP/aCHaNSQk7lKcSpUk9SfbDz7G3UJgfXP77U95WU64j1sja7Gtw41e+3MvtYZfjguJ69XDqXQw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n7aJKu7BohUpFcYIdwpDeid+Mzh23OW02rRcztcHd+0=; b=oTWOZQwIRW+sRoJKgscUvtc8f2NmgRZbSzUE4lwGfogXcueSQPihSV+yNIkgGtgLGhTYWFPgCGqjLaQi8kTcTMr4Ay9ADyfKMLLzvZ320Ix4FTYMHwE/kehbAq60SwunwoTODfWNgbYgT5HIl+picAnGxU6I+7+AQHrIC5iwdL3wVszT8M5Ygw8j/iGI6QHn3hs50Jau5bEuCCbvdSxCGQxMpCM9u0d8oWp45gtCO67eUrXmiaOG5fqjRHVJpPAa7F+fk+IGE4Xoj0IBVsTR1idugCRFKtyipchb9giYcpDRZ5U9jP8NoRrRdmAtKJ+a4Vlv2vrgaQJI2/ZmlBuWdw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:43 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:43 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 24/30] iommu/virtio: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:31 -0400 Message-ID: <24-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0017.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::15) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: f184cbfa-52b3-4d89-5ed6-08dbf1412a6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LGVZ66x0Z/c4A6yfd8vLDEdf+b6sgChnN84rSZ7LBwHl2BtRXlBVm+2WpXBl5Lkgt3fvU9Y1jumfYyLXJwVsnSFmOeTPAuBHcQDCgsdIdbAPylZktkseaBYMxfcarg8nttCn/+57uar/E2l1KQB/VJWY9cA+j8Y3mvgbsDbFIa9pp9m991KxuSayertSROc3nPNAz51GFOUAe2rHa9DOrbyDMKntkOq92h+axz5GMHkTRVWdoZdNDpMMl9i6/YGtbvRS6eCqkt022p8DRfU3hoXgunNUV7EgTapOcWYY53teGi+TQoCViuNRCLerPKEKh1ETHIHmW21/uEqIsHCdQQUJnTpHffTwP3Gk8tXacvS3FqFSFc/FMNiAC2it8rjjbfsF1krkCJUfkUJaeBmSV8vOifI0dT6gZfKt0dbN3VQnwDogqEL3voeyWIIaQ/mn8TyHU2gNhhicbFjBJmRK9Ry0te6+5aw9mFHFSJwINCHBl7E6rQbUdzR1hUWbHP4in+htuzLmpRngudq7rkQ4bvcgHBH4gTeu/HwCZUpN60oPIz+0OPu7flsHG5DMHRHgRIQXuwjMFc4H+iKvhhBn7TWz8nARPFxV3Vj5Ug/lbRDB1hF/TzlsGlMMVErzoNN54o4jAv/2JE1X2R/zz8kc1A== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nwh4P5igKZINuWBNkgxmbvQVTx47VsyJlltLwDktBJ5Sfp+zWmHQRpNfPorx4iyl/Hgvhh1/FEeVyBF5Zq6fZ+2eyUE5WCbGEENQVCQPOwqldo36I2pczKDdV+eJ8nL0hCElkytr7kOfsogkKAV5pW5CD91YfwGzNL9eaX9C7/qO/l3e1zZUC4n4PaBymBeYddMrCztcXPyYl7P0iWtG5BA6K56QnJaLNcag9o+CbNGC+xFzJOREmljn/ZBaTzekHRAtiL/dYVB8ahqkg5ATjqWO+GoeObHVJ226nME2nEPIkZlS3Bd84gVE4AO/WNv11kXn5i45BoeLjdAi5U/cokM+QZYgLNepxmBaR1f7pMT3mwyfzNKF4jobw40tRv0LrcuUS3zIwhCnEMBKuo3G8fLapkZdyAZEVjfl6DVgov90plihm222NmdccwdRZFkrL7TI9dZwc6moWNNFPYwY+WLwDZQxitzRWQ/QjNcLiHRQPkncotfYaAbRHoNxu/GDxwvi0bRtKMMHMm8coHdM0MwGDWth9m12fNr2jfD+T9dLbuBzDQxgtxSHY0sSrJHPwYH76Jf5+Rcctt/o7vcc0Nbn8dYGs0FU1E/Q7EFdJDiLC3/hVAMfFW7xSkBWxGUpzSce4wKc/VpKg5NdJ9wyyPBItYvh+PG6dHk31G7BUwZ07mmPSX1kB5zisliy+8Qoj9vZh1PKlyjxVgQwW3ygv+MQ2KWlMn2MtxPDCvcxrKw1ngCSVMsgMV9GJUVWRSdUfxiCfF3r9MXqs1UA9ttjsz8173lGm0pI6Z+saOjrid9zq+fFjk1rkxn0Hh+bSnZbIBZ761+3jo5tvjXV3FvnfNx6MZIMnxl7/vGrNyxPDUck+d6l5FkyMs+XOoNLuwE54XUvoOvRlKlx84Tgxis7ttjSB+gqjrGGRqcdAEE9PqyyCgGkuzmB771Xyc/pcnsxYw3QCS9nQxEp1vztCE/+fcTz/nyaPpvfVdJMyVyDf7KbwZ2c92TAOXEhZykKl6qdXeppjvdL46Ctb2Qpcq5AmP6/x+gQqWM8CXH2sG4LZhcSBjJtrJHpYBs2MJbb8FUuF10DjM1hW3cVwm21wdp+VV1ZEjkKBOqRebIRzp6TpxZNr5zhgl5+Z89NRMG+U5LIDJx3nrveJCfPi/x7GoRMQHsCBx8ZEqBXpBlk8hLdGc8xDQizKMlQhoKN3t9Vdr+yRgyLqBnxZJhGWl+yhIfdn9qR+l0hnuMt+kfAXcxaS9HrOfL8TlYf93+7AFXXOt3sZTozi+zH+wkCGvp+hV2mgcV07gtlkVL8wtnDqgvcfTF5PB8xLsxnO2O/8O7WP6fB+3sjijOwEPiRTknInkW8KApty5bMTfglfpsLXa7eINg9E17IYIJxSn9kQOVk8nRnKTHIKKaaldEG+gFcKPJAJH40I5NEsbdu02UOtY86j9Vv6ttgh/yDZM0X6jl+UnvjA/X921+yeXFPEKlQzJLICs509GYnwWQG/7V4oY/8gV/svW0abeQxthJGvNGt+YWN0/PHHnXxDimEbTQfaLcso3Ons4SGokaZcshVdezW+tK1s33bzXmp51Mo0XVv7s+N X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f184cbfa-52b3-4d89-5ed6-08dbf1412a6b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.2211 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6f71zxWNLJgkgz6I6UQT2udJEyUgiiFHt2tncVABgwqBz9pvFR9sJ/GUov3TVaZL X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 virtio supports a single iommu instance with multiple ids. It has a combined ACPI (via the VIOT table) and OF probe path, add iommu_viot_get_single_iommu() to respresent this. It already has a per-instance structure, extend it with the ids[] array and use iommu_fw_alloc_per_device_ids() to populate it. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using he per-device data and remove all use of fwspec. Signed-off-by: Jason Gunthorpe --- drivers/iommu/virtio-iommu.c | 67 +++++++++++++----------------------- 1 file changed, 23 insertions(+), 44 deletions(-) diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index b1a7b14a6c7a2f..767919bf848999 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -77,6 +77,8 @@ struct viommu_endpoint { struct viommu_dev *viommu; struct viommu_domain *vdomain; struct list_head resv_regions; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; struct viommu_request { @@ -510,19 +512,16 @@ static int viommu_add_resv_mem(struct viommu_endpoint *vdev, return 0; } -static int viommu_probe_endpoint(struct viommu_dev *viommu, struct device *dev) +static int viommu_probe_endpoint(struct viommu_endpoint *vdev) { int ret; u16 type, len; size_t cur = 0; size_t probe_len; + struct device *dev = vdev->dev; struct virtio_iommu_req_probe *probe; struct virtio_iommu_probe_property *prop; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); - - if (!fwspec->num_ids) - return -EINVAL; + struct viommu_dev *viommu = vdev->viommu; probe_len = sizeof(*probe) + viommu->probe_size + sizeof(struct virtio_iommu_req_tail); @@ -535,7 +534,7 @@ static int viommu_probe_endpoint(struct viommu_dev *viommu, struct device *dev) * For now, assume that properties of an endpoint that outputs multiple * IDs are consistent. Only probe the first one. */ - probe->endpoint = cpu_to_le32(fwspec->ids[0]); + probe->endpoint = cpu_to_le32(vdev->ids[0]); ret = viommu_send_req_sync(viommu, probe, probe_len); if (ret) @@ -721,7 +720,6 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) int i; int ret = 0; struct virtio_iommu_req_attach req; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); struct viommu_domain *vdomain = to_viommu_domain(domain); @@ -763,8 +761,8 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) if (vdomain->bypass) req.flags |= cpu_to_le32(VIRTIO_IOMMU_ATTACH_F_BYPASS); - for (i = 0; i < fwspec->num_ids; i++) { - req.endpoint = cpu_to_le32(fwspec->ids[i]); + for (i = 0; i < vdev->num_ids; i++) { + req.endpoint = cpu_to_le32(vdev->ids[i]); ret = viommu_send_req_sync(vdomain->viommu, &req, sizeof(req)); if (ret) @@ -792,7 +790,6 @@ static void viommu_detach_dev(struct viommu_endpoint *vdev) int i; struct virtio_iommu_req_detach req; struct viommu_domain *vdomain = vdev->vdomain; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(vdev->dev); if (!vdomain) return; @@ -802,8 +799,8 @@ static void viommu_detach_dev(struct viommu_endpoint *vdev) .domain = cpu_to_le32(vdomain->id), }; - for (i = 0; i < fwspec->num_ids; i++) { - req.endpoint = cpu_to_le32(fwspec->ids[i]); + for (i = 0; i < vdev->num_ids; i++) { + req.endpoint = cpu_to_le32(vdev->ids[i]); WARN_ON(viommu_send_req_sync(vdev->viommu, &req, sizeof(req))); } vdomain->nr_endpoints--; @@ -974,34 +971,21 @@ static void viommu_get_resv_regions(struct device *dev, struct list_head *head) static struct iommu_ops viommu_ops; static struct virtio_driver virtio_iommu_drv; -static int viommu_match_node(struct device *dev, const void *data) -{ - return device_match_fwnode(dev->parent, data); -} - -static struct viommu_dev *viommu_get_by_fwnode(struct fwnode_handle *fwnode) -{ - struct device *dev = driver_find_device(&virtio_iommu_drv.driver, NULL, - fwnode, viommu_match_node); - put_device(dev); - - return dev ? dev_to_virtio(dev)->priv : NULL; -} - -static struct iommu_device *viommu_probe_device(struct device *dev) +static struct iommu_device *viommu_probe_device(struct iommu_probe_info *pinf) { int ret; + struct viommu_dev *viommu; struct viommu_endpoint *vdev; - struct viommu_dev *viommu = NULL; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct device *dev = pinf->dev; - viommu = viommu_get_by_fwnode(fwspec->iommu_fwnode); - if (!viommu) - return ERR_PTR(-ENODEV); + viommu = iommu_viot_get_single_iommu(pinf, &viommu_ops, + struct viommu_dev, iommu); + if (IS_ERR(viommu)) + return ERR_CAST(viommu); - vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); - if (!vdev) - return ERR_PTR(-ENOMEM); + vdev = iommu_fw_alloc_per_device_ids(pinf, vdev); + if (IS_ERR(vdev)) + return ERR_CAST(vdev); vdev->dev = dev; vdev->viommu = viommu; @@ -1010,7 +994,7 @@ static struct iommu_device *viommu_probe_device(struct device *dev) if (viommu->probe_size) { /* Get additional information for this endpoint */ - ret = viommu_probe_endpoint(viommu, dev); + ret = viommu_probe_endpoint(vdev); if (ret) goto err_free_dev; } @@ -1050,11 +1034,6 @@ static struct iommu_group *viommu_device_group(struct device *dev) return generic_device_group(dev); } -static int viommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static bool viommu_capable(struct device *dev, enum iommu_cap cap) { switch (cap) { @@ -1070,12 +1049,12 @@ static bool viommu_capable(struct device *dev, enum iommu_cap cap) static struct iommu_ops viommu_ops = { .capable = viommu_capable, .domain_alloc = viommu_domain_alloc, - .probe_device = viommu_probe_device, + .probe_device_pinf = viommu_probe_device, .probe_finalize = viommu_probe_finalize, .release_device = viommu_release_device, .device_group = viommu_device_group, .get_resv_regions = viommu_get_resv_regions, - .of_xlate = viommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = viommu_attach_dev, From patchwork Thu Nov 30 01:10:32 2023 Content-Type: text/plain; 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R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. 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The ACPI IORT table can return a flags value to indicate IOMMU_FWSPEC_PCI_RC_ATS, return this through an output flags pointer. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 3 +- drivers/acpi/scan.c | 1 + drivers/iommu/Makefile | 1 + drivers/iommu/iommu.c | 3 ++ drivers/iommu/iort_iommu.c | 98 ++++++++++++++++++++++++++++++++++++ include/linux/acpi_iort.h | 1 + include/linux/iommu-driver.h | 41 +++++++++++++++ 7 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 drivers/iommu/iort_iommu.c diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 798c0b344f4be8..6b2d50cc9ac180 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -79,8 +79,7 @@ static inline int iort_set_fwnode(struct acpi_iort_node *iort_node, * * Returns: fwnode_handle pointer on success, NULL on failure */ -static inline struct fwnode_handle *iort_get_fwnode( - struct acpi_iort_node *node) +struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node) { struct iort_fwnode *curr; struct fwnode_handle *fwnode = NULL; diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9ec01196573b6e..eb7406cdc9a464 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1571,6 +1571,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) struct iommu_probe_info pinf = { .dev = dev, .is_dma_configure = true, + .acpi_map_id = id_in, .is_acpi = true, }; diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 9c35b106cecb2e..ebf6c151a97746 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o obj-$(CONFIG_IOMMU_IO_PGTABLE_DART) += io-pgtable-dart.o obj-$(CONFIG_IOMMU_IOVA) += iova.o obj-$(CONFIG_OF_IOMMU) += of_iommu.o +obj-$(CONFIG_ACPI_IORT) += iort_iommu.o obj-$(CONFIG_ACPI_VIOT) += viot_iommu.o obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index caf14a53ed1952..7468a64778931b 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3030,6 +3030,9 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, if (!pinf->num_ids) pinf->cached_single_iommu = true; + if (pinf->is_acpi) + pinf->acpi_fwnode = fwnode; + if (!iommu || iommu->fwnode != fwnode) { iommu = iommu_device_from_fwnode(fwnode); if (!iommu) diff --git a/drivers/iommu/iort_iommu.c b/drivers/iommu/iort_iommu.c new file mode 100644 index 00000000000000..9a997b0fd5d5f1 --- /dev/null +++ b/drivers/iommu/iort_iommu.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include + +#include +#include + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + u32 *ids; +}; + +static bool iort_iommu_driver_enabled(struct iommu_probe_info *pinf, u8 type) +{ + switch (type) { + case ACPI_IORT_NODE_SMMU_V3: + return IS_ENABLED(CONFIG_ARM_SMMU_V3); + case ACPI_IORT_NODE_SMMU: + return IS_ENABLED(CONFIG_ARM_SMMU); + default: + dev_warn(pinf->dev, + FW_WARN + "IORT node type %u does not describe an SMMU\n", + type); + return false; + } +} + +static int parse_single_iommu(struct acpi_iort_node *iort_iommu, u32 streamid, + void *_info) +{ + struct parse_info *info = _info; + struct iommu_probe_info *pinf = info->pinf; + struct fwnode_handle *fwnode; + struct iommu_device *iommu; + + fwnode = iort_get_fwnode(iort_iommu); + if (!fwnode) + return -ENODEV; + + iommu = iommu_device_from_fwnode_pinf(pinf, info->ops, fwnode); + if (IS_ERR(iommu)) { + if (iommu == ERR_PTR(-EPROBE_DEFER) && + !iort_iommu_driver_enabled(pinf, iort_iommu->type)) + return -ENODEV; + return PTR_ERR(iommu); + } + iommu_fw_cache_id(pinf, streamid); + return 0; +} + +static int parse_read_ids(struct acpi_iort_node *iommu, u32 streamid, + void *_info) +{ + struct parse_info *info = _info; + + *info->ids = streamid; + (*info->ids)++; + return 0; +} + +static int iort_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) +{ + struct parse_info info = { .pinf = pinf, .ids = ids }; + struct iort_params params; + + return iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, ¶ms, + parse_read_ids, &info); +} + +struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params) +{ + struct parse_info info = { .pinf = pinf, .ops = ops }; + struct iort_params unused_params; + int err; + + if (!pinf->is_dma_configure || !pinf->is_acpi) + return ERR_PTR(-ENODEV); + + if (!params) + params = &unused_params; + + iommu_fw_clear_cache(pinf); + err = iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, params, + parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + pinf->get_u32_ids = iort_get_u32_ids; + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL(__iommu_iort_get_single_iommu); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 13f0cefb930693..bacba2a76c3acb 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -40,6 +40,7 @@ typedef int (*iort_for_each_fn)(struct acpi_iort_node *iommu, u32 streamid, int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, struct iort_params *params, iort_for_each_fn fn, void *info); +struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node); #ifdef CONFIG_ACPI_IORT u32 iort_msi_map_id(struct device *dev, u32 id); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index ce0ba1f35bb5dc..c4e133cdef2c78 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -19,6 +19,7 @@ struct of_phandle_args; struct fwnode_handle; struct iommu_device; +struct iort_params; struct iommu_ops; /* @@ -39,7 +40,9 @@ struct iommu_probe_info { struct list_head *deferred_group_list; struct iommu_device *cached_iommu; struct device_node *of_master_np; + struct fwnode_handle *acpi_fwnode; const u32 *of_map_id; + const u32 *acpi_map_id; int (*get_u32_ids)(struct iommu_probe_info *pinf, u32 *ids); unsigned int num_ids; u32 cached_ids[8]; @@ -63,6 +66,21 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, struct fwnode_handle *fwnode); struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); +/** + * iommu_fw_acpi_fwnode - Get an ACPI fwnode_handle + * @pinf: The iommu_probe_info + * + * Return the ACPI version of the fwnode describing the iommu data that is + * associated with the device being probed. + */ +static inline struct fwnode_handle * +iommu_fw_acpi_fwnode(struct iommu_probe_info *pinf) +{ + if (!pinf->is_acpi) + return NULL; + return pinf->acpi_fwnode; +} + typedef int (*iommu_of_xlate_fn)(struct iommu_device *iommu, struct of_phandle_args *args, void *priv); void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf); @@ -213,4 +231,27 @@ __iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, __iommu_of_get_single_iommu(pinf, ops, -1)), \ drv_struct, member) +#if IS_ENABLED(CONFIG_ACPI_IORT) +struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params); +#else +static inline struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params) +{ + return ERR_PTR(-ENODEV); +} +#endif +#define iommu_iort_get_single_iommu(pinf, ops, params, drv_struct, member) \ + ({ \ + memset(params, 0, sizeof(*(params))); \ + container_of_err(__iommu_first(__iommu_iort_get_single_iommu( \ + pinf, ops, params), \ + __iommu_of_get_single_iommu( \ + pinf, ops, -1)), \ + drv_struct, member) \ + }) #endif From patchwork Thu Nov 30 01:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748560 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CN8+7BV7" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D415B10CB; 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R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 26/30] iommu/arm-smmu-v3: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:33 -0400 Message-ID: <26-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0001.namprd08.prod.outlook.com (2603:10b6:805:66::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 72d5ace2-3b95-4d23-87a1-08dbf1412b2c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 92Xkiy7Ge3EyyeZMq1jHCmrHDof2nfgXnt5krfuyp9sXi5zeS2ZGZyMrV6BODuhKVOxL/AUCDG8k3aP3Q9diTte8jlkNdoNTiQaEQAg1uA5/BzT0l4TrCaV2MkMLSU5bCsDB3Oz8BtjmiY6ToeQJtpjT+YOTO8FW5SnVCUg615BnKNDZBoHvhUF70D5L93CnxfzK1mnAChT1KjyqQHJU6NcloZjQNdI7Zz4W0B6BOIVpK1VVt1sbObC38NKWcahueEozbssTYBNci7B9u0RjxjitSPIxiCypxWTKgNHQJSZ8g70qh2AJn0dWjHpbYzOQJWqk/SRx3BnT3IIixzAHsTKifAShMiXY3nxFT6OicBPkwv38/2jIw+bGZk8Gh8VoPAqa6THx13y9KP3GxVM1Y9Dzqze7kBxN80YpqcT8BOyx+Zq8qhtokRrwuA3Aicz37U2/uMHmqCG06Bj6MqP6JneUuURaUCXBcgVIQgT382RsNifCMTixt+yuCDzwva11J4DFikqxx+pKbo+NeC63iCeUxnJqJuIIP1NwvYUrE62z7QC6kmrU9w5uW1T9PtpUlB+ziRAnilzZrRb9nGhDzmmT3Ck7P9yNIGYCZ4mzrKsLw+3/BnpZzV8gNfejkPvWw1c2yn5WpHJRazxA+uqL6g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sJvPkKnT8OSWWSISjBxvPyOFfkzFZcWpoixVo4xEwL74hOkh8fL0JxMduSr+AvWSIcipMikb42ZUgKnGDZvvDZBR+Ugsinx8GGDY1LACAoRCpOBYFipKMSXv8r+ZfjVFEk9IvOIZkInwyBBzRQdPs2onnnLRZQT/6aKmLbdXmqgcGXfjlLsTeC2DDVCebf0nRYY0/5fOZME9YxM7I9YZ0xF7+GQ1rPAD4qJuNCfB5wOm3UY74IUQM0Ss1ftMB/8gtpp0dShVgtv3X7p1zQ82a7/2EC8Rz+QQKQfZXAPvUdHz9FAUKJcmIqwyl4b8jNMVLrWFlGxVw+ZDe1pc22HAQ34Uk+mgYPwMeOUEDXEeJqBitoe4N6XDnw1vLSSwbCD+x1XHy4ufGmay8me0gD9x0tdtTicRP6AbVpW7Bd/dFCp2eAS2bjcRiw0OM3I7iY6AK0BbPZ9EuepRBZ9thCy7nHwLm3fCgmQpv1xdAgSU9BbsYQJcUr/sp6QD9j6i1y3LRPZl/PomMsl0NI1XjW7b2qg3voR5Ki22pcY1owZHkJrNfc9u+np6svDjw3Q91BDyh1Sc2RLIcVlL0tKDv+n/TKgy9NN6sGHU5G6SphvazGn0udlfpgyK5ZIMjVe6O3J0mXsBGX3SZeIMDQYoVkDYNN9c2NW67dq0nbq9eKguBuLaB0F7rK2OZ36WCqTNBxbvCqTRSZpDlQ56XBPAB4zsAthR20n9c2ReguPEYgRNJduX94s5PQMF1aECpAPafZhDZYDjh0rnU6l8h6J7Lqa1H6hCVYSZDVYCDxWEz8LRBFq1nBHPDbtZhWcgpBthIAd/6isoxsBxOknvJjkgDZ3MTbf2ZJn8v/Ipos9ft6k3Z6V29yM8BL0tshhVfkuR0lKC4bOAcNXIKMa1j3rJCyogOZFSNrf3QSZ+/3iZoP6e6VMQpH9BYU7cGnfmP6qW6loNphSG78algA7ncihi95VlKwU7WAAgYQoqkwIS/3d2S3V72fDYtYlX6nMaSHvKZYEZewHnHv4Qw4PKom31Hoz8qQ7zkUoKCd2vZ4F4aZMsfu3p7iFgvRKzRJHF+J7NT1bIqH/222/Nb8UPJ5WnVsrvPszLPtjlSE3e4MHjgSy9uMRsNCIYnhitK70li3C5oqKkgDqlkT6J/MfTRbGfP5hEcCCQR8l13bY+BeQAEEjZ/dM46feMtnYIB3gCheDHlG8/yfYFgGpGxMFqdyCGs+hM2xNjqg9xRkllCTfj80tiSxMCpwIWYsBGQ/6PpXWUS2IK+BALXA6UQNjwSW/WA/lygxzosVeSssxImkZkxWhVdwrd12tS7R6pZHPVu03PT8q9EiVs/eknw/dhTVGTTjT9A04bgz2y24RL2wUXn1KLhmR1IuKdpwA12E7Ap0hcGp+PXF8i1YMEn7HKD3Oj2nvEWWyIT+E1Khqv3DcmFox6rEwkPNbD0vEJZOD0ErHHKRK+eaXaRmOBEEZ6tYddrs4MRiH/LKQseXA6ogAstefjZux1ay4QWGam54uLgwmZvY/HB33OtAYFNtsZQ2cyJYtIs52nAGmxvsK3I4R+3jWYCkZW8Hi5JEYo2ROcy0q89VgK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72d5ace2-3b95-4d23-87a1-08dbf1412b2c X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.4864 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4t7oHSiKphoopW92I1Rm+6YwRFEu5JL6Inb7Ybt6vg/SK6SPNORu2XecHKqXHdbE X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 SMMUv3 supports a single iommu instance with multiple ids. It has a combined ACPI (via the IORT table) and OF probe path, add iommu_iort_get_single_iommu() to respresent this. It already has a per-instance structure, extend it with the ids[] array and use iommu_fwb_alloc_per_device_ids() to populate it. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Directly call iort_iommu_get_resv_regions() and pass in the internal id array instead of getting it from the fwspec. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 2 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++ include/linux/iommu-driver.h | 2 +- 4 files changed, 35 insertions(+), 47 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 6b2d50cc9ac180..acd2e48590f37a 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1297,8 +1297,6 @@ static void iort_named_component_init(struct device *dev, props[0] = PROPERTY_ENTRY_U32("pasid-num-bits", FIELD_GET(ACPI_IORT_NC_PASID_BITS, nc->node_flags)); - if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED) - props[1] = PROPERTY_ENTRY_BOOL("dma-can-stall"); if (device_create_managed_software_node(dev, props, NULL)) dev_warn(dev, "Could not add device properties\n"); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1855d3892b15f8..1a43c677e2feaf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,9 +26,9 @@ #include #include #include +#include #include "arm-smmu-v3.h" -#include "../../dma-iommu.h" #include "../../iommu-sva.h" static bool disable_bypass = true; @@ -2255,12 +2255,11 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master) { struct device *dev = master->dev; struct arm_smmu_device *smmu = master->smmu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); if (!(smmu->features & ARM_SMMU_FEAT_ATS)) return false; - if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) + if (!master->pci_rc_ats) return false; return dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev)); @@ -2382,14 +2381,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { int ret = 0; unsigned long flags; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_master *master; - if (!fwspec) - return -ENOENT; - master = dev_iommu_priv_get(dev); smmu = master->smmu; @@ -2529,15 +2524,6 @@ arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) static struct platform_driver arm_smmu_driver; -static -struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode) -{ - struct device *dev = driver_find_device_by_fwnode(&arm_smmu_driver.driver, - fwnode); - put_device(dev); - return dev ? dev_get_drvdata(dev) : NULL; -} - static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) { unsigned long limit = smmu->strtab_cfg.num_l1_ents; @@ -2568,17 +2554,16 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, int ret = 0; struct arm_smmu_stream *new_stream, *cur_stream; struct rb_node **new_node, *parent_node = NULL; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); - master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), + master->streams = kcalloc(master->num_ids, sizeof(*master->streams), GFP_KERNEL); if (!master->streams) return -ENOMEM; - master->num_streams = fwspec->num_ids; + master->num_streams = master->num_ids; mutex_lock(&smmu->streams_mutex); - for (i = 0; i < fwspec->num_ids; i++) { - u32 sid = fwspec->ids[i]; + for (i = 0; i < master->num_ids; i++) { + u32 sid = master->ids[i]; new_stream = &master->streams[i]; new_stream->id = sid; @@ -2627,13 +2612,12 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) { int i; struct arm_smmu_device *smmu = master->smmu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); if (!smmu || !master->streams) return; mutex_lock(&smmu->streams_mutex); - for (i = 0; i < fwspec->num_ids; i++) + for (i = 0; i < master->num_ids; i++) rb_erase(&master->streams[i].node, &smmu->streams); mutex_unlock(&smmu->streams_mutex); @@ -2642,26 +2626,27 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) static struct iommu_ops arm_smmu_ops; -static struct iommu_device *arm_smmu_probe_device(struct device *dev) +static struct iommu_device *arm_smmu_probe_device(struct iommu_probe_info *pinf) { int ret; + struct device *dev = pinf->dev; struct arm_smmu_device *smmu; struct arm_smmu_master *master; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iort_params params; - if (WARN_ON_ONCE(dev_iommu_priv_get(dev))) - return ERR_PTR(-EBUSY); + smmu = iommu_iort_get_single_iommu(pinf, &arm_smmu_ops, ¶ms, + struct arm_smmu_device, iommu); + if (IS_ERR(smmu)) + return ERR_CAST(smmu); - smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - if (!smmu) - return ERR_PTR(-ENODEV); - - master = kzalloc(sizeof(*master), GFP_KERNEL); - if (!master) - return ERR_PTR(-ENOMEM); + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); master->dev = dev; master->smmu = smmu; + master->pci_rc_ats = params.pci_rc_ats; + master->acpi_fwnode = iommu_fw_acpi_fwnode(pinf); INIT_LIST_HEAD(&master->bonds); dev_iommu_priv_set(dev, master); @@ -2670,7 +2655,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) goto err_free_master; device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); - master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); + master->ssid_bits = min(smmu->ssid_bits, + max(params.pasid_num_bits, master->ssid_bits)); /* * Note that PASID must be enabled before, and disabled after ATS: @@ -2687,7 +2673,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) CTXDESC_LINEAR_CDMAX); if ((smmu->features & ARM_SMMU_FEAT_STALLS && - device_property_read_bool(dev, "dma-can-stall")) || + (device_property_read_bool(dev, "dma-can-stall") || + params.dma_can_stall)) || smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled = true; @@ -2744,14 +2731,10 @@ static int arm_smmu_enable_nesting(struct iommu_domain *domain) return ret; } -static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { + struct arm_smmu_master *master = dev_iommu_priv_get(dev); struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; @@ -2762,7 +2745,10 @@ static void arm_smmu_get_resv_regions(struct device *dev, list_add_tail(®ion->list, head); - iommu_dma_get_resv_regions(dev, head); + if (master->acpi_fwnode) + iort_iommu_get_resv_regions(dev, head, master->acpi_fwnode, + master->ids, master->num_ids); + of_iommu_get_resv_regions(dev, head); } static int arm_smmu_dev_enable_feature(struct device *dev, @@ -2851,10 +2837,10 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, - .probe_device = arm_smmu_probe_device, + .probe_device_pinf = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .of_xlate = arm_smmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .remove_dev_pasid = arm_smmu_remove_dev_pasid, .dev_enable_feat = arm_smmu_dev_enable_feature, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 961205ba86d25d..ac293265b21a13 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -692,6 +692,7 @@ struct arm_smmu_stream { struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; + struct fwnode_handle *acpi_fwnode; struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; @@ -702,8 +703,11 @@ struct arm_smmu_master { bool stall_enabled; bool sva_enabled; bool iopf_enabled; + bool pci_rc_ats; struct list_head bonds; unsigned int ssid_bits; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; /* SMMU private data for an IOMMU domain */ diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index c4e133cdef2c78..8f7089d3bb7135 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -252,6 +252,6 @@ __iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, pinf, ops, params), \ __iommu_of_get_single_iommu( \ pinf, ops, -1)), \ - drv_struct, member) \ + drv_struct, member); \ }) #endif From patchwork Thu Nov 30 01:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 748550 Authentication-Results: smtp.subspace.kernel.org; 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Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DM6PR12MB4484.namprd12.prod.outlook.com (2603:10b6:5:28f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.23; Thu, 30 Nov 2023 01:11:26 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:11:26 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 28/30] iommu: Call all drivers if there is no fwspec Date: Wed, 29 Nov 2023 21:10:35 -0400 Message-ID: <28-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR13CA0030.namprd13.prod.outlook.com (2603:10b6:806:130::35) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DM6PR12MB4484:EE_ X-MS-Office365-Filtering-Correlation-Id: f67500fe-40c5-4676-d4a3-08dbf1412d51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kU3T7H5J57NLM9QajWOnU7z7Xu9y794iVNtOqReqjjMT9Tu3yv2lFF8WAgFzrOqUWvpglv1Igb3RhXi2xM94Vmx3ebqu31En5zdMgZdN2j6yCnaFCTlapBrEjZ07EFM02cLu5UlvXpr0O2YLeKQqySJlZPiFsZy6iPky8VAIaywxdG4vGtMxVL6Up4OzMueg6OGciJxgdCDn7Jbcn0ZUqHn3K1ym+q5+8vyrxsqmsFB1GWogzupFWDt4RGofVfAoS2bMJ9h+j/OlqIOZ0CcUv709vKKkqEIsu00l4IOoZmX6C5Zd3noH4KZSQ5tAfdJXpP5uiZBR3eX8cVBF0HAQCyY3Erel1ZQ0UzCBMLqd27W+pQvoKQ4CqvObpWlzzj3xtlt+jxiLwH+ZKkGyOeg7Gmnb018jPv6bkNLgPvGyE48yby4y2X43+C/mhKh9gib9m26cHq4bcioT+oSPmn90EvCigfgVy+3RpxEkuZ+9Er4LN91nrNVkLndQxMeBUneW/bnjVEPaAklk5VZZgViEQtZAqC6+wAKPyfQRp7dGgdwKpe0gAQSfo5tdmEBQE8GmA3Plk89UnM/zCCZBQgJoIkEAHk2ynbKiPI2fFEEsp6gsEOnFprXEbm5h9DHRPEffpcudc1+f/Lwiy5bAvwmgww== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:LV2PR12MB5869.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(376002)(366004)(396003)(136003)(346002)(39860400002)(230922051799003)(1800799012)(451199024)(186009)(64100799003)(83380400001)(1191002)(2616005)(26005)(921008)(66476007)(66946007)(66556008)(7406005)(7366002)(7416002)(110136005)(2906002)(8676002)(4326008)(8936002)(86362001)(5660300002)(41300700001)(6506007)(6666004)(6512007)(36756003)(316002)(478600001)(6486002)(202311291699003)(38100700002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r3OsdJrBhVIA+ZSfZKD6MQxElvohXeb8xslb73RAKupEeYHmd/CydVrE2+CYUsrVOF42DMuBW55zsqBMyZfs3OztqOw7he9GYAcFZWzjCohoE9tKzYE2FqeWvjKPp6Nf2one0OYjZOr82gRrisxHrTSr9Wz8H6jRtEcoLRAqoQw45RzZytR6L/qzh1ORcI0wqFwIdJX170WWoyymABvPtUsxx8ndY47CWtF9PDXc7JsI2VQnMXPI+t7gfrNqy/b/junKEaltSde2B4oFoN+RLhhF75uEn07pd7Z2coRkUxMd8jtnKfuJ+EmzimuXyl43yk4NgZdNRJIxG5ftLTVndNOGZYDDgoSiLn0KVlaBbXH09SRjC8ktap8vOUrigULSwYkkQLkmFxNjTLO5phGmL302qpMNCuChIQoRiB6fx6oSWImvMPRe38EFmoG1DBXN3S/EMjEmFAmabNOoACaTVUEbFxJs3nsxK/o3M10UhlzCmkgMnapIZOgKG0YulADBN7a0hkP4/0uEqTS9ff8WxMJSqgpZGmWZMxlKu48TmxDe3lzvm6ZoUZAP+s+0afKgfKaC2BO01jB2pHrIqt5paOVUcNLy/8GlmNsrgU3gST+fu1wP99Q4vsfs27xb/8hc8vKkQQTebLIKmy6YuOyp0LWchuAsiIlCQ+ARMHJFND8/JjyoRIJCFzZCT5uVScLUPEAknF1G36sveW68SYquR4aFSMqgGmustnm46nElOaMsD9JxKApJmpCuOyePfWsC1H6HBA5kiGxDl+lSMhX36/lQO2hosmef4wv+g9eMH9WhInszOlcyv0kzlYohlobDGDn5g+3is3cpXZkmmdDjetyzZRH0jo+IInH+0CFZu5hnr70BgM1FomN4k4bxk72unbpxu8US3TckRuZSna1CnHOL8/u69s+zlUY34gWeOi/JKrgKmj9rR9C6qKaqrh81YNmpmk0t2S5nHsrUtHQvU/k30worvyMFLRgJIwKjV7S9jLDijlBR/meGUe0szE35nLA2KoFlQ2w7+rNGUKEd0nlUGYU3CVqHoRjtyaXBWFBSotVufp0RNMip3TqoAzkCGfHDkl6Lj2Bn2xmbsA/+etx8sGi+KYVwdOQXrJV+8+Fe+LuRLLZMdFIfS3Y7iVfYro+LjMjuudXkHKzTvz3ZmR1F7diUEGIsn0whZHpx928lNtBv/o2F0ZXzp+bwI2VEpyrVMdViYLe9JmUzwJeCr5c6RMN4AQFWEtqRRGYZPE9U6sTbxhAns2JwdjZEcW/AvwN7TkVInvdsF7ipvMh4W1WEMOcdJ57rbCqqZAb4ZzKkwVo2nSC5h/Wycs/x4NtJddua7xgmfLB/mdUALnjhVLTkop+qUyI88cUBF3xg2/6N0TbLQvfNtw0tl8p8OXQAHQJG9PzP4wygd2/lUT1RTkFxY/4hzYv1MsbtpUn9s8N/txi65RSuNHz92nwSkUxFZX0DtV2L8vYXWKP7qFP9GDkgieHeUG6FnvNnLSCgIDdL4W7N4/sHJn53Z8AX9avvGuRSJuKR8PK1kVhI9ts7sIUmI716MAo0H1am2tjWz5DvuvRKDkLJNmFhmWnXwUhd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f67500fe-40c5-4676-d4a3-08dbf1412d51 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:43.9426 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TEOSbs4TX0OsynOw7k+u1QMSzSAFEHuPp5BjKVlPQuf9rZ/slvmuhCDeEsWEh4zy X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4484 Now all the iommu drivers can self probe by checking the struct device to see if it has an appropriate FW attached to it. We don't need the concept of "global" drivers with a NULL fwspec, just invoke all the ops. Real systems only have one ops, so this effectively invokes the single op in the system to probe each device. If there are multiple ops we invoke each one once, and drivers that don't understand the struct device should return -ENODEV. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 59 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 7468a64778931b..54e3f14429b3b4 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -241,6 +241,26 @@ static int remove_iommu_group(struct device *dev, void *data) return 0; } +static void iommu_device_add(struct iommu_device *iommu) +{ + struct iommu_device *cur; + + /* + * Keep the iommu_device_list grouped by ops so that + * iommu_find_init_device() works efficiently. + */ + mutex_lock(&iommu_probe_device_lock); + list_for_each_entry(cur, &iommu_device_list, list) { + if (cur->ops == iommu->ops) { + list_add(&iommu->list, &cur->list); + goto out; + } + } + list_add(&iommu->list, &iommu_device_list); +out: + mutex_unlock(&iommu_probe_device_lock); +} + /** * iommu_device_register() - Register an IOMMU hardware instance * @iommu: IOMMU handle for the instance @@ -262,9 +282,7 @@ int iommu_device_register(struct iommu_device *iommu, if (hwdev) iommu->fwnode = dev_fwnode(hwdev); - mutex_lock(&iommu_probe_device_lock); - list_add_tail(&iommu->list, &iommu_device_list); - mutex_unlock(&iommu_probe_device_lock); + iommu_device_add(iommu); for (int i = 0; i < ARRAY_SIZE(iommu_buses) && !err; i++) err = bus_iommu_probe(iommu_buses[i]); @@ -502,6 +520,29 @@ static void iommu_deinit_device(struct device *dev) DEFINE_MUTEX(iommu_probe_device_lock); +static int iommu_find_init_device(struct iommu_probe_info *pinf) +{ + const struct iommu_ops *ops = NULL; + struct iommu_device *iommu; + int ret; + + lockdep_assert_held(&iommu_probe_device_lock); + + /* + * Each unique ops gets a chance to claim the device, -ENODEV means the + * driver does not support the device. + */ + list_for_each_entry(iommu, &iommu_device_list, list) { + if (iommu->ops != ops) { + ops = iommu->ops; + ret = iommu_init_device(pinf, iommu->ops); + if (ret != -ENODEV) + return ret; + } + } + return -ENODEV; +} + static int __iommu_probe_device(struct iommu_probe_info *pinf) { struct device *dev = pinf->dev; @@ -524,13 +565,6 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) ops = fwspec->ops; if (!ops) return -ENODEV; - } else { - struct iommu_device *iommu; - - iommu = iommu_device_from_fwnode(NULL); - if (!iommu) - return -ENODEV; - ops = iommu->ops; } /* @@ -546,7 +580,10 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) if (dev->iommu_group) return 0; - ret = iommu_init_device(pinf, ops); + if (ops) + ret = iommu_init_device(pinf, ops); + else + ret = iommu_find_init_device(pinf); if (ret) return ret;