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[176.184.17.116]) by smtp.gmail.com with ESMTPSA id d9-20020a05600c34c900b0040b2c195523sm6888542wmq.31.2023.11.30.12.32.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Nov 2023 12:32:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Max Filippov , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.0] accel/tcg: Remove unused tb_invalidate_phys_addr() Date: Thu, 30 Nov 2023 21:32:40 +0100 Message-ID: <20231130203241.31099-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit e3f7c801f1 introduced the TCGCPUOps::debug_check_breakpoint() handler, and commit 10c37828b2 "moved breakpoint recognition outside of translation", so "we no longer need to flush any TBs when changing BPs". The last target using tb_invalidate_phys_addr() was converted to the debug_check_breakpoint(), so this function is now unused. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Based-on: <20231130171920.3798954-1-jcmvbkbc@gmail.com> --- include/exec/exec-all.h | 5 ----- cpu-target.c | 29 ----------------------------- 2 files changed, 34 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ee90ef122b..df3d93a2e2 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -518,11 +518,6 @@ static inline void tb_set_page_addr1(TranslationBlock *tb, uint32_t curr_cflags(CPUState *cpu); /* TranslationBlock invalidate API */ -#if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(hwaddr addr); -#else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); -#endif void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); diff --git a/cpu-target.c b/cpu-target.c index 508013e23d..997ca2e846 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -276,35 +276,6 @@ void list_cpus(void) #endif } -#if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(hwaddr addr) -{ - mmap_lock(); - tb_invalidate_phys_page(addr); - mmap_unlock(); -} -#else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) -{ - ram_addr_t ram_addr; - MemoryRegion *mr; - hwaddr l = 1; - - if (!tcg_enabled()) { - return; - } - - RCU_READ_LOCK_GUARD(); - mr = address_space_translate(as, addr, &addr, &l, false, attrs); - if (!(memory_region_is_ram(mr) - || memory_region_is_romd(mr))) { - return; - } - ram_addr = memory_region_get_ram_addr(mr) + addr; - tb_invalidate_phys_page(ram_addr); -} -#endif - /* enable or disable single step mode. EXCP_DEBUG is returned by the CPU loop after each instruction */ void cpu_single_step(CPUState *cpu, int enabled)