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[176.184.17.116]) by smtp.gmail.com with ESMTPSA id h13-20020aa7c60d000000b0053e5f67d637sm586275edq.9.2023.11.30.06.25.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Nov 2023 06:25:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.0 1/3] target/arm: Restrict TCG specific helpers Date: Thu, 30 Nov 2023 15:25:17 +0100 Message-ID: <20231130142519.28417-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231130142519.28417-1-philmd@linaro.org> References: <20231130142519.28417-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 55 -------------------------------------- target/arm/tcg/op_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 55 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2746d3fdac..4844cf1d78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10135,61 +10135,6 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, } } -/* Sign/zero extend */ -uint32_t HELPER(sxtb16)(uint32_t x) -{ - uint32_t res; - res = (uint16_t)(int8_t)x; - res |= (uint32_t)(int8_t)(x >> 16) << 16; - return res; -} - -static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) -{ - /* - * Take a division-by-zero exception if necessary; otherwise return - * to get the usual non-trapping division behaviour (result of 0) - */ - if (arm_feature(env, ARM_FEATURE_M) - && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { - raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); - } -} - -uint32_t HELPER(uxtb16)(uint32_t x) -{ - uint32_t res; - res = (uint16_t)(uint8_t)x; - res |= (uint32_t)(uint8_t)(x >> 16) << 16; - return res; -} - -int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) -{ - if (den == 0) { - handle_possible_div0_trap(env, GETPC()); - return 0; - } - if (num == INT_MIN && den == -1) { - return INT_MIN; - } - return num / den; -} - -uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) -{ - if (den == 0) { - handle_possible_div0_trap(env, GETPC()); - return 0; - } - return num / den; -} - -uint32_t HELPER(rbit)(uint32_t x) -{ - return revbit32(x); -} - #ifdef CONFIG_USER_ONLY static void switch_mode(CPUARMState *env, int mode) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index ea08936a85..9de0fa2d1f 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -121,6 +121,61 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) } } +/* Sign/zero extend */ +uint32_t HELPER(sxtb16)(uint32_t x) +{ + uint32_t res; + res = (uint16_t)(int8_t)x; + res |= (uint32_t)(int8_t)(x >> 16) << 16; + return res; +} + +static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) +{ + /* + * Take a division-by-zero exception if necessary; otherwise return + * to get the usual non-trapping division behaviour (result of 0) + */ + if (arm_feature(env, ARM_FEATURE_M) + && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { + raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); + } +} + +uint32_t HELPER(uxtb16)(uint32_t x) +{ + uint32_t res; + res = (uint16_t)(uint8_t)x; + res |= (uint32_t)(uint8_t)(x >> 16) << 16; + return res; +} + +int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) +{ + if (den == 0) { + handle_possible_div0_trap(env, GETPC()); + return 0; + } + if (num == INT_MIN && den == -1) { + return INT_MIN; + } + return num / den; +} + +uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) +{ + if (den == 0) { + handle_possible_div0_trap(env, GETPC()); + return 0; + } + return num / den; +} + +uint32_t HELPER(rbit)(uint32_t x) +{ + return revbit32(x); +} + uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res = a + b; From patchwork Thu Nov 30 14:25:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 748497 Delivered-To: patch@linaro.org Received: by 2002:adf:e9c2:0:b0:32d:baff:b0ca with SMTP id l2csp909033wrn; Thu, 30 Nov 2023 06:27:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IEIRL8sxgckXBPSim6RD/TY5aYSkog/sepZD8IK3XKmoqr79QlaXIHvQ8T/fcKhkTSPCn4a X-Received: by 2002:a81:9850:0:b0:5d3:a348:b0bc with SMTP id p77-20020a819850000000b005d3a348b0bcmr726485ywg.48.1701354430917; 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[176.184.17.116]) by smtp.gmail.com with ESMTPSA id w8-20020a056402070800b0054aeac2c4b9sm591628edx.81.2023.11.30.06.25.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Nov 2023 06:25:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.0 2/3] target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accel Date: Thu, 30 Nov 2023 15:25:18 +0100 Message-ID: <20231130142519.28417-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231130142519.28417-1-philmd@linaro.org> References: <20231130142519.28417-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hardware accelerators handle that in *hardware*. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4844cf1d78..20e13215bb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7645,6 +7645,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { +#ifdef CONFIG_TCG ARMCPU *cpu = env_archcpu(env); /* CTR_EL0 System register -> DminLine, bits [19:16] */ uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); @@ -7669,6 +7670,10 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, } #endif /*CONFIG_USER_ONLY*/ } +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } static const ARMCPRegInfo dcpop_reg[] = { From patchwork Thu Nov 30 14:25:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 748496 Delivered-To: patch@linaro.org Received: by 2002:adf:e9c2:0:b0:32d:baff:b0ca with SMTP id l2csp909034wrn; Thu, 30 Nov 2023 06:27:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtsh7TSkWEnl+0RdG1FZFWPBNZveaazhk+yaGG5hjSWOwwqRzXIfwgs9p2/BKKr6z/VYAE X-Received: by 2002:a05:6102:198a:b0:464:45b1:a846 with SMTP id jm10-20020a056102198a00b0046445b1a846mr5335766vsb.9.1701354430963; Thu, 30 Nov 2023 06:27:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701354430; cv=none; d=google.com; s=arc-20160816; b=qqTEWnOFY0G/Y3/av7i6UxD6odzpG0iy08ssFlR+fcWtYlAMH8N6QT45sqfasAONk5 knjveNi4ymZUvaza6rq3CY9sBswjOl/9Ovnn891pnPAr0gAPfz6byQrM8sEDNLnpSHtA YJ8tqNdtT79xUB+pFjRwJzGGwFT1QVYIkgpAa29g5uBVEJgYm8TiKaBCEElARzB6+ExL 4PpN2EBEvOEjbPsEqXd/N3Lv0mHF6Pr1ZUob/4ZQHDYJpD8X68sSQ+T3Aia0TcvrjuZ+ 1fc+c+A8a/JQGXBMwHy8vHS8S+RIqwY7C1nUBRUeKDjHwe2uDdpQXzEM08DrmIjRyV3Y Newg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xIkyywCV84pixVtgL1sg5DGw0uU59TDxgCkewEW8ZWA=; fh=DKQFoSm5rvXVk6AUqpSavFv+IR+qPwKdgcCOIx8jJm4=; b=YAxp/4pWntm80mTcr59/6mvIOsIFz04bg3xN98McRYyaMF80mjuR80zjHhM82GJjIX JXOlf4pHAWPJ4XC/ijw+1tXUrHZXi32NsG31b0EVbEvF4Ji+QGuO2LqPgzu/yu4jNPg1 Y01TtCQnzeybht22O/u86Y9tgrKxpKs/W6qoiw9QSkLJF1Snutz0GC/4tA6I+hSuW3mQ z6o+cDGPpg9TjujtxSjsGm4wjZDxk3S6oICKOlXr13DCtG8Emg4Z7qoWExluuorvq3l/ yrUK1fynUw8PogJXBP0I4n1qK1ZiRUWPyuwjCKJ9rgjvW6im3ZSJEGoVb2r75y3sAA/B mxBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x+h5n80j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.17.116]) by smtp.gmail.com with ESMTPSA id n23-20020a170906089700b0099297782aa9sm726356eje.49.2023.11.30.06.25.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Nov 2023 06:25:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.0 3/3] target/arm/tcg: Including missing 'exec/exec-all.h' header Date: Thu, 30 Nov 2023 15:25:19 +0100 Message-ID: <20231130142519.28417-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231130142519.28417-1-philmd@linaro.org> References: <20231130142519.28417-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org translate_insn() ends up calling probe_access_full(), itself declared in "exec/exec-all.h": TranslatorOps::translate_insn -> aarch64_tr_translate_insn() -> is_guarded_page() -> probe_access_full() Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a2e49c39f9..f3b5b9124d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "exec/exec-all.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h"