From patchwork Wed Nov 29 13:39:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 748775 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="PR3NUmXg" Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB964CE for ; Wed, 29 Nov 2023 05:40:32 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2c87acba73bso89284491fa.1 for ; Wed, 29 Nov 2023 05:40:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1701265231; x=1701870031; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dNV0r1tk7i0wstK5L78tpqt0TYtEG6tPq8iOAeVFOuU=; b=PR3NUmXggT3VAc2Q9lPcRj3wE/QB8VSIu04RTsr7v8NVdOQyXdHmj3XKr+BCKDXH7O ZypBSTkOq6toplifydqrYTstPKQRuSY8XTxRCWQVmEpDHXJOB/WagnXap7Qyk/ahrW5m vek7mm4Uzttnu1TH6ULjdVLKmrsgwIgrcOiHVg/3SilJkKvJD/kLrP7Abm0i7NWJ5SAZ vMUpq8av6xu9geJzHgd752LCtqIX1kHysqPa0X6a/HHPH1c4UIGDQRIc38yOVN/Kce94 x/31TOoGWUOW/s/WApBpbAHRmIwnhdNcN751ynhinSP+2OS5U2+CH4YugB/RYnrz7grv qchg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701265231; x=1701870031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dNV0r1tk7i0wstK5L78tpqt0TYtEG6tPq8iOAeVFOuU=; b=ia0qSAN7Zs6QAYmr+39ECkE/diWRKAL1SsWWHL4Wgrm9BbHylVNvFDY68gl14sg/g9 nVIDFnBcyi5cZtvN3GeM168gb1eHOLuvIGkLF2NiLRCK3YNpNsGNAG2+m4rUXrKoF7uS p85i8VFMky49L5MZ13AEP5ISEPolZi3P/HEG48NwaRir1itfFgWPPG5t/ngT+m+A/2sE ElMeJqiIrbpwxWSclhNeQJZgtinoPalrVXxR1GpiTIiKGxEe/6pXOxdun3kjjZgtEY6+ IzdzJHQ2U2HeIWVamyxxoKBNSk0JU//ZaZbneeNK1j4cVUfvtnl6FkS0b+29OynKUGY2 oDBA== X-Gm-Message-State: AOJu0YyqwcRgAiEUmMfLBdULyV1TRySt2Xz/QyEYA6o8doMVZ5PNV4rP IR3ltHMSxgl4BQFyxeHltnn4Cg== X-Google-Smtp-Source: AGHT+IG9Ttru1ruXIsW674i0vE1QI20t43Hug+5XJhyzfmCgdCqgGynOwZI682I9zwA4RbLZ0btt3A== X-Received: by 2002:a05:651c:c85:b0:2c9:9376:1ae7 with SMTP id bz5-20020a05651c0c8500b002c993761ae7mr11736281ljb.28.1701265231148; Wed, 29 Nov 2023 05:40:31 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:6101:5529:fe2d:d7eb]) by smtp.googlemail.com with ESMTPSA id w17-20020a05600c475100b004080f0376a0sm2285860wmo.42.2023.11.29.05.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 05:40:30 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring Subject: [PATCH v3 1/4] dt-bindings: pwm: amlogic: fix s4 bindings Date: Wed, 29 Nov 2023 14:39:57 +0100 Message-ID: <20231129134004.3642121-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231129134004.3642121-1-jbrunet@baylibre.com> References: <20231129134004.3642121-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify s4 has been added to the compatible list while converting the Amlogic PWM binding documentation from txt to yaml. However, on the s4, the clock bindings have different meaning compared to the previous SoCs. On the previous SoCs the clock bindings used to describe which input the PWM channel multiplexer should pick among its possible parents. This is very much tied to the driver implementation, instead of describing the HW for what it is. When support for the Amlogic PWM was first added, how to deal with clocks through DT was not as clear as it nowadays. The Linux driver now ignores this DT setting, but still relies on the hard-coded list of clock sources. On the s4, the input multiplexer is gone. The clock bindings actually describe the clock as it exists, not a setting. The property has a different meaning, even if it is still 2 clocks and it would pass the check when support is actually added. Also the s4 cannot work if the clocks are not provided, so the property no longer optional. Finally, for once it makes sense to see the input as being numbered somehow. No need to bother with clock-names on the s4 type of PWM. Fixes: 43a1c4ff3977 ("dt-bindings: pwm: Convert Amlogic Meson PWM binding") Reviewed-by: Rob Herring Signed-off-by: Jerome Brunet --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 69 ++++++++++++++++--- 1 file changed, 60 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml index 527864a4d855..387976ed36d5 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -9,9 +9,6 @@ title: Amlogic PWM maintainers: - Heiner Kallweit -allOf: - - $ref: pwm.yaml# - properties: compatible: oneOf: @@ -43,12 +40,8 @@ properties: maxItems: 2 clock-names: - oneOf: - - items: - - enum: [clkin0, clkin1] - - items: - - const: clkin0 - - const: clkin1 + minItems: 1 + maxItems: 2 "#pwm-cells": const: 3 @@ -57,6 +50,57 @@ required: - compatible - reg +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm + - amlogic,meson8b-pwm + - amlogic,meson-gxbb-pwm + - amlogic,meson-gxbb-ao-pwm + - amlogic,meson-axg-ee-pwm + - amlogic,meson-axg-ao-pwm + - amlogic,meson-g12a-ee-pwm + - amlogic,meson-g12a-ao-pwm-ab + - amlogic,meson-g12a-ao-pwm-cd + - amlogic,meson-gx-pwm + - amlogic,meson-gx-ao-pwm + then: + # Historic bindings tied to the driver implementation + # The clocks provided here are meant to be matched with the input + # known (hard-coded) in the driver and used to select pwm clock + # source. Currently, the linux driver ignores this. + properties: + clock-names: + oneOf: + - items: + - enum: [clkin0, clkin1] + - items: + - const: clkin0 + - const: clkin1 + + # Newer IP block take a single input per channel, instead of 4 inputs + # for both channels + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-s4-pwm + then: + properties: + clocks: + items: + - description: input clock of PWM channel A + - description: input clock of PWM channel B + clock-names: false + required: + - clocks + additionalProperties: false examples: @@ -68,3 +112,10 @@ examples: clock-names = "clkin0", "clkin1"; #pwm-cells = <3>; }; + - | + pwm@1000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x1000 0x10>; + clocks = <&pwm_src_a>, <&pwm_src_b>; + #pwm-cells = <3>; + }; From patchwork Wed Nov 29 13:39:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 748287 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="JhJFE5s9" Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02CC8E6 for ; Wed, 29 Nov 2023 05:40:34 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c88b7e69dfso80940381fa.0 for ; Wed, 29 Nov 2023 05:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1701265232; x=1701870032; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hQRwxx9GEOBkFVTtu0HXXPOcGrMBOKITGaWl4mMUCHI=; b=JhJFE5s9qNJaFRQopr+cK1bLrEwuATVyZ4pBBTf3+Nx8RQ8Rdi6kvrufAEyjSac/b5 flnqbFamH5PzLaGzE8QkgEwGWN2rTuAJcdVgsXGTnxpszd0euFL6l7MqmBJ+0fNhW/wq wO7TCpJBDu9vGy3k79HbyRuLAZ/GqTH8pS73Iq8FTU9V5kP1YCDVbD2lh570QZhBdZFq geMfimrX86N5hsfGe9MsJ7T3HPIRtiuzV/1jwOOUXD1ayvbJhu97sxqQoKDCS1pahgL3 7/3fpVnp5cleisFgVzjlTL+02qD78Kfxq+lUs9Puaf0iWdeXnYNFIHrYSnoXLXILONLf xGmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701265232; x=1701870032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hQRwxx9GEOBkFVTtu0HXXPOcGrMBOKITGaWl4mMUCHI=; b=HWWPJ2VUnNyNGuF3Gr1uCg1cVgy1eZNMLfHo+WE01e2h1FbMCcjG/jLIUFnJy5maa0 kC/+qdv9/5kqx7SSzDW3AxQgehZSoIGrzi2Nvx1ZasVrFhkCPNLF9uC8uwxv66gDBuD0 Hp1Nsr89F5Q4ZTi7MTmkkFtbv7Z9bLOGKqPJQlwOF6QPfLh59k4cdrS+1wMASwkg7y5D lj928OhvyY3tRCLAzvAzpg3s32ApLtgpt6dviTBkhDZaqAAg1AX6EaHzLNSPPCEyHNJI whu1VpqVaaSXnmIAtut+4pBSrxC2y7w+OKG9PxS/pt1ZM3D1djQlT7leQtGcMLBu4+HL 0A5A== X-Gm-Message-State: AOJu0Yxk3wWPMogF6XUh0ndv9vlbnNwwLPYR1C1xUX7vhuQSof+w/iYn avagFr9q7C8YDgCz8KSMUsALxH6MbBMGRUTS9q0= X-Google-Smtp-Source: AGHT+IE6EXkIS1MLDJ9G7G35/UHE0u8PoIQgoq4VqHWzasYKaYE0gqoMNy6M4o6VE2MrG4pH/0KbYg== X-Received: by 2002:a2e:9646:0:b0:2c9:ba44:fd9d with SMTP id z6-20020a2e9646000000b002c9ba44fd9dmr2347821ljh.38.1701265232031; Wed, 29 Nov 2023 05:40:32 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:6101:5529:fe2d:d7eb]) by smtp.googlemail.com with ESMTPSA id w17-20020a05600c475100b004080f0376a0sm2285860wmo.42.2023.11.29.05.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 05:40:31 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Subject: [PATCH v3 2/4] dt-bindings: pwm: amlogic: add new compatible for meson8 pwm type Date: Wed, 29 Nov 2023 14:39:58 +0100 Message-ID: <20231129134004.3642121-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231129134004.3642121-1-jbrunet@baylibre.com> References: <20231129134004.3642121-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Add a new compatible for the pwm found in the meson8 to sm1 Amlogic SoCs, dealing with clocks differently. This does not enable new HW. It is meant to fix a bad DT ABI for the currently supported HW. The original clock bindings describe which input the PWM channel multiplexer should pick among its possible parents, which are hard-coded in the driver. As such, it is a setting tied to the driver implementation and does not describe the HW. The new bindings introduce here describe the clocks input of the PWM block as they exist. The old compatible is deprecated but kept to maintain ABI compatibility. The SoC specific compatibles introduced match the SoC families supported by the original bindings. Signed-off-by: Jerome Brunet --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 52 ++++++++++++++++--- 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml index 387976ed36d5..eece390114a3 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -21,23 +21,35 @@ properties: - amlogic,meson-g12a-ee-pwm - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd - - amlogic,meson-s4-pwm + deprecated: true - items: - const: amlogic,meson-gx-pwm - const: amlogic,meson-gxbb-pwm + deprecated: true - items: - const: amlogic,meson-gx-ao-pwm - const: amlogic,meson-gxbb-ao-pwm + deprecated: true - items: - const: amlogic,meson8-pwm - const: amlogic,meson8b-pwm + deprecated: true + - const: amlogic,meson8-pwm-v2 + - items: + - enum: + - amlogic,meson8b-pwm-v2 + - amlogic,meson-gxbb-pwm-v2 + - amlogic,meson-axg-pwm-v2 + - amlogic,meson-g12-pwm-v2 + - const: amlogic,meson8-pwm-v2 + - const: amlogic,meson-s4-pwm reg: maxItems: 1 clocks: minItems: 1 - maxItems: 2 + maxItems: 4 clock-names: minItems: 1 @@ -58,7 +70,6 @@ allOf: compatible: contains: enum: - - amlogic,meson8-pwm - amlogic,meson8b-pwm - amlogic,meson-gxbb-pwm - amlogic,meson-gxbb-ao-pwm @@ -67,14 +78,15 @@ allOf: - amlogic,meson-g12a-ee-pwm - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd - - amlogic,meson-gx-pwm - - amlogic,meson-gx-ao-pwm then: - # Historic bindings tied to the driver implementation + # Obsolete historic bindings tied to the driver implementation # The clocks provided here are meant to be matched with the input # known (hard-coded) in the driver and used to select pwm clock # source. Currently, the linux driver ignores this. + # This is kept to maintain ABI backward compatibility. properties: + clocks: + maxItems: 2 clock-names: oneOf: - items: @@ -83,6 +95,27 @@ allOf: - const: clkin0 - const: clkin1 + # Newer binding where clock describe the actual clock inputs of the pwm + # block. These are necessary but some inputs may be grounded. + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm-v2 + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock 0 of the pwm block + - description: input clock 1 of the pwm block + - description: input clock 2 of the pwm block + - description: input clock 3 of the pwm block + clock-names: false + required: + - clocks + # Newer IP block take a single input per channel, instead of 4 inputs # for both channels - if: @@ -112,6 +145,13 @@ examples: clock-names = "clkin0", "clkin1"; #pwm-cells = <3>; }; + - | + pwm@2000 { + compatible = "amlogic,meson8-pwm-v2"; + reg = <0x1000 0x10>; + clocks = <&xtal>, <0>, <&fdiv4>, <&fdiv5>; + #pwm-cells = <3>; + }; - | pwm@1000 { compatible = "amlogic,meson-s4-pwm"; From patchwork Wed Nov 29 13:39:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 748774 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="aY+NgK5Z" Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78460CA for ; Wed, 29 Nov 2023 05:40:34 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-409299277bbso51392325e9.2 for ; Wed, 29 Nov 2023 05:40:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1701265233; x=1701870033; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z0+vsbx15h8F7iZEWw3YAZV40GdDwQ9Lrg1zkM7+uXE=; b=aY+NgK5Z2G02arce5owTN1KWhw7LuQ7NTBgvCwJBRrYkhz+syWIkLGxeBe8wT/+T9J zjmFr6SKmA+Il7Yrfv42nSpZVQ3XGjFPauPzhxyJlIVWjC5SoT69VpEsylS0WUBUGzPI MnuQevrdRmB2DepcTvuWngFRJvypRdIh9PK7b40C87yF+ZG5ue9Ve6tnM7+ixMQMDjNM UchOROvT4veLJAC6HEa9dr4E5moxYKu92qv0uj5UL8Kar8ixigqKIpj32HujllvKj7n7 N8/fd5AR+4h+oDs1kzmxvMPcI7LO9dHUA1ExZvbfEGKGsn7tOAZiDNwPl0LatdERmiZD I6YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701265233; x=1701870033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z0+vsbx15h8F7iZEWw3YAZV40GdDwQ9Lrg1zkM7+uXE=; b=qtX44loFW83tFd+ynZwTwz6boZkKnJrtRBeCZx0bU7F0rzhzIJYHYyoKV/BgIEYLnI 4hf3513XClc9dysVY4tYKlq20Z9XZSFPmOO43huukWXasTL7Cdi1FOYN061Natru0+Cx 3CjgW6uUwECdyIr6lpCYIni7KPzZqx+1wVUTncZ9ylRF3s7Fdh5hHSCBUt729uxabsyA a+Xn6DR/TmIVueIR2YFpjpL6euVYsJdIG+FegUeWtB+H2R9c9eHay4vPU4s/vRpXFQbR 0ufl00p9F092LSaDsSFPAb43uEoUvkUQejjDSEg7tdncajnOVsf/ZIuihVNo71dWYfir TgTg== X-Gm-Message-State: AOJu0YzfxxOThw1cqrWUcV7cBA930XxwkAbFE3oULQ6S+LEPeimH2Zqo F+0BAxZzX0lyt6zIwV+Edj0a0A== X-Google-Smtp-Source: AGHT+IGO5xlQpc0pK/xpaBnA/MLmbOocAbg7CZOKArt+y0Fo/ijzvKHBYsC2K/wZmHK3aPfUBnObPA== X-Received: by 2002:a05:600c:1d17:b0:401:eb0:a974 with SMTP id l23-20020a05600c1d1700b004010eb0a974mr15130701wms.3.1701265232916; Wed, 29 Nov 2023 05:40:32 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:6101:5529:fe2d:d7eb]) by smtp.googlemail.com with ESMTPSA id w17-20020a05600c475100b004080f0376a0sm2285860wmo.42.2023.11.29.05.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 05:40:32 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Subject: [PATCH v3 3/4] pwm: meson: prepare addition of new compatible types Date: Wed, 29 Nov 2023 14:39:59 +0100 Message-ID: <20231129134004.3642121-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231129134004.3642121-1-jbrunet@baylibre.com> References: <20231129134004.3642121-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Clean the amlogic pwm driver to prepare the addition of new pwm compatibles * Generalize 4 inputs clock per channel. AO pwm may just get 2 extra NULL entries which actually better describes the reality of the HW. * Use driver data to carry the device data and remove pwm_chip from it * Stop carrying the internal clock elements with the device data. These are not needed past init. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 150 +++++++++++++++++++++++----------------- 1 file changed, 87 insertions(+), 63 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 5bea53243ed2..5cbd65cae28a 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -60,7 +60,7 @@ #define MISC_A_EN BIT(0) #define MESON_NUM_PWMS 2 -#define MESON_MAX_MUX_PARENTS 4 +#define MESON_NUM_MUX_PARENTS 4 static struct meson_pwm_channel_data { u8 reg_offset; @@ -90,19 +90,14 @@ struct meson_pwm_channel { unsigned int hi; unsigned int lo; - struct clk_mux mux; - struct clk_divider div; - struct clk_gate gate; struct clk *clk; }; struct meson_pwm_data { const char * const *parent_names; - unsigned int num_parents; }; struct meson_pwm { - struct pwm_chip chip; const struct meson_pwm_data *data; struct meson_pwm_channel channels[MESON_NUM_PWMS]; void __iomem *base; @@ -115,7 +110,7 @@ struct meson_pwm { static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip) { - return container_of(chip, struct meson_pwm, chip); + return dev_get_drvdata(chip->dev); } static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) @@ -147,6 +142,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, const struct pwm_state *state) { struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; + struct device *dev = pwm->chip->dev; unsigned int cnt, duty_cnt; unsigned long fin_freq; u64 duty, period, freq; @@ -169,19 +165,19 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, fin_freq = clk_round_rate(channel->clk, freq); if (fin_freq == 0) { - dev_err(meson->chip.dev, "invalid source clock frequency\n"); + dev_err(dev, "invalid source clock frequency\n"); return -EINVAL; } - dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); + dev_dbg(dev, "fin_freq: %lu Hz\n", fin_freq); cnt = div_u64(fin_freq * period, NSEC_PER_SEC); if (cnt > 0xffff) { - dev_err(meson->chip.dev, "unable to get period cnt\n"); + dev_err(dev, "unable to get period cnt\n"); return -EINVAL; } - dev_dbg(meson->chip.dev, "period=%llu cnt=%u\n", period, cnt); + dev_dbg(dev, "period=%llu cnt=%u\n", period, cnt); if (duty == period) { channel->hi = cnt; @@ -192,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, } else { duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC); - dev_dbg(meson->chip.dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt); + dev_dbg(dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt); channel->hi = duty_cnt; channel->lo = cnt - duty_cnt; @@ -215,7 +211,7 @@ static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) err = clk_set_rate(channel->clk, channel->rate); if (err) - dev_err(meson->chip.dev, "setting clock rate failed\n"); + dev_err(pwm->chip->dev, "setting clock rate failed\n"); spin_lock_irqsave(&meson->lock, flags); @@ -343,7 +339,6 @@ static const char * const pwm_meson8b_parent_names[] = { static const struct meson_pwm_data pwm_meson8b_data = { .parent_names = pwm_meson8b_parent_names, - .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), }; /* @@ -351,12 +346,11 @@ static const struct meson_pwm_data pwm_meson8b_data = { * The last 2 are grounded */ static const char * const pwm_gxbb_ao_parent_names[] = { - "xtal", "clk81" + "xtal", "clk81", NULL, NULL, }; static const struct meson_pwm_data pwm_gxbb_ao_data = { .parent_names = pwm_gxbb_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; static const char * const pwm_axg_ee_parent_names[] = { @@ -365,7 +359,6 @@ static const char * const pwm_axg_ee_parent_names[] = { static const struct meson_pwm_data pwm_axg_ee_data = { .parent_names = pwm_axg_ee_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), }; static const char * const pwm_axg_ao_parent_names[] = { @@ -374,7 +367,6 @@ static const char * const pwm_axg_ao_parent_names[] = { static const struct meson_pwm_data pwm_axg_ao_data = { .parent_names = pwm_axg_ao_parent_names, - .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), }; static const char * const pwm_g12a_ao_ab_parent_names[] = { @@ -383,16 +375,14 @@ static const char * const pwm_g12a_ao_ab_parent_names[] = { static const struct meson_pwm_data pwm_g12a_ao_ab_data = { .parent_names = pwm_g12a_ao_ab_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), }; static const char * const pwm_g12a_ao_cd_parent_names[] = { - "xtal", "g12a_ao_clk81", + "xtal", "g12a_ao_clk81", NULL, NULL, }; static const struct meson_pwm_data pwm_g12a_ao_cd_data = { .parent_names = pwm_g12a_ao_cd_parent_names, - .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), }; static const struct of_device_id meson_pwm_matches[] = { @@ -432,23 +422,25 @@ static const struct of_device_id meson_pwm_matches[] = { }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -static int meson_pwm_init_channels(struct meson_pwm *meson) +static int meson_pwm_init_clocks_legacy(struct device *dev, + struct clk_parent_data *mux_parent_data) { - struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {}; - struct device *dev = meson->chip.dev; + struct meson_pwm *meson = dev_get_drvdata(dev); unsigned int i; char name[255]; int err; - for (i = 0; i < meson->data->num_parents; i++) { - mux_parent_data[i].index = -1; - mux_parent_data[i].name = meson->data->parent_names[i]; - } - - for (i = 0; i < meson->chip.npwm; i++) { + for (i = 0; i < MESON_NUM_PWMS; i++) { struct meson_pwm_channel *channel = &meson->channels[i]; struct clk_parent_data div_parent = {}, gate_parent = {}; struct clk_init_data init = {}; + struct clk_divider *div; + struct clk_gate *gate; + struct clk_mux *mux; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); @@ -456,69 +448,76 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) init.ops = &clk_mux_ops; init.flags = 0; init.parent_data = mux_parent_data; - init.num_parents = meson->data->num_parents; - - channel->mux.reg = meson->base + REG_MISC_AB; - channel->mux.shift = - meson_pwm_per_channel_data[i].clk_sel_shift; - channel->mux.mask = MISC_CLK_SEL_MASK; - channel->mux.flags = 0; - channel->mux.lock = &meson->lock; - channel->mux.table = NULL; - channel->mux.hw.init = &init; - - err = devm_clk_hw_register(dev, &channel->mux.hw); + init.num_parents = MESON_NUM_MUX_PARENTS; + + mux->reg = meson->base + REG_MISC_AB; + mux->shift = meson_pwm_per_channel_data[i].clk_sel_shift; + mux->mask = MISC_CLK_SEL_MASK; + mux->flags = 0; + mux->lock = &meson->lock; + mux->table = NULL; + mux->hw.init = &init; + + err = devm_clk_hw_register(dev, &mux->hw); if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i); init.name = name; init.ops = &clk_divider_ops; init.flags = CLK_SET_RATE_PARENT; div_parent.index = -1; - div_parent.hw = &channel->mux.hw; + div_parent.hw = &mux->hw; init.parent_data = &div_parent; init.num_parents = 1; - channel->div.reg = meson->base + REG_MISC_AB; - channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift; - channel->div.width = MISC_CLK_DIV_WIDTH; - channel->div.hw.init = &init; - channel->div.flags = 0; - channel->div.lock = &meson->lock; + div->reg = meson->base + REG_MISC_AB; + div->shift = meson_pwm_per_channel_data[i].clk_div_shift; + div->width = MISC_CLK_DIV_WIDTH; + div->hw.init = &init; + div->flags = 0; + div->lock = &meson->lock; - err = devm_clk_hw_register(dev, &channel->div.hw); + err = devm_clk_hw_register(dev, &div->hw); if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); init.name = name; init.ops = &clk_gate_ops; init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; gate_parent.index = -1; - gate_parent.hw = &channel->div.hw; + gate_parent.hw = &div->hw; init.parent_data = &gate_parent; init.num_parents = 1; - channel->gate.reg = meson->base + REG_MISC_AB; - channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; - channel->gate.hw.init = &init; - channel->gate.flags = 0; - channel->gate.lock = &meson->lock; + gate->reg = meson->base + REG_MISC_AB; + gate->bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; + gate->hw.init = &init; + gate->flags = 0; + gate->lock = &meson->lock; - err = devm_clk_hw_register(dev, &channel->gate.hw); + err = devm_clk_hw_register(dev, &gate->hw); if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } - channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL); + channel->clk = devm_clk_hw_get_clk(dev, &gate->hw, NULL); if (IS_ERR(channel->clk)) { err = PTR_ERR(channel->clk); dev_err(dev, "failed to register %s: %d\n", name, err); @@ -529,31 +528,56 @@ static int meson_pwm_init_channels(struct meson_pwm *meson) return 0; } +static int meson_pwm_init_channels(struct device *dev) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; + struct meson_pwm *meson = dev_get_drvdata(dev); + int i; + + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { + mux_parent_data[i].index = -1; + mux_parent_data[i].name = meson->data->parent_names[i]; + } + + return meson_pwm_init_clocks_legacy(dev, mux_parent_data); +} + static int meson_pwm_probe(struct platform_device *pdev) { struct meson_pwm *meson; + struct pwm_chip *chip; int err; + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); if (!meson) return -ENOMEM; + platform_set_drvdata(pdev, meson); + meson->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(meson->base)) return PTR_ERR(meson->base); spin_lock_init(&meson->lock); - meson->chip.dev = &pdev->dev; - meson->chip.ops = &meson_pwm_ops; - meson->chip.npwm = MESON_NUM_PWMS; + chip->dev = &pdev->dev; + chip->ops = &meson_pwm_ops; + chip->npwm = MESON_NUM_PWMS; meson->data = of_device_get_match_data(&pdev->dev); + if (!meson->data) { + dev_err(&pdev->dev, "failed to match device\n"); + return -ENODEV; + } - err = meson_pwm_init_channels(meson); + err = meson_pwm_init_channels(&pdev->dev); if (err < 0) return err; - err = devm_pwmchip_add(&pdev->dev, &meson->chip); + err = devm_pwmchip_add(&pdev->dev, chip); if (err < 0) { dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); return err; From patchwork Wed Nov 29 13:40:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 748286 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="cmL4Cw75" Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 826D41AD for ; Wed, 29 Nov 2023 05:40:35 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40b4746ae3bso22119805e9.0 for ; Wed, 29 Nov 2023 05:40:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1701265234; x=1701870034; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Wed, 29 Nov 2023 05:40:33 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:6101:5529:fe2d:d7eb]) by smtp.googlemail.com with ESMTPSA id w17-20020a05600c475100b004080f0376a0sm2285860wmo.42.2023.11.29.05.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 05:40:33 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Subject: [PATCH v3 4/4] pwm: meson: add generic compatible for meson8 to sm1 Date: Wed, 29 Nov 2023 14:40:00 +0100 Message-ID: <20231129134004.3642121-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231129134004.3642121-1-jbrunet@baylibre.com> References: <20231129134004.3642121-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Introduce a new compatible support in the Amlogic PWM driver. The PWM HW is actually the same for all SoCs supported so far. A specific compatible is needed only because the clock sources of the PWMs are hard-coded in the driver. It is better to have the clock source described in DT but this changes the bindings so a new compatible must be introduced. When all supported platform have migrated to the new compatible, support for the legacy ones may be removed from the driver. Adding a callback to setup the clock will also make it easier to add support for the new PWM HW found in a1, s4, c3 and t7 SoC families. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 224 ++++++++++++++++++++++++---------------- 1 file changed, 133 insertions(+), 91 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 5cbd65cae28a..d5d745a651d3 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -95,6 +95,7 @@ struct meson_pwm_channel { struct meson_pwm_data { const char * const *parent_names; + int (*channels_init)(struct device *dev); }; struct meson_pwm { @@ -333,95 +334,6 @@ static const struct pwm_ops meson_pwm_ops = { .get_state = meson_pwm_get_state, }; -static const char * const pwm_meson8b_parent_names[] = { - "xtal", NULL, "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_meson8b_data = { - .parent_names = pwm_meson8b_parent_names, -}; - -/* - * Only the 2 first inputs of the GXBB AO PWMs are valid - * The last 2 are grounded - */ -static const char * const pwm_gxbb_ao_parent_names[] = { - "xtal", "clk81", NULL, NULL, -}; - -static const struct meson_pwm_data pwm_gxbb_ao_data = { - .parent_names = pwm_gxbb_ao_parent_names, -}; - -static const char * const pwm_axg_ee_parent_names[] = { - "xtal", "fclk_div5", "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_axg_ee_data = { - .parent_names = pwm_axg_ee_parent_names, -}; - -static const char * const pwm_axg_ao_parent_names[] = { - "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" -}; - -static const struct meson_pwm_data pwm_axg_ao_data = { - .parent_names = pwm_axg_ao_parent_names, -}; - -static const char * const pwm_g12a_ao_ab_parent_names[] = { - "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" -}; - -static const struct meson_pwm_data pwm_g12a_ao_ab_data = { - .parent_names = pwm_g12a_ao_ab_parent_names, -}; - -static const char * const pwm_g12a_ao_cd_parent_names[] = { - "xtal", "g12a_ao_clk81", NULL, NULL, -}; - -static const struct meson_pwm_data pwm_g12a_ao_cd_data = { - .parent_names = pwm_g12a_ao_cd_parent_names, -}; - -static const struct of_device_id meson_pwm_matches[] = { - { - .compatible = "amlogic,meson8b-pwm", - .data = &pwm_meson8b_data - }, - { - .compatible = "amlogic,meson-gxbb-pwm", - .data = &pwm_meson8b_data - }, - { - .compatible = "amlogic,meson-gxbb-ao-pwm", - .data = &pwm_gxbb_ao_data - }, - { - .compatible = "amlogic,meson-axg-ee-pwm", - .data = &pwm_axg_ee_data - }, - { - .compatible = "amlogic,meson-axg-ao-pwm", - .data = &pwm_axg_ao_data - }, - { - .compatible = "amlogic,meson-g12a-ee-pwm", - .data = &pwm_meson8b_data - }, - { - .compatible = "amlogic,meson-g12a-ao-pwm-ab", - .data = &pwm_g12a_ao_ab_data - }, - { - .compatible = "amlogic,meson-g12a-ao-pwm-cd", - .data = &pwm_g12a_ao_cd_data - }, - {}, -}; -MODULE_DEVICE_TABLE(of, meson_pwm_matches); - static int meson_pwm_init_clocks_legacy(struct device *dev, struct clk_parent_data *mux_parent_data) { @@ -528,12 +440,15 @@ static int meson_pwm_init_clocks_legacy(struct device *dev, return 0; } -static int meson_pwm_init_channels(struct device *dev) +static int meson_pwm_init_channels_legacy(struct device *dev) { struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; struct meson_pwm *meson = dev_get_drvdata(dev); int i; + dev_info(dev, "using obsolete compatible, please consider updating dt\n"); + + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) { mux_parent_data[i].index = -1; mux_parent_data[i].name = meson->data->parent_names[i]; @@ -542,6 +457,133 @@ static int meson_pwm_init_channels(struct device *dev) return meson_pwm_init_clocks_legacy(dev, mux_parent_data); } +static int meson_pwm_init_channels_meson8b_v2(struct device *dev) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {}; + int i; + + /* + * NOTE: Instead of relying on the hard coded names in the driver + * as the legacy version, this relies on DT to provide the list of + * clocks. + * For once, using input numbers actually makes more sense than names. + * Also DT requires clock-names to be explicitly ordered, so there is + * no point bothering with clock names in this case. + */ + for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) + mux_parent_data[i].index = i; + + return meson_pwm_init_clocks_legacy(dev, mux_parent_data); +} + +static const char * const pwm_meson8b_parent_names[] = { + "xtal", NULL, "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_meson8b_data = { + .parent_names = pwm_meson8b_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +/* + * Only the 2 first inputs of the GXBB AO PWMs are valid + * The last 2 are grounded + */ +static const char * const pwm_gxbb_ao_parent_names[] = { + "xtal", "clk81", NULL, NULL, +}; + +static const struct meson_pwm_data pwm_gxbb_ao_data = { + .parent_names = pwm_gxbb_ao_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_g12a_ao_ab_parent_names[] = { + "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_g12a_ao_ab_data = { + .parent_names = pwm_g12a_ao_ab_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_g12a_ao_cd_parent_names[] = { + "xtal", "g12a_ao_clk81", NULL, NULL, +}; + +static const struct meson_pwm_data pwm_g12a_ao_cd_data = { + .parent_names = pwm_g12a_ao_cd_parent_names, + .channels_init = meson_pwm_init_channels_legacy, +}; + +static const struct meson_pwm_data pwm_meson8_v2_data = { + .channels_init = meson_pwm_init_channels_meson8b_v2, +}; + +static const struct of_device_id meson_pwm_matches[] = { + { + .compatible = "amlogic,meson8-pwm-v2", + .data = &pwm_meson8_v2_data + }, + /* + * The following compatibles are obsolete. + * Support for these may be removed once the related + * platforms have been updated + */ + { + .compatible = "amlogic,meson8b-pwm", + .data = &pwm_meson8b_data + }, + { + .compatible = "amlogic,meson-gxbb-pwm", + .data = &pwm_meson8b_data + }, + { + .compatible = "amlogic,meson-gxbb-ao-pwm", + .data = &pwm_gxbb_ao_data + }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, + { + .compatible = "amlogic,meson-g12a-ee-pwm", + .data = &pwm_meson8b_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-ab", + .data = &pwm_g12a_ao_ab_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-cd", + .data = &pwm_g12a_ao_cd_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, meson_pwm_matches); + static int meson_pwm_probe(struct platform_device *pdev) { struct meson_pwm *meson; @@ -573,7 +615,7 @@ static int meson_pwm_probe(struct platform_device *pdev) return -ENODEV; } - err = meson_pwm_init_channels(&pdev->dev); + err = meson->data->channels_init(&pdev->dev); if (err < 0) return err;