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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id q26-20020a17090622da00b00a0d74d56d66sm3154544eja.42.2023.11.28.05.37.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:37:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , Samuel Tardieu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Alessandro Di Federico Subject: [PULL 1/7] target/hexagon/idef-parser/prepare: use env to invoke bash Date: Tue, 28 Nov 2023 14:37:34 +0100 Message-ID: <20231128133740.64525-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Samuel Tardieu This file is the only one involved in the compilation process which still uses the /bin/bash path. Signed-off-by: Samuel Tardieu Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-ID: <20231123211506.636533-1-sam@rfc1149.net> Signed-off-by: Philippe Mathieu-Daudé --- target/hexagon/idef-parser/prepare | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/idef-parser/prepare b/target/hexagon/idef-parser/prepare index 72d6fcbd21..cb3622d4f8 100755 --- a/target/hexagon/idef-parser/prepare +++ b/target/hexagon/idef-parser/prepare @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # # Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved. 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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id f11-20020a17090624cb00b009fc3f347109sm6766375ejb.156.2023.11.28.05.37.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:37:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PULL 2/7] hw/isa/vt82c686: Bring back via_isa_set_irq() Date: Tue, 28 Nov 2023 14:37:35 +0100 Message-ID: <20231128133740.64525-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: BALATON Zoltan The VIA integrated south bridge chips combine several functions and allow routing their interrupts to any of the ISA IRQs also allowing multiple sources to share the same ISA IRQ. E.g. pegasos2 firmware configures everything to use IRQ 9 but amigaone routes them to separate ISA IRQs so the current simplified routing does not work. Bring back via_isa_set_irq() and change it to take the component that wants to change an IRQ and keep track of interrupt status of each source separately and do the mapping to ISA IRQ within the ISA bridge. This may not handle cases when an ISA IRQ is controlled by devices directly, not going through via_isa_set_irq() such as serial, parallel or keyboard but these IRQs being conventionally fixed are not likely to be change by guests or share with other devices so this does not cause a problem in practice. This reverts commit 4e5a20b6da9b1f6d2e9621ed7eb8b239560104ae. Signed-off-by: BALATON Zoltan Message-ID: <1c3902d4166234bef0a476026441eaac3dd6cda5.1701035944.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/isa/vt82c686.h | 2 ++ hw/isa/vt82c686.c | 41 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index b6e95b2851..da1722daf2 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -34,4 +34,6 @@ struct ViaAC97State { uint32_t ac97_cmd; }; +void via_isa_set_irq(PCIDevice *d, int n, int level); + #endif diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 57bdfb4e78..6fad8293e6 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -549,6 +549,7 @@ struct ViaISAState { PCIDevice dev; qemu_irq cpu_intr; qemu_irq *isa_irqs_in; + uint16_t irq_state[ISA_NUM_IRQS]; ViaSuperIOState via_sio; MC146818RtcState rtc; PCIIDEState ide; @@ -592,6 +593,46 @@ static const TypeInfo via_isa_info = { }, }; +void via_isa_set_irq(PCIDevice *d, int pin, int level) +{ + ViaISAState *s = VIA_ISA(pci_get_function_0(d)); + uint8_t irq = d->config[PCI_INTERRUPT_LINE], max_irq = 15; + int f = PCI_FUNC(d->devfn); + uint16_t mask = BIT(f); + + switch (f) { + case 2: /* USB ports 0-1 */ + case 3: /* USB ports 2-3 */ + max_irq = 14; + break; + } + + /* Keep track of the state of all sources */ + if (level) { + s->irq_state[0] |= mask; + } else { + s->irq_state[0] &= ~mask; + } + if (irq == 0 || irq == 0xff) { + return; /* disabled */ + } + if (unlikely(irq > max_irq || irq == 2)) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d", + irq, f); + return; + } + /* Record source state at mapped IRQ */ + if (level) { + s->irq_state[irq] |= mask; + } else { + s->irq_state[irq] &= ~mask; + } + /* Make sure there are no stuck bits if mapping has changed */ + s->irq_state[irq] &= s->irq_state[0]; + /* ISA IRQ level is the OR of all sources routed to it */ + qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]); +} + static void via_isa_request_i8259_irq(void *opaque, int irq, int level) { ViaISAState *s = opaque; From patchwork Tue Nov 28 13:37:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 747818 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp3833222wru; Tue, 28 Nov 2023 05:38:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IEzPEG3SNriqNC4Qd51R4nJ4ncYmamzhGMIBZ1uyRFR8jwrwkm8IAtm8hl+R9eaN17BZRVe X-Received: by 2002:a05:622a:13d0:b0:41c:c045:2c86 with SMTP id p16-20020a05622a13d000b0041cc0452c86mr34154585qtk.31.1701178739319; Tue, 28 Nov 2023 05:38:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701178739; cv=none; d=google.com; s=arc-20160816; b=GRQP10BkBpsSj0ytTtm7/Z0EC2UMtiQ3tB7t7wEQisHkHShJRXYNIpjfRjkZ5W13sO tesKQjVG6IQN8j04+eOc5ib9v/WW1zfl2iW2ZZH5lVvriL9qRlgCbyRQBot9k9/LuIZH xY2NOL8sQ1q5LDRkKE0ugm6u1qKEoylNVGuBLWsjhgwFBiVTp9HABYnMT/VvYf+q2eXX ST460EnJEhyfh71yC0ahWYR1Zyd9mBx9VtKje8aBB0oPb4d6cGE2W8dn7enEcR/6OmZd oyRAcs2EyjWx++bm1g465N4iSUzNTU1pzWPEg7Zl2HOcEDVh/bY9hE0qhHJiiTfphtoR x76Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AU3XHV66pWU29DJMHZUdephtHQTkVekgNrGzgZLdqHA=; fh=R1DZWSCtOOcpxfKmg0yS3ViW41SOHK39cw8w1UwMtV8=; b=tXTuE/KjEiAfG1fkeb8cmsaqMdzRlyrNp8dkJx64mQ8yaY7eOWM0UMTGz++5oPyYbU m1U3sBeAQMIqPWUBSCE7USYbQVfOVjsn7T8RhufUB2UqMZOo87jSgBpWyLGSRiuFaVAK BJnmvafxsGEJWpr/1vJrZ7UqI6ZDXgjZkPYhz2KaUnguS3a7g+hOKadlClezvKwaI08G Pnpu2FVxz+przn8vvldTX72z/KM59n92YOfaojUjlCVNHhQF9I/xkWOf72628o8S5v7C 8SJM5hSkhEsLwuMl2Be9Yzs3q4ncg76lPcPCgxpeo/AAOzigNgdEpRgzxP5m4o89DNKr qTcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rSEU1WnV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id bw24-20020a170906c1d800b009fc24437439sm6785378ejb.158.2023.11.28.05.37.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:37:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Jiaxun Yang Subject: [PULL 3/7] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts Date: Tue, 28 Nov 2023 14:37:36 +0100 Message-ID: <20231128133740.64525-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: BALATON Zoltan This device is part of a superio/ISA bridge chip and IRQs from it are routed to an ISA interrupt. Use via_isa_set_irq() function to implement this in a vt82c686-uhci-pci specific irq handler. This reverts commit 422a6e8075752bc5342afd3eace23a4990dd7d98. Signed-off-by: BALATON Zoltan Message-ID: Signed-off-by: Philippe Mathieu-Daudé --- hw/usb/vt82c686-uhci-pci.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/usb/vt82c686-uhci-pci.c b/hw/usb/vt82c686-uhci-pci.c index b4884c9011..6162806172 100644 --- a/hw/usb/vt82c686-uhci-pci.c +++ b/hw/usb/vt82c686-uhci-pci.c @@ -1,7 +1,14 @@ #include "qemu/osdep.h" +#include "hw/irq.h" #include "hw/isa/vt82c686.h" #include "hcd-uhci.h" +static void uhci_isa_set_irq(void *opaque, int irq_num, int level) +{ + UHCIState *s = opaque; + via_isa_set_irq(&s->dev, 0, level); +} + static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) { UHCIState *s = UHCI(dev); @@ -15,6 +22,8 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) pci_set_long(pci_conf + 0xc0, 0x00002000); usb_uhci_common_realize(dev, errp); + object_unref(s->irq); + s->irq = qemu_allocate_irq(uhci_isa_set_irq, s, 0); } static UHCIInfo uhci_info[] = { From patchwork Tue Nov 28 13:37:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 747820 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp3833527wru; Tue, 28 Nov 2023 05:39:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IGER/MxTsHWH2w8NTUXig1315Svfa95RPQkAJdCJ1A9xi5E0ODSvWBYqJT4D0z1WGdgD3hE X-Received: by 2002:a05:622a:7716:b0:423:a242:e888 with SMTP id ki22-20020a05622a771600b00423a242e888mr10730671qtb.10.1701178776974; Tue, 28 Nov 2023 05:39:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701178776; cv=none; d=google.com; s=arc-20160816; b=o8hLSg9XQ4EVS2feLliDo0SwwZI5x2Dt+1F+aMV8cTPI4fZdJUf90foZ5n78nOOl2I xDtd7annww/2xZ5FDFmPTJSyoIfKdD9inUFw++n+hRPjAOIyR1EPkKH1c+3je18Y+F64 VcXg8HLyZPPPJGVzvdVVkuJ8PL21Y9gx7WedObb+aWa0ZGffBJTTVy1+MreiYS0RUeKj PdJOaWEhg90YtAaKQCcSYde+4Axm3az1OGfFOSqwsm5xIKRgXcG4tSKTWIxNWTRwR/Vp kpZCzKUiFek+diW4evhL+3UZoHi778VNHBIfrg3nALST+Bm13TcJlY5LuzC1I8zBaupz q4eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=leKlI1n6G5PcdrvHQ/d7MuXu3YgwQw5y2/1THyY9+Xg=; fh=hBsxs0s1RgBcUVyI/rHo9bf553qggxN0nItGHUfTdbY=; b=mugiAyt+Uf6s6zCrpjBiPGzo8yw4nKoJhYH3ZqLVt6l7Oy55ZAl5VhkZuPF14xVjx3 1I95r+Ao3LNO1VbVvYQim79SUW3dfcEnoPI2YAL9XGrkT/m1OV+PlaENN0GQjcFj/vjf 55mTGGl+7TWHJn27L4tAWqXhNcQZ3D3PUE3d9RopSuTvcmSllObExYeGMhBIVmTWPbak qaX6GaGdRHIvlh2cfp7af+reA6aAgpEskMo/GV5cX+UBEXbSrHISKP3amfWg1zSck9s4 H0w2ZWSHRFl1N2tt/NS0ac6M12v9EnJ9vdN2h5xuoxuskJqdKGmcczNl2ieiGwZxqm8Z 9V6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W3PzGoEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id h1-20020a170906590100b00a0c68d3f486sm3861968ejq.94.2023.11.28.05.38.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:38:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PULL 4/7] hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq() Date: Tue, 28 Nov 2023 14:37:37 +0100 Message-ID: <20231128133740.64525-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: BALATON Zoltan The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in VT8231) that are meant to be connected to PCI IRQ lines and allow routing PCI interrupts to the ISA PIC. Route these in via_isa_set_irq() to make it possible to share them with internal functions that can also be routed to the same ISA IRQs. Fixes: 2fdadd02e675caca4aba4ae26317701fe2c4c901 Signed-off-by: BALATON Zoltan Message-ID: <8c4513d8b78fac40e6d4e65a0a4b3a7f2f278a4b.1701035944.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/vt82c686.c | 67 ++++++++++++++++++----------------------------- 1 file changed, 25 insertions(+), 42 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 6fad8293e6..a3eb6769fc 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -593,6 +593,21 @@ static const TypeInfo via_isa_info = { }, }; +static int via_isa_get_pci_irq(const ViaISAState *s, int pin) +{ + switch (pin) { + case 0: + return s->dev.config[0x55] >> 4; + case 1: + return s->dev.config[0x56] & 0xf; + case 2: + return s->dev.config[0x56] >> 4; + case 3: + return s->dev.config[0x57] >> 4; + } + return 0; +} + void via_isa_set_irq(PCIDevice *d, int pin, int level) { ViaISAState *s = VIA_ISA(pci_get_function_0(d)); @@ -601,6 +616,10 @@ void via_isa_set_irq(PCIDevice *d, int pin, int level) uint16_t mask = BIT(f); switch (f) { + case 0: /* PIRQ/PINT inputs */ + irq = via_isa_get_pci_irq(s, pin); + f = 8 + pin; /* Use function 8-11 for PCI interrupt inputs */ + break; case 2: /* USB ports 0-1 */ case 3: /* USB ports 2-3 */ max_irq = 14; @@ -633,52 +652,17 @@ void via_isa_set_irq(PCIDevice *d, int pin, int level) qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]); } +static void via_isa_pirq(void *opaque, int pin, int level) +{ + via_isa_set_irq(opaque, pin, level); +} + static void via_isa_request_i8259_irq(void *opaque, int irq, int level) { ViaISAState *s = opaque; qemu_set_irq(s->cpu_intr, level); } -static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) -{ - switch (irq_num) { - case 0: - return s->dev.config[0x55] >> 4; - case 1: - return s->dev.config[0x56] & 0xf; - case 2: - return s->dev.config[0x56] >> 4; - case 3: - return s->dev.config[0x57] >> 4; - } - return 0; -} - -static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) -{ - ViaISAState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - int i, pic_level, pic_irq = via_isa_get_pci_irq(s, irq_num); - - /* IRQ 0: disabled, IRQ 2,8,13: reserved */ - if (!pic_irq) { - return; - } - if (unlikely(pic_irq == 2 || pic_irq == 8 || pic_irq == 13)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing"); - } - - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PCI_NUM_PINS; i++) { - if (pic_irq == via_isa_get_pci_irq(s, i)) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - /* Now we change the pic irq level according to the via irq mappings. */ - qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); -} - static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s = VIA_ISA(d); @@ -689,6 +673,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp) int i; qdev_init_gpio_out(dev, &s->cpu_intr, 1); + qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS); isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d), errp); @@ -702,8 +687,6 @@ static void via_isa_realize(PCIDevice *d, Error **errp) i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); - qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS); - /* RTC */ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { From patchwork Tue Nov 28 13:37:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 747822 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp3833563wru; Tue, 28 Nov 2023 05:39:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IF8Lac8sVz5/ShMkycs82eVbeSFQiD2a2mhqopbSsNq1J3IxhczSMS6Jp9k3M6Qv6Kt4HAc X-Received: by 2002:ac8:7dcc:0:b0:423:8b9c:cfbc with SMTP id c12-20020ac87dcc000000b004238b9ccfbcmr20605534qte.8.1701178781668; Tue, 28 Nov 2023 05:39:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id h18-20020a1709063b5200b009fdd2c6d042sm6955414ejf.148.2023.11.28.05.38.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:38:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Jiaxun Yang Subject: [PULL 5/7] hw/audio/via-ac97: Route interrupts using via_isa_set_irq() Date: Tue, 28 Nov 2023 14:37:38 +0100 Message-ID: <20231128133740.64525-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: BALATON Zoltan This device is a function of VIA south bridge and should allow setting interrupt routing within that chip. This is implemented in via_isa_set_irq(). Fixes: eb604411a78b82c468e2b8d81a9401eb8b9c7658 Signed-off-by: BALATON Zoltan Message-ID: <5329840e4be6dd8ae143d07cbfe61d8d2d106654.1701035944.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/audio/via-ac97.c | 8 ++++---- hw/isa/vt82c686.c | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c index 30095a4c7a..4c127a1def 100644 --- a/hw/audio/via-ac97.c +++ b/hw/audio/via-ac97.c @@ -211,14 +211,14 @@ static void out_cb(void *opaque, int avail) AUD_set_active_out(s->vo, 0); } if (c->type & STAT_EOL) { - pci_set_irq(&s->dev, 1); + via_isa_set_irq(&s->dev, 0, 1); } } if (CLEN_IS_FLAG(c)) { c->stat |= STAT_FLAG; c->stat |= STAT_PAUSED; if (c->type & STAT_FLAG) { - pci_set_irq(&s->dev, 1); + via_isa_set_irq(&s->dev, 0, 1); } } if (CLEN_IS_STOP(c)) { @@ -305,13 +305,13 @@ static void sgd_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) if (val & STAT_EOL) { s->aur.stat &= ~(STAT_EOL | STAT_PAUSED); if (s->aur.type & STAT_EOL) { - pci_set_irq(&s->dev, 0); + via_isa_set_irq(&s->dev, 0, 0); } } if (val & STAT_FLAG) { s->aur.stat &= ~(STAT_FLAG | STAT_PAUSED); if (s->aur.type & STAT_FLAG) { - pci_set_irq(&s->dev, 0); + via_isa_set_irq(&s->dev, 0, 0); } } break; diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index a3eb6769fc..9c2333a277 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -622,6 +622,7 @@ void via_isa_set_irq(PCIDevice *d, int pin, int level) break; case 2: /* USB ports 0-1 */ case 3: /* USB ports 2-3 */ + case 5: /* AC97 audio */ max_irq = 14; break; } From patchwork Tue Nov 28 13:37:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 747819 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp3833220wru; Tue, 28 Nov 2023 05:38:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IEAO3UCDLt2Dyhsj6eib7uKFFPUbVKY542OUvms1pLwdl28Eb5QaVpvlylAOHAdPqkuzI8p X-Received: by 2002:ac8:4e88:0:b0:423:74a5:a8e with SMTP id 8-20020ac84e88000000b0042374a50a8emr24244381qtp.24.1701178739075; Tue, 28 Nov 2023 05:38:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701178739; cv=none; d=google.com; s=arc-20160816; b=TyZ+V9+SxYpXHfmK6SZAZJju10Ph38yKZ3Gz3DPxgTcr/x/u1e3biKhzEruZsHNhc2 2nc+GvqKPRT3COs5o9zeDlfp1lGrR2ZfKBXTfPqEu8kGqu4bUq9YtQLovHs0jtp79I4Q jO4K4EodSo5y0CPCfrikAOvpIlGlQu3yZFxspjWIP1sQQbxMJdfzGNLrbfGv1V7bWhWv y0aH+myFGV2d9E7T14Mo9iaQM6QQLST5LLzpmC+D+oMK4nqPP6pHXckZ27nmkalLB0OK r+g3KfPk3C4Qq/0VJl7oSqeDI+BYAQJhCd5ETeJZq/xmHBERs7PLyjFn2B+q53kG4PeW v5pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=peKa62xUsod/edNIYUpkMuF8n0prRBNW2awRUt91oBs=; fh=qexCIr1kq/v6pWN/euU8Ozev9ESr0tn/7HxtvuBZWfc=; b=wYI7kVn0HGvdxUleeguFZvKck82D88gASErccnZGN7OeTpjA3lFdaGZeUr0wolC5B/ lwLhyLUexnynzOQtMY22KB6Px8e2mtEnZ3m5B5aIlN9UuEe7fzggJatziUTDsSk6fb8e gJi3esRoHLZs2NpETHwARuCnJdeoOEcmlo7S9xh+uIt4pSgDW1Cbhol+YubUwTfXayb/ fNpw2qrk6ekdOWqODga6hrBcfLUvZhuLbgAJvnKg2dOj9Pq3fYvvpLo4d3XosoPeTS9D Qnkax6g3vlnmxHvknLn+Wa111w+Awz+jCW0uO7tVHBdV3xbpyrcR8HgxAaHBcSfnP40U in+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LbAnZXga; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id f3-20020a170906c08300b00a0a25541153sm5049993ejz.93.2023.11.28.05.38.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:38:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , Gihun Nam , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 6/7] hw/avr/atmega: Fix wrong initial value of stack pointer Date: Tue, 28 Nov 2023 14:37:39 +0100 Message-ID: <20231128133740.64525-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gihun Nam The current implementation initializes the stack pointer of AVR devices to 0. Although older AVR devices used to be like that, newer ones set it to RAMEND. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1525 Signed-off-by: Gihun Nam Reviewed-by: Philippe Mathieu-Daudé Message-ID: Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 3 +++ hw/avr/atmega.c | 4 ++++ target/avr/cpu.c | 10 +++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 8a17862737..7960c5c57a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -145,6 +145,9 @@ struct ArchCPU { CPUState parent_obj; CPUAVRState env; + + /* Initial value of stack pointer */ + uint32_t init_sp; }; /** diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index a34803e642..31c8992d75 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -233,6 +233,10 @@ static void atmega_realize(DeviceState *dev, Error **errp) /* CPU */ object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type); + + object_property_set_uint(OBJECT(&s->cpu), "init-sp", + mc->io_size + mc->sram_size - 1, &error_abort); + qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev = DEVICE(&s->cpu); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 44de1e18d1..999c010ded 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" +#include "hw/qdev-properties.h" static void avr_cpu_set_pc(CPUState *cs, vaddr value) { @@ -95,7 +96,7 @@ static void avr_cpu_reset_hold(Object *obj) env->rampY = 0; env->rampZ = 0; env->eind = 0; - env->sp = 0; + env->sp = cpu->init_sp; env->skip = 0; @@ -152,6 +153,11 @@ static void avr_cpu_initfn(Object *obj) sizeof(cpu->env.intsrc) * 8); } +static Property avr_cpu_properties[] = { + DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), + DEFINE_PROP_END_OF_LIST() +}; + static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -228,6 +234,8 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); + device_class_set_props(dc, avr_cpu_properties); + resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL, &mcc->parent_phases); From patchwork Tue Nov 28 13:37:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 747823 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp3833613wru; Tue, 28 Nov 2023 05:39:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IG2JcyfL/4JbuEpI30oEb6pNyxZKDxAKZR4tHXGTy8NKkZv2KWROR8yjiecsbAaxy1yWVnd X-Received: by 2002:a0c:ec06:0:b0:67a:47da:4fd7 with SMTP id y6-20020a0cec06000000b0067a47da4fd7mr7731081qvo.35.1701178791823; Tue, 28 Nov 2023 05:39:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701178791; cv=none; d=google.com; s=arc-20160816; b=zqhgw5CnvXgAGpzjytznZra9RY3NCXsUEHTSHI3r8A25xL2J1ijuxFQfjl2e7GXm8b y1eULUISQ7UnRECRkxyJ1/y/aZxLGTbAWI5HjrpbubFTXE/W7SgTT4thS4oUZAnp9EJ0 Dlg0Yf2Nv2F6/47OTwnlVALkjfrJp2NzWweHEwpbo6IAh+tMr2Nvdkpvn5pl0DdYMo4a 0lGC+GqbzUBZj+ly5KIN8DXbU6JTQDMdZGdFZPjjCmS5iRahiY7UM4uPE+Qa7TBlXgBr Oh6N3zB35BSA0VOp4Dx4FXGusvPjA616fBIrpmhg2rATzfX+dOpiYuqRW5JHOaxer0jn ehaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LowDtlS1mSCv15/zQIclQz5ifQEKy3t4KP1QtlXYuNc=; fh=3FZ4XRpBcl4chNJJILREFZUlUNzTZEpnb2+X/qanAcI=; b=BrKyGPxrv8yhxCrvB0zyeqOtElgh8X7zu4YRbGZdJqtOlcgs+y13Qa80QiXnlJxyN9 hm2PwY8k85hVjC5INesm/PBDixvLWkWQyUlBXE9pE27g4mV8ITn5d7kd8jKtGwLZy0/1 qrj0I+h4Zt9ADRhgLio7u1rVmNpRLhc95hdE3kSsYgvkVAkRstGgIKEjPJ/KxQdM1LIQ U/9d3K8LBfwrX9CWBOv5OSyZ/GS1t5AyomhwvHYaASwSHw6VsGTDic1zSa7b9seUUCty JhL7+6eUWGR8uXI6DtAZjPbjN5HLmgEN7o0jjCBVaCBeZtfUisjbj7k/Mrs83gI2U5vI 2R6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ic8Jx5gB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id hg12-20020a1709072ccc00b009fe1dd221a3sm6848556ejc.92.2023.11.28.05.38.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 Nov 2023 05:38:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Michael Rolnik , BALATON Zoltan , Zhao Liu , Nina Schoetterl-Glausch , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Thomas Huth Subject: [PULL 7/7] docs/s390: Fix wrong command example in s390-cpu-topology.rst Date: Tue, 28 Nov 2023 14:37:40 +0100 Message-ID: <20231128133740.64525-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231128133740.64525-1-philmd@linaro.org> References: <20231128133740.64525-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhao Liu >From s390_possible_cpu_arch_ids() in hw/s390x/s390-virtio-ccw.c, the "core-id" is the index of possible_cpus->cpus[], so it should only be less than possible_cpus->len, which is equal to ms->smp.max_cpus. Fix the wrong "core-id" 112, because it isn't less than maxcpus (36) in -smp, and the valid core ids are 0-35 inclusive. Signed-off-by: Zhao Liu Reviewed-by: Nina Schoetterl-Glausch Message-ID: <20231127134917.568552-1-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- docs/devel/s390-cpu-topology.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/devel/s390-cpu-topology.rst b/docs/devel/s390-cpu-topology.rst index 9eab28d5e5..48313b92d4 100644 --- a/docs/devel/s390-cpu-topology.rst +++ b/docs/devel/s390-cpu-topology.rst @@ -15,7 +15,7 @@ have default values: -smp 1,drawers=3,books=3,sockets=2,cores=2,maxcpus=36 \ -device z14-s390x-cpu,core-id=19,entitlement=high \ -device z14-s390x-cpu,core-id=11,entitlement=low \ - -device z14-s390x-cpu,core-id=112,entitlement=high \ + -device z14-s390x-cpu,core-id=12,entitlement=high \ ... Additions to query-cpus-fast @@ -78,7 +78,7 @@ modifiers for all configured vCPUs. "dedicated": true, "thread-id": 537005, "props": { - "core-id": 112, + "core-id": 12, "socket-id": 0, "drawer-id": 3, "book-id": 2 @@ -86,7 +86,7 @@ modifiers for all configured vCPUs. "cpu-state": "operating", "entitlement": "high", "qom-path": "/machine/peripheral-anon/device[2]", - "cpu-index": 112, + "cpu-index": 12, "target": "s390x" } ]