From patchwork Mon Nov 27 15:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747613 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aATXXn5z" Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E02B0D6 for ; Mon, 27 Nov 2023 07:28:58 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-5094cb3a036so5920093e87.2 for ; Mon, 27 Nov 2023 07:28:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701098937; x=1701703737; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tCPGBitG9/6KXdvU+lPUvXD7HIIGNEDSeEGVdElqkaM=; b=aATXXn5zw2+SiTVONWWSQn2wZSynq/ULHGaPjSxd8dCHxJNJxoEkvu9H9b1qP/9P8+ 0zt0I0Z0wA+wqotXrt+VDEf2SyxEBb8p6Nocd9hVDD5/i9HnFMyh3EvZF6UYI058fct0 caLtApejpL6YcSybj1XVQlM70888nBebK6IWRnLhEZxOTau4A8To84F5QzJ35z9bC4WA 9lStuVtgC2azDp6y47rtwKqFTRfp+1mCYB0vAyvSBkBgKA9zZJlmEbowubxc8WJ2rcKo 93/Bd5MnhRWd7IB5jQv6LqVnOazGA4XPzBJH4faKVHAct76X1GtWbeQaQSxIHl3Tqj+j lbcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701098937; x=1701703737; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tCPGBitG9/6KXdvU+lPUvXD7HIIGNEDSeEGVdElqkaM=; b=iOmn2HEaVtb9K3ikXJ/raXr/nn6/rDcTCabx/VCeDfZBSIcSWiWProz/MJux4ujU3k uyaNg7JYsn3aET51tCXxo48jjfN5gE+q3GeQjgwTyeLPqOJfJpML5W6f0k9/HrUK2Ot2 bnNJz5DX44PQocrixfKoTbz/DLU6YrRBJLtEu319l98Ids+eovGy0ugWky0H2IPXjASN tl9kMEESFh7fj1Uc6sH0EFy1gHfiC/D1Qxpv7PkCaZJOootGrxVZOuuG07Ye1mNHdR2F 1QAo9krbsarDinE5y2IvYZ1qcolCoVwJPbsYENJYdS8u52+JFVmGkKBEiaaxhrOdztz9 F3vA== X-Gm-Message-State: AOJu0YyWdA86jiev1dyNeNrRe9rgjf7mHOks0Ae80tdH0usnwpPsjyZH rIQ60PXpjtqpI9/DujG8aic0gQ== X-Google-Smtp-Source: AGHT+IH9HFjsaRyEGI/bPEJt0t/pme1c29F8+9ebs0nRfu5ekDAC+NwjiRH9hv37y5bc3wqPAZ2OmQ== X-Received: by 2002:ac2:4344:0:b0:50b:aee8:bdfb with SMTP id o4-20020ac24344000000b0050baee8bdfbmr3090897lfl.2.1701098936988; Mon, 27 Nov 2023 07:28:56 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:28:56 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:42 +0100 Subject: [PATCH v2 02/12] dt-bindings: display: msm: Add reg bus and rotator interconnects Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-2-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=10671; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=AI8ujGLZlBaJZlOW2pjBLpvVqMuO/BaY4E8wkJtK6AM=; b=92JPSK9FgauS056u7gnbDz0tlni42SCYcsIB7205V/h69eeky/CTMVYu3yBn8m9nzQflpHtdq QkP37nctQDvDO4bHhFeyPD3umxJLk4TKtT6t5EUgXCgzknfSc2Ms6b/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are other connection paths: - a path that connects rotator block to the DDR. - a path that needs to be handled to ensure MDSS register access functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG interconnect. Describe these paths to allow using them in device trees and in the driver. Signed-off-by: Dmitry Baryshkov [Konrad: rework for one vs two MDP paths, update examples] Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/mdss-common.yaml | 18 ++++++++++++++---- .../bindings/display/msm/qcom,qcm2290-mdss.yaml | 14 ++++++++++---- .../bindings/display/msm/qcom,sc7180-mdss.yaml | 14 ++++++++++---- .../bindings/display/msm/qcom,sc7280-mdss.yaml | 14 ++++++++++---- .../bindings/display/msm/qcom,sm6115-mdss.yaml | 10 ++++++++++ .../bindings/display/msm/qcom,sm6125-mdss.yaml | 8 ++++++-- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 8 ++++++-- .../bindings/display/msm/qcom,sm6375-mdss.yaml | 8 ++++++-- .../bindings/display/msm/qcom,sm8450-mdss.yaml | 13 ++++++++----- 9 files changed, 80 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index f69196e4cc76..c6305a6e0334 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -61,17 +61,27 @@ properties: ranges: true + # This is not a perfect description, but it's impossible to discern and match + # the entries like we do with interconnect-names interconnects: minItems: 1 items: - description: Interconnect path from mdp0 (or a single mdp) port to the data bus - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - minItems: 1 - items: - - const: mdp0-mem - - const: mdp1-mem + oneOf: + - minItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg + + - minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: cpu-cfg resets: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index d71a8e09a798..f0cdb5422688 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -36,10 +36,14 @@ properties: maxItems: 2 interconnects: - maxItems: 1 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -98,8 +102,10 @@ examples: interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; + interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>, + <&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; iommus = <&apps_smmu 0x420 0x2>, <&apps_smmu 0x421 0x0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml index 3432a2407caa..7a0555b15ddf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml @@ -36,10 +36,14 @@ properties: maxItems: 1 interconnects: - maxItems: 1 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -106,8 +110,10 @@ examples: interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; iommus = <&apps_smmu 0x800 0x2>; ranges; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index bbb727831fca..2947f27e0585 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -36,10 +36,14 @@ properties: maxItems: 1 interconnects: - maxItems: 1 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -118,8 +122,10 @@ examples: interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; - interconnect-names = "mdp0-mem"; + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; iommus = <&apps_smmu 0x900 0x402>; ranges; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml index dde5c2acead5..309de1953c88 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml @@ -29,6 +29,16 @@ properties: iommus: maxItems: 2 + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + patternProperties: "^display-controller@[0-9a-f]+$": type: object diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml index 671c2c2aa896..3deb9dc81c9c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml @@ -35,10 +35,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml index e1dcb453762e..c9ba1fae8042 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -35,10 +35,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml index b15c3950f09d..8e8a288d318c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml @@ -35,10 +35,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml index 001b26e65301..747a2e9665f4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -30,10 +30,10 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + maxItems: 3 interconnect-names: - maxItems: 2 + maxItems: 3 patternProperties: "^display-controller@[0-9a-f]+$": @@ -91,9 +91,12 @@ examples: reg = <0x0ae00000 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, - <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>, + <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; From patchwork Mon Nov 27 15:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747612 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MjKz4i9J" Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90370137 for ; Mon, 27 Nov 2023 07:29:05 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-54b0310f536so5338576a12.0 for ; Mon, 27 Nov 2023 07:29:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701098944; x=1701703744; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Dsjff4lo1TEsrq1gFW/fhWlByzdhetZPF5yWDTWUZEA=; b=MjKz4i9JEnsvpFh9NJbh6ao518pGLidS+riiMljmapXlIwc7jS7grGtgYOHWQJkfSw guCJlFjnd70xio2crIB3s+a536rpt6HzisaAIX3BSzROg93WhSULXqnx9aPxwVfcVdIH wMGSKhpTVST14FPmE33QU0mCM/J1+4ELP3PXgyVCBPeLI5yXOo8S1JnQz7Q2m22yXSVE dn0236y/E5S/OQJ9gLc/d0OW40q4G20w0qtyY+kNyVwEWZR+/Ll49eApOBfN44kf7Z0y ElP/3ZG6Ih5e/+b5DI1sXGTJOI8z7fvPDfX7v/W16VkeWzbY1Pcc2jt3X11Kxl+T01mt /gow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701098944; x=1701703744; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dsjff4lo1TEsrq1gFW/fhWlByzdhetZPF5yWDTWUZEA=; b=w+RKNxftxjviOQxw1yvJ9Ocfxgycnb1N4bqmdkRjtptrYyIt92/NCS7KQh3t82jG5W yRRwQqg9PJZw/QxU7+5qBA7qjQKtHjVFbXrN6R6XUbOG76EXZwcVJJLeSvSbd1nh/5ih Xdy0eH6Of2qZjrCOwEPPSEdFaHH2VRyEAsX8kzjxL17gGvKJnZHCD5Qv+Bkqg8zsN6AN KahpYBgVQ64uAKcwpozD7UY2bZrvpZ8DlHIDMkxThvZuGdvsyrxdl2U3pZ01uYbR0qoP rXtarFxRUFHrdUcqIrqX2pCAH3DiUjj6FF9El4ikYpfRoPeHnMdVksPNAQZMMbi8zDOY QESw== X-Gm-Message-State: AOJu0YzO/bPz442jrfBKS/7RYyogHjs/llClVBlAQLCSmSDXRJcG5Y9Z BBqjWgMtGY+gaSHwVN4U9p2o5g== X-Google-Smtp-Source: AGHT+IFOyIrlG3K4TKUYS2ME/41gHY9uKSnDmZkZO/xmnu/DRtbRQqQLfmFgD0DWgrRTWqt07Bphiw== X-Received: by 2002:a05:6402:b08:b0:54b:35f1:905 with SMTP id bm8-20020a0564020b0800b0054b35f10905mr5607319edb.3.1701098944044; Mon, 27 Nov 2023 07:29:04 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:29:03 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:44 +0100 Subject: [PATCH v2 04/12] dt-bindings: firmware: qcom,scm: Allow interconnect for everyone Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-4-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=1156; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ATWzTDawV1rfiW1Rmh2AEVyFtBtlEoO5VeMvQ1CdaLU=; b=d2uxm8koLiSmmdjKdjpShjLXryrZ+gjNkqEkIxKGxUdhaPhhQ69YN5mCvINv/crH2NFSPaxwY vbIbYzQoWl8CAPM339TI9Ayh67M741P51t4zrDzpIG103JKmvS20sDA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane. Allow this property to be present, no matter the SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 0613a37a851a..f3a87a8426d0 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -178,21 +178,6 @@ allOf: minItems: 3 maxItems: 3 - # Interconnects - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,scm-qdu1000 - - qcom,scm-sc8280xp - - qcom,scm-sm8450 - - qcom,scm-sm8550 - then: - properties: - interconnects: false - # Interrupts - if: not: From patchwork Mon Nov 27 15:28:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747611 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UKonYcAR" Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AD06137 for ; Mon, 27 Nov 2023 07:29:13 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-507c5249d55so6617090e87.3 for ; Mon, 27 Nov 2023 07:29:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701098951; x=1701703751; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3WME6ubitd3vxaAOMdHVezdwhed8qbighnDEBO169Ec=; b=UKonYcARxR2F+oVvEtIZffRRe3YUImWLduFZvNkzJxKbi4hJfZa9bu411c5qWtcmko 22xkUEofvENTiEvu7JUT0ZcgBGZ6wDCWgAhw+N9VDkHUyWR+rAuK0rlNiYTF+RHLY5Z+ D2LKUNClcPN30hH82qlHHr0EmGXhFl6sViSnQtt6JfvN95A268ur8+AysSUfa7uVsC1I HHH7e0h4OMAd+VzCIqh/1F5lmA6xXs+TlQB0GeDMGtjDyyk9CfvHIiBvooUBnd1OqHQj fbGrtTRQFsfp8PTt0LpS/dgrhrNQ59PY8mRyTY+r/XmlZru6e/nBDe4Wu4MkmnthA8Ed r+VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701098951; x=1701703751; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3WME6ubitd3vxaAOMdHVezdwhed8qbighnDEBO169Ec=; b=bT4f5eaSa6w2Qaqkj74JGrxKHR6VPqy/AlRNeJXBgfvVAHoFDhryFbcR1KUkdmk5nv MPhOAMFkZ62ZLyRuvpDEid93nkgB8jcXKcAOVwa2XWsiOk/xvwUHGrKh0pc81DfRyoAP 2Nfyn3qqJaXW1gr0KQ10z32oHuoZ9o9DezAvkAVA9CU6xjVC8skV7ud3NvpgTavXv3yq 0cS+gJJxgGk4FDVxr2OQZC6tps5uBBzsSXCHKG6Owi6UFMuBjMn5DbQB4kSrRuGxtVr8 MNtcawzsIaYUfQNbr4N72MILSXYHGr5hERCCd3Z6OkMP1dDgFeWaDZTqAUuOGewjmYvm YOfA== X-Gm-Message-State: AOJu0YxINjGOfbP/wSnm6pgk+NnSOqDzzvHyA6et4VGSuRedjj7BE0tH 15JsnafDTbmVIuxOIyQlCZtYfw== X-Google-Smtp-Source: AGHT+IH9PASqf8+9MS/t3uEvXsv+5J3bCkLHJgeNIv00zKAMBrW7rkqqrSRlRaaexUly2vTsBuJ+TA== X-Received: by 2002:a19:ac48:0:b0:50a:6fc5:e95c with SMTP id r8-20020a19ac48000000b0050a6fc5e95cmr7956561lfc.60.1701098951013; Mon, 27 Nov 2023 07:29:11 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:29:10 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:46 +0100 Subject: [PATCH v2 06/12] arm64: dts: qcom: sc7180: Add the missing MDSS icc path Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-6-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=1145; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QxbVxThi6gj4JqQP8V9LpJsjR/myuVOnIJbwHX7amYU=; b=fS2uPRd3j9acJg11U61tq9XVN8ayomlEw9d5ATm43L3nTtaAyensMfnnnvE/jpMI6SBpUTurk TEzmocPClnSCqU9FEoaODlLAlpLeRUPaiJm5qFPFJKjE9fYnQKYi6tN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one. Failing to provide it may result in register accesses failing and that's never good. Add the missing path. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 11f353d416b4..9664e42faeb1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3100,8 +3100,12 @@ mdss: display-subsystem@ae00000 { interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem"; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; iommus = <&apps_smmu 0x800 0x2>; From patchwork Mon Nov 27 15:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747610 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hju7Sgcc" Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 391B11BC1 for ; Mon, 27 Nov 2023 07:29:20 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-54b18c9b21bso2760117a12.0 for ; Mon, 27 Nov 2023 07:29:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701098958; x=1701703758; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8KqUGGYBrVzv5cHQpnzoWSbk/05sDmdEfZhra6WsNz8=; b=hju7SgccjZ9zmKBukLGv7t8oBdRj8x+Zt6VPbvgGTESbRi8WEGcK6j33/j3xySr9j9 ZsV2m68CFMgz9H+kJRRVcD6E5SGp+t1Lu57gxz25ICh7A0kugMSlhX1Qa4SX0qrbF4qT 7tHnHjr48rfsYUOeAYyvp1ubWYpC+ilFC0oPoje/PQ/pH8EQj8dDySWvsDPY7CUgUbOK xqbNQqzsWkNBgEZDBwNgZ5KpqIWw5M2CR7EYX2hDyGw9bA95PMIW5KL4CazCaM+ET043 AQHhENVbDQX2rW2IN47/QX98e8Ec6XSLU4kz2isSEHMuxXUJkL4UXeGuIzKr/9umTOT4 f8RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701098958; x=1701703758; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8KqUGGYBrVzv5cHQpnzoWSbk/05sDmdEfZhra6WsNz8=; b=Y8S6MaBgd3WOP4PbIPaOa5wd4QFfxvxnt7yJG+9RKb2Vo23EECt/7T2GX5GK6l1eAY GqQpCnyP2+IvosjoJOxDt81HVLNxyoCt/utJVrUXajoSpQ82Fw4oEOo8CSqAxkX9hKKv EZbYP3DkaOiqbu9alVb6hc1FKERGRG9rMaCm7nmlnXjPadsYII6klEatr8oceUWHMsLU M3EcU/N2WG+SbV8eUhCep5DZZDkye6GADL5/eH28iaeDv+jhjnYiqqWetjrYzcwOMs8k fRuefyXK1iwFrH/io/RKufG2MvTpRj1xwTg5BZJEWjcHPt9Q+yLXRqMhcSfJPneVZdos FsYQ== X-Gm-Message-State: AOJu0YzY4XfycKNRXUbYzlcecej8P+2PPv4L8IIV5NEt2RVnqa62R4Aq uQOCb/qxwSaq9OrmjpwlXEc+9A== X-Google-Smtp-Source: AGHT+IE34J1yrZKyVnjv9I0/jaxeMheQIdVlY6+QPWz/y7bn5Rjj11hn2KtJFU/SMs8gA930OCx/fQ== X-Received: by 2002:a05:6402:1359:b0:54b:22a1:e6fe with SMTP id y25-20020a056402135900b0054b22a1e6femr4926690edw.7.1701098958210; Mon, 27 Nov 2023 07:29:18 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:29:17 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:48 +0100 Subject: [PATCH v2 08/12] arm64: dts: qcom: qcm2290: Add display nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-8-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=6335; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BTvepHr7en8R5ipJOnsIKxJu6757PVnhk3uZkFoZtMc=; b=szvoMpvK+ObnNJ6LxCnrwTffnTk1GdVPeI133ELHQNKr8OXo5e88CkULH498pnI8joR0XUbFg my+j2X4g1vgBDywqUYycb06FrY3cEMPvnB30RoupdgclF+VA8+PJDfG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the required nodes to support display on QCM2290. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 214 ++++++++++++++++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index d46e591e72b5..a3edc4667cc5 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -5,6 +5,7 @@ * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. */ +#include #include #include #include @@ -1105,6 +1106,219 @@ usb_dwc3: usb@4e00000 { }; }; + mdss: display-subsystem@5e00000 { + compatible = "qcom,qcm2290-mdss"; + reg = <0x0 0x05e00000 0x0 0x1000>; + reg-names = "mdss"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@5e01000 { + compatible = "qcom,qcm2290-dpu"; + reg = <0x0 0x05e01000 0x0 0x8f000>, + <0x0 0x05eb0000 0x0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "core", + "lut", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@5e94000 { + compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x05e94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + power-domains = <&rpmpd QCM2290_VDDMX>; + required-opps = <&rpmpd_opp_nom>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,qcm2290-dispcc"; + reg = <0x0 0x05f00000 0x0 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk"; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + remoteproc_mpss: remoteproc@6080000 { compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; reg = <0x0 0x06080000 0x0 0x100>; From patchwork Mon Nov 27 15:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747609 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="L3TAiNK9" Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 211E41FC0 for ; Mon, 27 Nov 2023 07:29:26 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-54af1daf6a9so5861782a12.1 for ; Mon, 27 Nov 2023 07:29:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701098964; x=1701703764; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c6/lhVmHX/sXs0e46ClnnLz5Erfr7PRCNkXawgtymt8=; b=L3TAiNK961B+e2vdd8O3nLAD/FSNmUkcpOVDNA5ge13EgQfaTB34fAlqSa2aNNYjHE 9CwGe32LwwOE/PzYvA07dGL9XKLGAqmw7svOpNg6OcJKDBf2zejUBK3SE5IiS/VenLv1 qHeS6sd4wFej+qZhjtKucQXAD169UAYskstSVCvjQV6Z6NS7hRVWO/S2fuBh60c54PU/ ZKtI3zd6LGGfbv01Wer4xD0uvF0t0ClAhK932BgdOAafJuE7TIiU2oRk/UVyLh/5Eonb /dB46YzLeo2Mcnz6BnWOs9D7fI/ck1XDaMsXG8vpNLcedOWXZ/ZKA+kUIiSJ+lU/7eS4 DoGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701098964; x=1701703764; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c6/lhVmHX/sXs0e46ClnnLz5Erfr7PRCNkXawgtymt8=; b=oCrZp7PDqT9euLCI/5V41TE/YPs2zckyNlOlgW93x4oNrU3VZzFD7D6xJlUIL8hLQU HTbrmupwI8oGGy8CxL434M6U6FaUkfQpJl+kYc7SkP5eMz6X5HyonLadOthvLnyCaVx1 iHkhMapQVvm6r/KGcTo7i49VNnKuEiG3ZbXyToSf5pyoBEMAIFA1ef89c3Z352EY1T4l +5HwTzjuLl+DSECBGmqvqgln3OxPNvQ5LJgXRVoNELrP3qqbzCDq8hoqZ5dXhYjyHZXC yAVh1gKBKoHX3Ac6rDemAdVz8cimyX3GYJhT6XaNDqthWpY7Y82HpujIqj+AOjRxN8rY 3QdQ== X-Gm-Message-State: AOJu0YzrvMEj5uHRxSZlxNjTOvnF+0UEyb784o/Bt8oVDuVIghdBejLT e1i8VZ5HOqiTK4ncXm+s3K1qSw== X-Google-Smtp-Source: AGHT+IE12MRZ+K4+7Ya9XYiXHy8f8LRtqIz85wDPP5rtzWUU+R4ruteNN5riVPicBCMiZlt8klaJfQ== X-Received: by 2002:aa7:c401:0:b0:54b:3bba:8372 with SMTP id j1-20020aa7c401000000b0054b3bba8372mr5621717edq.5.1701098964534; Mon, 27 Nov 2023 07:29:24 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:29:24 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:50 +0100 Subject: [PATCH v2 10/12] arm64: dts: qcom: qrb2210-rb1: Set up HDMI Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-10-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=2344; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HG+qKKvGUGteXhS1Efd/CaFsVpJbWzVwdo27Zc2OxfM=; b=bScEiiVF7H6OgG93/bEfiiBpKcPZrN5AKqa/34nrmj67oU8vvcbgzuavBX+sO/7vUBhqlFj4Q H4dnTJ831zLC3QqIiTvg8eNp9DXstc5E1AfZnn/Y3db9beLHUlgcQ+X X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the required nodes to support display output via the HDMI port. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 86 ++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 94885b9c21c8..ac6584164058 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -40,6 +40,17 @@ key-volume-up { }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -158,6 +169,68 @@ vph_pwr: regulator-vph-pwr { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_hdmi_out_1p2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm2250_l5>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &pm2250_resin { linux,code = ; status = "okay"; @@ -377,6 +450,19 @@ &sdhc_2 { }; &tlmm { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; + input-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio46"; + function = "gpio"; + bias-disable; + }; + sd_det_in_on: sd-det-in-on-state { pins = "gpio88"; function = "gpio"; From patchwork Mon Nov 27 15:28:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747608 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="n9UejEQ1" Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66B0D10C1 for ; Mon, 27 Nov 2023 07:29:33 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-54af4f2838dso4182451a12.2 for ; Mon, 27 Nov 2023 07:29:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701098972; x=1701703772; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6AuHxZr8x/Uk1Y12/gMeKhnjQeN0t/qZ6GCe7PtBack=; b=n9UejEQ12RcJS6EOwUkVD9IE4V2/Ax/KY/sFWYINrIEji+JRelZdBxGAAhKGQXljGU PpnwzX61v4UBxNQ7uaBVThcSBg55ZPlykvhrHVc42D/c95ipz0Dn5Fuc6UExFeMfBHQi 71bdxk9tFBNPlzRTEf+Tz8CbHfb+A16OcM0p3sH7avK81LGmoL8MtpYUoQegoP+Km1RU T8YL139Si74MOTjwU3JyAGAA6wGFRWJSMj12NJFjElOCwqOFmLfx53B00I4QrHKzF589 sou1WIkASZhK3lrd8iCWKWJHNxDjAAClZyQuaUqSwYl3ZOKJdSlwixjGipNlTGYh1OK/ Bc5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701098972; x=1701703772; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6AuHxZr8x/Uk1Y12/gMeKhnjQeN0t/qZ6GCe7PtBack=; b=r/Avv5fkp3zaamHTInn/XV+B2h2rKYlDXlSEXfSzXQeaBAcc8G6xH+VXnDjkh+eegd 12eHU/aLCFGWBBtDZTR7qDvF3xEP4Qbut3h0DIFCoHudmCrxSVDlN+LLuaiKiSaJ9L3u p5dsW/RJsnf0blzQVEPnpnfg8tOpVGWfZtEfy+yKs1dZjikAKnNkXFEvuJkvIr4A56eq UcpziyyA05LiH4ievXJOhSiRYuzEIOHn9G9JKDkJ+rCeua8vVMJ2EMh1JQo7/FJNz93N Jq9buOMADMYe7Or8lsgUabUI7qB7F1r9QOwQynSG6SaGLcmaYDLFjX1f1zpJsiyxO2g0 V7xQ== X-Gm-Message-State: AOJu0YxlLjFf0QW8Y1wpWP0pMNAvJ/ef0qPTF+8UQxmmle77tygfIx37 smFqvvlYzJCiNcISSRWGWcyZYA== X-Google-Smtp-Source: AGHT+IEjg8fNoQ7pGDMxE5+HZKEN6r9zGLEH/tW3tKBdtUVnvRcZMMfRiedeZ6EJ8qo8zRPeowbcFw== X-Received: by 2002:a50:bb63:0:b0:548:55f0:b5f2 with SMTP id y90-20020a50bb63000000b0054855f0b5f2mr8631879ede.6.1701098971847; Mon, 27 Nov 2023 07:29:31 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:29:31 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:52 +0100 Subject: [PATCH v2 12/12] arm64: dts: qcom: qrb2210-rb1: add wifi variant property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-12-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=1845; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=F+2+KPEjbmpD3TQ3tmcuJpeM3OLd440fgCNNO64cW48=; b=bLy6ijre+9R3R+FKK/1GG7JMsEi9kVICNx6m8/ep2irrVHKiERIRYGcphHFdybjbbOBmXg5y7 ne+m1DehqnJCCueb5BUTJg2eKDJXfBoj0gZYp5ymD7+HN2P2QtRbnl4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Dmitry Baryshkov The RB1 platform doesn't have board-specific board-id programmed, it uses generic 0xff. Thus add the property with the 'variant' of the calibration data. Note: the driver will check for the calibration data for the following IDs, so existing board-2.bin files will continue to work. - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120,variant=Thundercomm_RB1' - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120' - 'bus=snoc,qmi-board-id=ff' For the reference, the board is identified by the driver in the following way: ath10k_snoc c800000.wifi: qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 ath10k_snoc c800000.wifi: qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 ath10k_snoc c800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc c800000.wifi: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc c800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc c800000.wifi: htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index ac597eb3fe9d..bd7bcf803654 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -535,6 +535,7 @@ &wifi { vdd-1.8-xo-supply = <&pm2250_l13>; vdd-1.3-rfa-supply = <&pm2250_l10>; vdd-3.3-ch0-supply = <&pm2250_l22>; + qcom,ath10k-calibration-variant = "Thundercomm_RB1"; status = "okay"; };