From patchwork Sun Nov 26 23:27:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 747441 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=canonical.com header.i=@canonical.com header.b="MocMhaDo" Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B40A6111 for ; Sun, 26 Nov 2023 15:28:07 -0800 (PST) Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 12B6A40C52 for ; Sun, 26 Nov 2023 23:28:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1701041286; bh=UTWv7B0aMCLXIjGIp62HkL6y/eNl9IP6Uhar24MKibc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MocMhaDotGAeHqTwO11kml/FOxZkPEUMFvUX8JrPx85W3/gTYP2eK5dwI0vYTIfLP nc29XfQ8UVOQP8YNI0RBVPOxBgqiwpu6bVKSM1p4zq4isdjsU0yIP3QsCeP/75iCvM cukL9CZ9TI1+JXp6/7e15eui6bX0jQiX98+y5lcDkm9sDudGXMp+odGcUaUMklhIlg t4Jd2LQIaWi4gmLh8o5gDX7yegpzAioajjqVboPJBCaDs6fpIDzZnNR5j8yn16NH66 mY/UkPWBKtWK488JPcnPZ9VzGvslnmWeDOHg+h+tfHP9r7zHFYH9dlYlEzjMEKqvnx CW4LnUlGFyl3A== Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-1cfaeab7dafso18348455ad.1 for ; Sun, 26 Nov 2023 15:28:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701041284; x=1701646084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UTWv7B0aMCLXIjGIp62HkL6y/eNl9IP6Uhar24MKibc=; b=vR6pVNjMbXG/nPsTUKod2yZdkdc/Q8JjSZ4M0kn4w4kDKuuqYcBhDn1Nbw+PsnH5HL iMo7ReDOO5fPCvXM59fdXDcFutE3wcLKU6qRg68KfKywi3HXLsiZ96B/SZ8Fzd3FgvqB R8QQq9m618bYBIslCHofMhBuXVVQBXT3FyCpJXhuQ2g6mKOvXpr7Augw5/1cnfeVKUGU sD3+wrMP6ZD4jaaz8pLdDAPFLq6k4vggD6HnxGThGTY1hO5ynXo9uE9ncHsY17SS8ILN C1tYgwVyxC0PvWX+vEC67FK5AlSMimGe+9gchSkHDt/JYNcfdhy44071PjcCzB2G+E3Z 626w== X-Gm-Message-State: AOJu0YxM+tbQNixV6c4e3maQJhhsv0S7zRE3Dr0ZGt6d+Oqi+LEjVpjB cfhYZb1AhCSgqSi0E70iuasyEqC5opPG3SVB2knwZw3667a4tfZZo4JATqqWmiuG373XlKa2e5R DcQ0dcLwbwAtzl9SakNAWne3KWExiCmIhk/s7mEU= X-Received: by 2002:a17:903:2308:b0:1ce:6312:5373 with SMTP id d8-20020a170903230800b001ce63125373mr9452857plh.0.1701041284715; Sun, 26 Nov 2023 15:28:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IE43ssElCwc1AHbafPfLyauBD+DF8njBdZmf6dkxFwE+D353fKdfdo6BtPGfyggI8uwjzzEag== X-Received: by 2002:a17:903:2308:b0:1ce:6312:5373 with SMTP id d8-20020a170903230800b001ce63125373mr9452844plh.0.1701041284377; Sun, 26 Nov 2023 15:28:04 -0800 (PST) Received: from stitch.. ([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y10-20020a170902b48a00b001cfb52ebffesm3123853plr.147.2023.11.26.15.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 15:28:04 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Cristian Ciocaltea Subject: [PATCH v1 1/8] riscv: errata: Add StarFive JH7100 errata Date: Mon, 27 Nov 2023 00:27:39 +0100 Message-Id: <20231126232746.264302-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126232746.264302-1-emil.renner.berthing@canonical.com> References: <20231126232746.264302-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This not really an errata, but since the JH7100 was made before the standard Zicbom extension it needs the DMA_GLOBAL_POOL and RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. Signed-off-by: Emil Renner Berthing Acked-by: Conor Dooley --- arch/riscv/Kconfig.errata | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..692de149141f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE_JH7100 + bool "StarFive JH7100 support" + depends on ARCH_STARFIVE && NONPORTABLE + select DMA_GLOBAL_POOL + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + select SIFIVE_CCACHE + default n + help + The StarFive JH7100 was a test chip for the JH7110 and has + caches that are non-coherent with respect to peripheral DMAs. + It was designed before the Zicbom extension so needs non-standard + cache operations through the SiFive cache controller. + + Say "Y" if you want to support the BeagleV Starlight and/or + StarFive VisionFive V1 boards. + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE From patchwork Sun Nov 26 23:27:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 747440 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=canonical.com header.i=@canonical.com header.b="USWA50dv" Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 917EB182 for ; Sun, 26 Nov 2023 15:28:21 -0800 (PST) Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id C8BA640C4F for ; Sun, 26 Nov 2023 23:28:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1701041299; bh=O3TPicaObXUf+CQ2/13bF4S5EM9ZMGJpI/eXjOZpsCQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=USWA50dviKu0ODjnStxQ60N4E+f8SjbFwNwDDVLiIrVYhRORgfsiYUX5/sOvV9Ghg NMGNopa+TC+kpym7UssVLMivTbm7UhptxPPap6oDi4uwfgouGTA3bTDQuIy8t1j7ut ZrOCi0Vy6bUFJ24TWfpNJx0voiCHDXFgC7D3nmUzeGUsDj91KKHdyae3ZRU0LDeBhv wIanGTdK47sawznoTpUQi+50wYdYpKplSzyZeE/KM0+XA9X0NL19h2eXzbdrR0PCLy IaqfOF9WT49ahcqsHQq1IZvIz2z5QVKtkPIYCqmwBGsRWJR07ZkoVTD781KZkskIxO HJV4fH3Z1rDsQ== Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-5c5d72fb5e6so247752a12.1 for ; Sun, 26 Nov 2023 15:28:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701041298; x=1701646098; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O3TPicaObXUf+CQ2/13bF4S5EM9ZMGJpI/eXjOZpsCQ=; b=xO+MOmxNLePo5naTMw/CGCMlLf9FVgm7+50/Nz/UbeGoMFHQUn8gMXOnltP4ALvEvb aUeo4WPD2EZxLCnK6yBTIrECo5kl4DLS1GaTMvK2fFN2WJnZBTaOBPfHeLY2TzWlr9B4 KjGX3glqUO9oSPuMwRZRtVdnUDZ3HjV1uFRJvX70LJJSGXraXpQo209AtyAl1lxcuYl4 DXFzpl6R6lq+rKVODqqv/qgeFEvCwPp9CVNa6HYxMBiNK8dW91dMn3m5nHLX5ktsm5Zt dGgxuHBHsiU2kSPCcNoPHRyjUPYe1fW752zksz9t6r4v52gn3JORNh7oa7C2nIaC0OJo pIbg== X-Gm-Message-State: AOJu0YzRZsvWUup4MlSOcS5neXsBLH+uSL8UN2ScFvlYY6yOkvCZx4am nY7n3B8xfewVlsOxW3rhEKAOfHYLpd7mNLbKnkEMH5uMYw27ISITDhk68mgtRhiR8GAJzQ1UeW/ Ry1ZdR8tPCWyCJttgDSPDxUx43hnwrx5K+16zGNw= X-Received: by 2002:a17:902:be08:b0:1cf:747e:89c6 with SMTP id r8-20020a170902be0800b001cf747e89c6mr8786550pls.26.1701041298544; Sun, 26 Nov 2023 15:28:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFFuQM7m8wCn6b39aPT5b9YXgOSCYAQDDWmZ8ylvHuaFNyspEtnWGrMk3kxYgR8lkzRlvz2bg== X-Received: by 2002:a17:902:be08:b0:1cf:747e:89c6 with SMTP id r8-20020a170902be0800b001cf747e89c6mr8786540pls.26.1701041298276; Sun, 26 Nov 2023 15:28:18 -0800 (PST) Received: from stitch.. ([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y10-20020a170902b48a00b001cfb52ebffesm3123853plr.147.2023.11.26.15.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 15:28:17 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Cristian Ciocaltea Subject: [PATCH v1 3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs Date: Mon, 27 Nov 2023 00:27:41 +0100 Message-Id: <20231126232746.264302-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126232746.264302-1-emil.renner.berthing@canonical.com> References: <20231126232746.264302-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Emil Renner Berthing The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a40a8544b860..7c1009428c1f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -144,6 +144,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; clint: clint@2000000 { From patchwork Sun Nov 26 23:27:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 747439 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=canonical.com header.i=@canonical.com header.b="JQBKF97m" Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA5F8D53 for ; Sun, 26 Nov 2023 15:28:34 -0800 (PST) Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 78AE93F885 for ; Sun, 26 Nov 2023 23:28:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1701041313; bh=x/4VKc6j7ZPLGeNJb06p6pcCmpUDLk01xwbpFjzzvZw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JQBKF97mNX55Yf3Gyc2h2E3Ppw+eHmmbNqFuFmM/Zhm126nXJhsKyqc0xCm7nuL0w aG994RUfDT5oNwldoNpSR60mqWo4rQVXXwQHu8+TmprsjuF+HIZbnDxhCu8eol/1uP ehsYxm1WzCaC+Ts48Fzou0cRMWTucocEXyqrONyIT6SkuhoDRxPa+7QNtxUYeidORC L7T7lP/CuVHI2wjsgAt1Or+CXFo/dKSjH7z2GMInI5iMFkvQQsVD7uZSY/EWaRgQHu NJmsliRbOwSkHtSQkjS8P3vjPv+QwKD0p3yrxNYmIEq0RHBkyfbCPPBxKWOHUPqAAO Y/VNxZ0R3j4Aw== Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-5bd26ef66d1so5042573a12.2 for ; Sun, 26 Nov 2023 15:28:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701041312; x=1701646112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x/4VKc6j7ZPLGeNJb06p6pcCmpUDLk01xwbpFjzzvZw=; b=ERJphmkfZ2kloS2PwsjVT722KiVNfeUPeQbffuWzJFFHERqBeh+mEdk4UcpT42XJt+ lELJcyPAjQSNeVpyNmsHqmFdxZ1v4L/Tv5cLeLtz3CmA4Psxqh39+sgDlKPkWUEt6kEt igCZljqhpFA9FPW1eNc+xasCT4Q+W0C0jojWb+76GlQykRTA1fZMNY46NoljBpDyOGHd gIMSqf4sxQJaK1kcrqAp5NzZ7SR8SUVKVNpEsKrZclYtvflxXiErQqsehK8uNJkbiD1P FZz+QBNxgu25hkTYc53N5jxq6sBhIQ7RXFzoXA6mdXw1vrrnpHgp0CRjcQUR+1oTiwgD 5AkA== X-Gm-Message-State: AOJu0Yy8QOdQS2gJDhR3SY67Zq/bjUs3q8TfXWvsdVVsKg7v+EoNYQI6 pl6iMNru2X1FsxOxBMkUncQxKoB1WedJAQ6cGNjjBjKg4PMtth0pQiP2KaDkmtg35YxoToEr1ap IfsnUoYEDRHu208jSo8DSPhA568OdtpVyyO85Zv0= X-Received: by 2002:a17:902:ab94:b0:1cf:b6a7:67a3 with SMTP id f20-20020a170902ab9400b001cfb6a767a3mr5596105plr.56.1701041312180; Sun, 26 Nov 2023 15:28:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IGn7gI9RzWm5JEwz0gkJGEdgyWBwAAAeo20KFp29UD271sxXxpOWLxGNhlLdPN5ZwfEX2jcYQ== X-Received: by 2002:a17:902:ab94:b0:1cf:b6a7:67a3 with SMTP id f20-20020a170902ab9400b001cfb6a767a3mr5596096plr.56.1701041311896; Sun, 26 Nov 2023 15:28:31 -0800 (PST) Received: from stitch.. ([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y10-20020a170902b48a00b001cfb52ebffesm3123853plr.147.2023.11.26.15.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 15:28:30 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Cristian Ciocaltea Subject: [PATCH v1 5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Date: Mon, 27 Nov 2023 00:27:43 +0100 Message-Id: <20231126232746.264302-6-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126232746.264302-1-emil.renner.berthing@canonical.com> References: <20231126232746.264302-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers expect to be able to allocate coherent memory for DMA descriptors and such. However on the JH7100 DDR memory appears twice in the physical memory map, once cached and once uncached: 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached To use this uncached region we create a global DMA memory pool there and reserve the corresponding area in the cached region. However the uncached region is fully above the 32bit address limit, so add a dma-ranges map so the DMA address used for peripherals is still in the regular cached region below the limit. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Signed-off-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..3af88e6970a3 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -39,6 +39,30 @@ led-ack { label = "ack"; }; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma-reserved@fa000000 { + reg = <0x0 0xfa000000 0x0 0x1000000>; + no-map; + }; + + linux,dma@107a000000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x7a000000 0x0 0x1000000>; + no-map; + linux,dma-default; + }; + }; + + soc { + dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>, + <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>, + <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>; + }; }; &gpio { From patchwork Sun Nov 26 23:27:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 747438 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=canonical.com header.i=@canonical.com header.b="FZoeHXHW" Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D75C118E for ; Sun, 26 Nov 2023 15:28:47 -0800 (PST) Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 45AD940C59 for ; Sun, 26 Nov 2023 23:28:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1701041326; bh=3BV4Vz9z3QHFiX3Dv1bjv4P8f3k40Tur0+jRMIWhjwA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FZoeHXHWvyz/kKxWZ6nr5oB4aFa9WsY+qk3Wv8LVQj9uyUcoJgP+MSCse8L//XXhI cz5BhPCDmHQYL4D9JG41A2tQA4/1QgmdoQJryJQQcshLXcgCyby1nOUidDxLkKfPTf apNH1sVwOstou57IwQHut81xyexvY9oSNjjo5IS3frF64EgKmcoaygRP8+Zp3ABYNB vclZhZkwl+K2ApRdAEQTuW/oAHadgakkAgDuKAfmgjI9Z6XoR+hzvtY44z5Dzbqy+V uKyHdFU2I2cFHYOPF4odsIb1+dIpluTRf9Xz4LO0wkV3RxpP2TCnMEHh8KOahhT9Z1 PBHC7ofGKSg7g== Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-5bd18d54a48so3562605a12.0 for ; Sun, 26 Nov 2023 15:28:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701041325; x=1701646125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3BV4Vz9z3QHFiX3Dv1bjv4P8f3k40Tur0+jRMIWhjwA=; b=JLSdbnPqWzqcLOAIHLadTZf4Y1gwkabEASdbD6j3f3BSxHctTLXnwTzlEQVZWpF6Ay BTAGf95RU2Jdow8P8RHjfA4ZeuKX5j2b0CqDOzLPhpGoFzjIuPb36LmYDfvmLyNUgNWE n9kK0219afv+XF9Shc5r59gjcmKdEhw8eV83G1G/yp/Zc22gcY/aa+dmvGBWxpMQu/sX irAT/zdQFkCZcwKiKzb3jf3HaOoGMMJNfoBZ+zofHZM/zx9dketRuS0znocqhEESw6IS kBUKBgqOUM7G6clGUd2QtLIxzOm9rWzCjH41Sbz7f96MwTfSeiqozAd+TyE/4AAsY8L0 Qc9A== X-Gm-Message-State: AOJu0Yym1c+wX1IeB0OeFgz9sd2OZlWKYiJXPq5bBCJdBbYMMd6zJ5xm LC01XI1sRzt+Wyl3X8kjfN7+rkHI3QJfVkwW763QGo8aWNgGxfYLKxN3ONyAmTHEhjT2lRIbcCp uFn1/oyWeisKql+G+WcjjgSzNOX9FTDaiJxq4nhQ= X-Received: by 2002:a17:902:efc5:b0:1cc:32b7:e5b9 with SMTP id ja5-20020a170902efc500b001cc32b7e5b9mr8690141plb.67.1701041324949; Sun, 26 Nov 2023 15:28:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IFu5REQhM9BvA/Q6QjZJDOHExkoWf96BeljpTfWoUEfeaxHnVUPLtF62hI5iumuW9CPgiN14g== X-Received: by 2002:a17:902:efc5:b0:1cc:32b7:e5b9 with SMTP id ja5-20020a170902efc500b001cc32b7e5b9mr8690128plb.67.1701041324714; Sun, 26 Nov 2023 15:28:44 -0800 (PST) Received: from stitch.. ([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y10-20020a170902b48a00b001cfb52ebffesm3123853plr.147.2023.11.26.15.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 15:28:44 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Cristian Ciocaltea Subject: [PATCH v1 7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards Date: Mon, 27 Nov 2023 00:27:45 +0100 Message-Id: <20231126232746.264302-8-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126232746.264302-1-emil.renner.berthing@canonical.com> References: <20231126232746.264302-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pinctrl and MMC device tree nodes for the SD-card on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-common.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index 3af88e6970a3..adcdbbc4f57f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -12,6 +12,7 @@ / { aliases { + mmc0 = &sdio0; serial0 = &uart3; }; @@ -108,6 +109,43 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + sdio0_pins: sdio0-0 { + clk-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + sdio-pins { + pinmux = , + , + , + , + , + ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; }; +&sdio0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>;