From patchwork Sat Nov 25 14:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 747256 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=edgeble-ai.20230601.gappssmtp.com header.i=@edgeble-ai.20230601.gappssmtp.com header.b="SxizX2Si" Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5426CD3 for ; Sat, 25 Nov 2023 06:40:31 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1cfa71b6029so9629545ad.1 for ; Sat, 25 Nov 2023 06:40:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20230601.gappssmtp.com; s=20230601; t=1700923231; x=1701528031; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8ClHDKk94Mp6MkLZWS45aw08xTZcLTQDzkuejmENcr4=; b=SxizX2Si5imw65YeL7RvFiD3vpcU72biIJqomKsBLz3BQsH0BYotTcd4bodBctpJ3X A1TSQ7O2+D+ZomcB31gs0LgMnAxSAbwJ9BAH0jGaPX3wPhuJ7U1nmOkdTt5vIB/FW1Mf yaHG9QgX4Gj9/RUchIWhiI/lz6w+NydoyWHTHnevp0mRFA14JPTUl2SpJ4+eq9eidprA fjtrUCkLGQUROYVNaerA69zBPW0mkci1Ie54DYdc5IJhiDTPr9Z3tioVPJRogEj17oYr SE0e+IOxx76BtmDb6aAVRNYSMt3skQlOcSWH70CcZc0jBj6IDIuZBad9wDdy7ZxXUEll lVDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700923231; x=1701528031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8ClHDKk94Mp6MkLZWS45aw08xTZcLTQDzkuejmENcr4=; b=sn6Aw9bzRgp2lQMTLwRkWpKJdCoplOvVtGFZeDwPm51kWIr4EJLkD0ldkjfZ9ukS1F 8sT/qmkX5ZNzuoB8Axpi/oCUbNlzykd8XAL4kig6scZpwOBbJ/4oHh8yYRaWwS0kW/gg STqdhATRgJU7+uAmfbVNmK/hIZDm0faerhlq6HF9RgcH8VyLh37hsJ4X713bifERc/wA ol2PorLZ8+lYIn9/0uL/CnH9kQGHBt4mtst7z+WuQdUsBl41O++PtjK65ocjD2oseZG/ grIdF1+nK0KAbEPpo7sJNvFUVkHIwv5eEVBgFT9gM3kNZ6AzAkjOpJGnkeMWoQmAu9+Z wGDA== X-Gm-Message-State: AOJu0YzzbQSNyO9Pwd6Ue78kxMN1gYQpcqn4tquOMFOydtRoHBy3ljeX l4avlGu2QWhwOBVsbjc62gCzTA== X-Google-Smtp-Source: AGHT+IF/6lT5Az3dHhIUcXsN8Kwxs9XoleCS24Z4vF5DI7GGvh/QA7VwRvIH1qUNvPxVY8kJjPhUbw== X-Received: by 2002:a17:90b:4d10:b0:27d:5964:4eec with SMTP id mw16-20020a17090b4d1000b0027d59644eecmr6305356pjb.1.1700923230691; Sat, 25 Nov 2023 06:40:30 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a208:d471:6d33:4b36:d85]) by smtp.gmail.com with ESMTPSA id h15-20020a17090aea8f00b002802d264240sm4817998pjz.29.2023.11.25.06.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:40:30 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH 02/10] arm64: dts: rockchip: Add edgeble-neu6a-common DT Date: Sat, 25 Nov 2023 20:10:04 +0530 Message-Id: <20231125144012.58668-3-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125144012.58668-1-jagan@edgeble.ai> References: <20231125144012.58668-1-jagan@edgeble.ai> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Edgeble NCM6A-IO is common compatible IO board for both NCM6A and NCM6B. Add a common io DTSI for it to include them in both NCM6A and NCM6B DTS files. Signed-off-by: Jagan Teki --- .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 386 ++++++++++++++++++ .../dts/rockchip/rk3588-edgeble-neu6a.dtsi | 25 +- .../dts/rockchip/rk3588-edgeble-neu6b.dtsi | 382 +---------------- 3 files changed, 390 insertions(+), 403 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi new file mode 100644 index 000000000000..e141dc84654a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi index 727580aaa105..4c76a00b41eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi @@ -3,29 +3,8 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include "rk3588-edgeble-neu6a-common.dtsi" + / { compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi index 4797260a8a78..c4634bc09fb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi @@ -3,386 +3,8 @@ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. */ +#include "rk3588-edgeble-neu6a-common.dtsi" + / { compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; }; From patchwork Sat Nov 25 14:40:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 747255 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=edgeble-ai.20230601.gappssmtp.com header.i=@edgeble-ai.20230601.gappssmtp.com header.b="wJZbB029" Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 080A9C6 for ; Sat, 25 Nov 2023 06:40:38 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-5bd6ac9833fso1701115a12.0 for ; Sat, 25 Nov 2023 06:40:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20230601.gappssmtp.com; s=20230601; t=1700923237; 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Sat, 25 Nov 2023 06:40:37 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a208:d471:6d33:4b36:d85]) by smtp.gmail.com with ESMTPSA id h15-20020a17090aea8f00b002802d264240sm4817998pjz.29.2023.11.25.06.40.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:40:37 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH 04/10] arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay Date: Sat, 25 Nov 2023 20:10:06 +0530 Message-Id: <20231125144012.58668-5-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125144012.58668-1-jagan@edgeble.ai> References: <20231125144012.58668-1-jagan@edgeble.ai> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Edgeble NCM6A SOM has on-module M.2 1216-compatible WiFi modules. Currently, AW-XM548NF WiFi6 and Intel 8260D2W WiFi5 modules are supported. WiFi modules are fixed on SoM, not pluggable M.2 slots, so different SoM's for each type of WiFi module. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588-edgeble-neu6a-wifi.dtso | 56 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f969618da352..543a2f68b654 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso new file mode 100644 index 000000000000..e9a3855e8752 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * + * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules, + * - AW-XM548NF + * - Intel 8260D2W + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vcc3v3_pcie2x1l1: vcc3v3-pcie2x1l1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* WIFI_3V3_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +/* WiFi6 */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; /* PCIE20_2_WIFI_PERSTn */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; + status = "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_vcc3v3_en: pcie2-1-vcc-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; From patchwork Sat Nov 25 14:40:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 747254 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=edgeble-ai.20230601.gappssmtp.com header.i=@edgeble-ai.20230601.gappssmtp.com header.b="VLHyQFH2" Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DB05107 for ; Sat, 25 Nov 2023 06:40:45 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-285636785ddso2045237a91.3 for ; Sat, 25 Nov 2023 06:40:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20230601.gappssmtp.com; s=20230601; t=1700923244; x=1701528044; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IUgKD0qz4V3/XXhXUCXdndZjhXDkH98hRGDGFOanDcc=; b=VLHyQFH2wARe+5973TC8lY/BwrEaxBXH6qgbczbHBhpe7sMN2PE+vAiFWIs4RtEVUU KiHWW5AVepDr+p9mEgrCjR+z8RReMa+z2241B1bIzSVp5sLG/CrYw7iFklIgTNO/G4hp pnxMtDrRgUxh9NDNdeHXKussslE0i5EvruLHpgh7iAnbFSZN8w1slkMbdmQuL8K+VhRI VwKkqlKmNlrVMehewJZ7CYD+FE0LByItsMcuNu3pdE6LDIGgIdanwenj8R67jNkiihhd cQDjVP1z122+21fyl2MyH5qh+sMG7SBLBTQAeWiUHQ52DNj4RFhNobUz/G9NSgSruY1f mE5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700923244; x=1701528044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IUgKD0qz4V3/XXhXUCXdndZjhXDkH98hRGDGFOanDcc=; b=c1YVl314EqY3b0sUZJxHhhQd/JzHHLP55cAUvCN7TrNFWa20jsh3UG62Sce43L6hkY 8n2HA2HHWflsXCjAWlm63+OimcxKEHAp9lv6A3MJL3R28uPh5JV5jNdJjatLGlN7ZhCP 1q1ai65dApsc/8NtiVWeCo0h16AvPfY+EjnxemLG8Wj3Np3pOz3fQoFsprUeGh5H6B2y BVg53nFJwfXYDpQIMYN1P2BFniIsGunQGp8MqKKrwOSa0uklG16E/0olkGwwkonMIoma u89ICCvnLPBdVxg3EPV9LFq3Vo0OjhS6ThzSnHLORZkyCoWep3BSdn6jN3VLQPwcxCuc K0QQ== X-Gm-Message-State: AOJu0YxQlfTFtMDi2zSqX+ziF4eHAURs2rKUu6D1L2qeStsjXaS2NcQJ PYG4jntRgytSLUas/D7sd54X9A== X-Google-Smtp-Source: AGHT+IGAgxm743znNlj8wApEJKbIGlJxeIn8bL/GrrcKdJGwx2Ocie85VdA72i+sp0r75E8L2/GQbw== X-Received: by 2002:a17:90b:4a09:b0:280:8356:10b2 with SMTP id kk9-20020a17090b4a0900b00280835610b2mr5927050pjb.5.1700923244578; Sat, 25 Nov 2023 06:40:44 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a208:d471:6d33:4b36:d85]) by smtp.gmail.com with ESMTPSA id h15-20020a17090aea8f00b002802d264240sm4817998pjz.29.2023.11.25.06.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:40:44 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH 06/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH Date: Sat, 25 Nov 2023 20:10:08 +0530 Message-Id: <20231125144012.58668-7-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125144012.58668-1-jagan@edgeble.ai> References: <20231125144012.58668-1-jagan@edgeble.ai> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Edgeble NCM6A-IO board has 2.5Gbps Ethernet via PCI2_0. Add support for it. Signed-off-by: Jagan Teki --- .../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 845f90c302ca..7e838d76fa73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. */ +#include + / { aliases { serial2 = &uart2; @@ -11,12 +13,25 @@ aliases { chosen { stdout-path = "serial2:1500000n8"; }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; }; &combphy0_ps { status = "okay"; }; +&combphy1_ps { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -33,7 +48,22 @@ hym8563: rtc@51 { }; }; +/* ETH */ +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + &pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; From patchwork Sat Nov 25 14:40:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 747253 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=edgeble-ai.20230601.gappssmtp.com header.i=@edgeble-ai.20230601.gappssmtp.com header.b="3BXkPpJT" Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BC0BC6 for ; Sat, 25 Nov 2023 06:40:51 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2855b3d9a9bso1948108a91.2 for ; Sat, 25 Nov 2023 06:40:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20230601.gappssmtp.com; s=20230601; t=1700923250; x=1701528050; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kNBeKi0rAQB1+toxqqlE2nYrDGFed7KQnf2/b2wSloo=; b=3BXkPpJThtwAY5uyqDKOdPQEkMl6Qt6inX0Hj6Zz6uzcnFpz5KIPTcO3LEfrQBWpyf v7hpyz0vUl2nxGgT4wsYlMJggYY7+oPX+2l2B+Smbh2F1w9ogSPBlHSjsPvUQu3mMEOC 0nxjS50Dpiw6L+eVUi9GYzvFOw7yif2u6mOnh/DPHNgkAIH5bC0ACEvNWjYfh2Sv1gjM XbabmDisyfsKcqKeDGgMgXDgwei/AQ7s9OvxJoznvdtEMLPWwznjevMFfVeX9oOeC6Gt 6Y9KndIstfc+lmRIw3jtVNIA0U3W/piCVcgsAncFilfE3JNoYENi9Ypzi56IevOjU5sJ k2Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700923250; x=1701528050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kNBeKi0rAQB1+toxqqlE2nYrDGFed7KQnf2/b2wSloo=; b=dXMrxEiFlDnH2Bn/hsSTcD+8zPikJvKAJeU7KTlJmWTOwU71i00dRD0gWnEZgmDcb0 dGpvWkB9I4DrbGZGUJXKNDlCRqY6DmkkZJeYTM5Tkhy/ULCc8q5cMdcWJlj1IUN2k4iz BWbrur9DzUkrVCPMMN3v8n8waHHaLqNNtj37CPXnPntCp/IAkBoxfCFGC2EFlqZx9GMC K98XroZuC3BrNjPWUFPAq7RFRr/6MvOoXi6H8vMta16IhBxxpcuzBbEd4Zl/E1Robpa/ A5vp0O74b+kvtCUaS0U2rU+JCMzZLRCpOzTgOyuZzN/nEvozvsa4zjv8AY1RG7xSEoes BAgQ== X-Gm-Message-State: AOJu0Yy+gJHahnkDHscbNT6ijBsX3b4K8YF4g4tWqOryv4L6zYpvGSMv AsIz64+MYspveNWKnuL2KLP9XGWj8DtXlki00cw0pw== X-Google-Smtp-Source: AGHT+IGgrQuoXz9aS84oakVKvlIXt016m8KWKC6TXzUrZ9EvF6saHWaaHxHERtYqyDBBSLnEetkBeg== X-Received: by 2002:a17:90b:3852:b0:281:3a2:80ee with SMTP id nl18-20020a17090b385200b0028103a280eemr5538394pjb.14.1700923250627; Sat, 25 Nov 2023 06:40:50 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a208:d471:6d33:4b36:d85]) by smtp.gmail.com with ESMTPSA id h15-20020a17090aea8f00b002802d264240sm4817998pjz.29.2023.11.25.06.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:40:50 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH 08/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key Date: Sat, 25 Nov 2023 20:10:10 +0530 Message-Id: <20231125144012.58668-9-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125144012.58668-1-jagan@edgeble.ai> References: <20231125144012.58668-1-jagan@edgeble.ai> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Edgeble NCM6A-IO board has M.2 B-Key, E-Key via PCI3x2. Add support for it. Signed-off-by: Jagan Teki --- .../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 03a81f1dedf9..77fafcdc6fdf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -23,6 +23,19 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { vin-supply = <&vcc_3v3_s3>; }; + vcc3v3_pcie3x2: vcc3v3-minipcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_pcie3x4: vcc3v3-pcie30 { compatible = "regulator-fixed"; enable-active-high; @@ -74,6 +87,15 @@ &pcie30phy { status = "okay"; }; +/* B-Key, E-Key */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x2>; + status = "okay"; +}; + /* M-Key */ &pcie3x4 { pinctrl-names = "default"; @@ -91,6 +113,14 @@ pcie2_0_rst: pcie2-0-rst { }; pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie3x4_rst: pcie3x4-rst { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; From patchwork Sat Nov 25 14:40:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 747252 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=edgeble-ai.20230601.gappssmtp.com header.i=@edgeble-ai.20230601.gappssmtp.com header.b="SXzDnDQl" Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8074C6 for ; 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Sat, 25 Nov 2023 06:40:56 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH 10/10] arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a Date: Sat, 25 Nov 2023 20:10:12 +0530 Message-Id: <20231125144012.58668-11-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125144012.58668-1-jagan@edgeble.ai> References: <20231125144012.58668-1-jagan@edgeble.ai> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Edgeble NCM6A, NCM6B SoM has Green LED on the module. Enable them with heartbeat function. Signed-off-by: Jagan Teki --- .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 961a80014686..003887fbf996 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -3,11 +3,27 @@ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. */ +#include +#include + / { aliases { mmc0 = &sdhci; }; + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -110,6 +126,14 @@ regulator-state-mem { }; }; +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &sdhci { bus-width = <8>; no-sdio;