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[209.51.188.17]) by mx.google.com with ESMTPS id h4-20020a05622a170400b0042384fb129asi3807978qtk.376.2023.11.24.10.34.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 24 Nov 2023 10:34:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KriKj1Ud; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6azj-00024P-4T; Fri, 24 Nov 2023 13:33:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6azh-000245-4B for qemu-devel@nongnu.org; Fri, 24 Nov 2023 13:33:37 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6azf-0003Xm-6p for qemu-devel@nongnu.org; Fri, 24 Nov 2023 13:33:36 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40b36e31b57so15150865e9.3 for ; Fri, 24 Nov 2023 10:33:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700850813; x=1701455613; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8SKOL+p0foMt3mWbWCnSJdA8STcRVEmjnWCmXC+Skls=; b=KriKj1UdxZHwtoM4dvRgA5JIX5D5NKEkcWug3S0oisz/IWNi1JNxpG8cnTbWiHAslS fDJFMcKjlvCMbDMlIoe98v5vEw8kbBbkMFNbZSDFEmA1ge9+VG7+7rqDSdqUXmEmGgGK Smml/44Kfy/L8zR4zJW+5aOG/j7CA/8LvFyfjcLg7vh3esm3zuaWHqliZlFoBJwRI3q3 TWk7KZ0rISJQwymPrL3lP3Hc1Abbsg4KyVL79zEY9dHpz4RNhKTqNghHQI1PktnR102b X2cQD+2ww2Chma4yRMvM8nzpNHYcHo+6ffLczfqlmmJ2jAdcfT2+He25H80XtisiG7M/ 1JfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700850813; x=1701455613; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8SKOL+p0foMt3mWbWCnSJdA8STcRVEmjnWCmXC+Skls=; b=kGVo+jShv8nIQqIJQ2hxQvCw0jaZ+aHNl0atgOkOfiNlfArrpAHHRPoNzKBmoGAGyD KnZ7nHBjVLXzTNAiqgBwkAOtN/6z3mDXItol713KD6cWXqSihEb14gV2axXAJIif/Llv 3md1VEme63A/5M2K/Y1FZTKweut4nTCmVWuWED+JMoeboxGUPvLwUwriToBPLIG6Uvo6 U1hYmVOayHXzP145wQFpWaGEkaE5MxtaqnmI8lloXfXl3SXZGjvOtloMfDr/2W8dLf3J 7NRWqz8zPvClBlX8UeH2uu6J8cx8Gl7TW6o1nUjnewHsgDLZKz6s50/WZXMoe13t3LKa rcdA== X-Gm-Message-State: AOJu0Yyz+NZxXBukJvO+ME6E3UX4V6fSwl3krQS/2MeAlMM9NwmFTvHW 76wJDJ7gQL18aTLN+WRVx+DRAgBNPDr6uT26pqU= X-Received: by 2002:a5d:6605:0:b0:332:e31b:1f3 with SMTP id n5-20020a5d6605000000b00332e31b01f3mr2875131wru.31.1700850813439; Fri, 24 Nov 2023 10:33:33 -0800 (PST) Received: from m1x-phil.lan ([176.187.218.17]) by smtp.gmail.com with ESMTPSA id c9-20020adfef49000000b00331698cb263sm4955541wrp.103.2023.11.24.10.33.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 24 Nov 2023 10:33:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Francisco Iglesias , Jason Wang , Vikram Garhwal , Anton Kochkov , Pavel Pisa , Vikram Garhwal , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Qiang Liu Subject: [PATCH-for-8.2? v3 1/2] hw/net/can/xlnx-zynqmp: Avoid underflow while popping TX FIFOs Date: Fri, 24 Nov 2023 19:33:24 +0100 Message-ID: <20231124183325.95392-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124183325.95392-1-philmd@linaro.org> References: <20231124183325.95392-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format Message Format The same message format is used for RXFIFO, TXFIFO, and TXHPB. Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. There is no mention in this reference manual about what the hardware does when not all four words are written. To fix the reported underflow behavior when DATA2 register is written, I choose to fill the data with the previous content of the ID / DLC / DATA1 registers, which is how I expect hardware would do. Note there is no hardware flag raised under such condition. Reported-by: Qiang Liu Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425 Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal Signed-off-by: Philippe Mathieu-Daudé --- hw/net/can/xlnx-zynqmp-can.c | 50 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index e93e6c5e19..1f1c686479 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -434,6 +434,52 @@ static bool tx_ready_check(XlnxZynqMPCANState *s) return true; } +static void read_tx_frame(XlnxZynqMPCANState *s, Fifo32 *fifo, uint32_t *data) +{ + unsigned used = fifo32_num_used(fifo); + bool is_txhpb = fifo == &s->txhpb_fifo; + + assert(used > 0); + used %= CAN_FRAME_SIZE; + + /* + * Frame Message Format + * + * Each frame includes four words (16 bytes). Software must read and write + * all four words regardless of the actual number of data bytes and valid + * fields in the message. + * If software misbehave (not writing all four words), we use the previous + * registers content to initialize each missing word. + * + * If used is 1 then ID, DLC and DATA1 are missing. + * if used is 2 then ID and DLC are missing. + * if used is 3 then only ID is missing. + */ + if (used > 0) { + data[0] = s->regs[is_txhpb ? R_TXHPB_ID : R_TXFIFO_ID]; + } else { + data[0] = fifo32_pop(fifo); + } + if (used == 1 || used == 2) { + data[1] = s->regs[is_txhpb ? R_TXHPB_DLC : R_TXFIFO_DLC]; + } else { + data[1] = fifo32_pop(fifo); + } + if (used == 1) { + data[2] = s->regs[is_txhpb ? R_TXHPB_DATA1 : R_TXFIFO_DATA1]; + } else { + data[2] = fifo32_pop(fifo); + } + /* DATA2 triggered the transfer thus is always available */ + data[3] = fifo32_pop(fifo); + + if (used) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Incomplete CAN frame (only %u/%u slots used)\n", + TYPE_XLNX_ZYNQMP_CAN, used, CAN_FRAME_SIZE); + } +} + static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) { qemu_can_frame frame; @@ -451,9 +497,7 @@ static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) } while (!fifo32_is_empty(fifo)) { - for (i = 0; i < CAN_FRAME_SIZE; i++) { - data[i] = fifo32_pop(fifo); - } + read_tx_frame(s, fifo, data); if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { /* From patchwork Fri Nov 24 18:33:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746812 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp1689686wru; Fri, 24 Nov 2023 10:34:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IFUFHC8MdLgUX57yl5IkRtpUasSETSwEY/EBok7/jsGEPs+oANEzI0mSJiL4HB3o9kBrdpy X-Received: by 2002:a05:6870:3926:b0:1f9:e8fe:95ab with SMTP id b38-20020a056870392600b001f9e8fe95abmr5011414oap.30.1700850879252; Fri, 24 Nov 2023 10:34:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700850879; cv=none; d=google.com; s=arc-20160816; b=QG3SbvensbQZO1camqeAksk/KnPfm4K+4UvhaI+Yfkc7vtXWWi3WEMG0JQlMN/BRo1 aqroxSK9gCzmwx8sAzkJmL4a6wPpZAjfSfD8ahpG9Vacn3F/bRX83JU9xSfC2O6UlrTI aazM72vhy8V6nXE3EnpN5iKJTWBM3ZVfG9Kxc7Bzc0E6w6ODKpXXRyLL620xIeMp0c30 Zq/XlisgOQUlLsYNWKJ0Rb3Rhqr5OZfEAf/B/Cx8gJQXs4p1BpZqPXphiBrxhhBTwggs QpedpX0Eil8VzABP2qIaud9Pug5+vri4+wbLENgsBRd6eOsPsy+nF8y0K8ZBwXjFOz0K zyDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bKUVprOOGD3OuG3+WfNy/MdCtQb19fWqkaa6eHfcY38=; fh=ij9motZtXSv0oHMpElM88zqWr1sn4oujnL1YfqFBaWE=; b=ZI2CwZsTHVstSzzocv7qqKi6y5u45juhbS0zcW9LKZ9t6xRNjg/Zgt7WFhlFjcMFOK OCytd3sVRrV5vYqx+lqDnea/UiTSUXgS+ReaWsigFsUQ4CI0GfQyaVaMD+gK7guPyETW a5zvZqtr8HhgtecoFljGC9nk5eVyUqiBaDNPp0lm+I9g7NYrwdqor1KCjJp3YpNKMyyo Y1vC2o302uPtz+mRtFPbn6EHZ6xRIqaMgvJ6VXoziCEWpZnU2bT4no8+8YDrp5zL8ucg my47RSrj6iC7CV6m4tvjffbICK6PbbNwMLHQ2zdjwOlAYY4qLnZOwaunT/12GsfI0C7J /Bkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wSYMoQAG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. There is no mention in this reference manual about what the hardware does when not all four words are read. To fix the reported underflow behavior, I choose to fill the 4 frame data registers when the first register (ID) is accessed, which is how I expect hardware would do. Reported-by: Qiang Liu Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1427 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal --- hw/net/can/xlnx-zynqmp-can.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index 1f1c686479..f60e480c3a 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -778,14 +778,18 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame) } } -static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val) +static uint64_t can_rxfifo_post_read_id(RegisterInfo *reg, uint64_t val) { XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); + unsigned used = fifo32_num_used(&s->rx_fifo); - if (!fifo32_is_empty(&s->rx_fifo)) { - val = fifo32_pop(&s->rx_fifo); - } else { + if (used < CAN_FRAME_SIZE) { ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); + } else { + val = s->regs[R_RXFIFO_ID] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DLC] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DATA1] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DATA2] = fifo32_pop(&s->rx_fifo); } can_update_irq(s); @@ -946,14 +950,11 @@ static const RegisterAccessInfo can_regs_info[] = { .post_write = can_tx_post_write, },{ .name = "RXFIFO_ID", .addr = A_RXFIFO_ID, .ro = 0xffffffff, - .post_read = can_rxfifo_pre_read, + .post_read = can_rxfifo_post_read_id, },{ .name = "RXFIFO_DLC", .addr = A_RXFIFO_DLC, .rsvd = 0xfff0000, - .post_read = can_rxfifo_pre_read, },{ .name = "RXFIFO_DATA1", .addr = A_RXFIFO_DATA1, - .post_read = can_rxfifo_pre_read, },{ .name = "RXFIFO_DATA2", .addr = A_RXFIFO_DATA2, - .post_read = can_rxfifo_pre_read, },{ .name = "AFR", .addr = A_AFR, .rsvd = 0xfffffff0, .post_write = can_filter_enable_post_write,