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Thu, 23 Nov 2023 08:17:44 -0800 (PST) From: Neil Armstrong Date: Thu, 23 Nov 2023 17:17:41 +0100 Subject: [PATCH v2 1/2] dt-bindings: power: meson-g12a-power: document ISP power domain Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231123-topic-amlogic-upstream-isp-pmdomain-v2-1-61f2fcf709e5@linaro.org> References: <20231123-topic-amlogic-upstream-isp-pmdomain-v2-0-61f2fcf709e5@linaro.org> In-Reply-To: <20231123-topic-amlogic-upstream-isp-pmdomain-v2-0-61f2fcf709e5@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Ulf Hansson Cc: Daniel Scally , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=643; i=neil.armstrong@linaro.org; h=from:subject:message-id; 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Thu, 23 Nov 2023 08:17:45 -0800 (PST) From: Neil Armstrong Date: Thu, 23 Nov 2023 17:17:42 +0100 Subject: [PATCH v2 2/2] pmdomain: amlogic: meson-ee-pwrc: add support for G12A ISP power domain Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231123-topic-amlogic-upstream-isp-pmdomain-v2-2-61f2fcf709e5@linaro.org> References: <20231123-topic-amlogic-upstream-isp-pmdomain-v2-0-61f2fcf709e5@linaro.org> In-Reply-To: <20231123-topic-amlogic-upstream-isp-pmdomain-v2-0-61f2fcf709e5@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Ulf Hansson Cc: Daniel Scally , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2024; i=neil.armstrong@linaro.org; h=from:subject:message-id; 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struct meson_ee_pwrc_domain; @@ -115,6 +117,13 @@ static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { .iso_mask = BIT(16) | BIT(17), }; +static struct meson_ee_pwrc_top_domain g12a_pwrc_isp = { + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, + .sleep_mask = BIT(18) | BIT(19), + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, + .iso_mask = BIT(18) | BIT(19), +}; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -231,6 +240,11 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_isp[] = { + { G12A_HHI_ISP_MEM_PD_REG0, GENMASK(31, 0) }, + { G12A_HHI_ISP_MEM_PD_REG1, GENMASK(31, 0) }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -269,6 +283,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, pwrc_ee_is_powered_off), + [PWRC_G12A_ISP_ID] = TOP_PD("ISP", &g12a_pwrc_isp, g12a_pwrc_mem_isp, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {