From patchwork Thu Nov 23 14:38:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746480 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp914412wru; Thu, 23 Nov 2023 06:41:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IFP+C0bH1l0U2gQqVrxnBMNqZzyHboPDdv7LVi+P8svhBRFE0C22zh7h8LtEos7MRcPFxTR X-Received: by 2002:a05:620a:178c:b0:774:fb6:124f with SMTP id ay12-20020a05620a178c00b007740fb6124fmr7104762qkb.29.1700750475677; Thu, 23 Nov 2023 06:41:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750475; cv=none; d=google.com; s=arc-20160816; b=Ntjwq4vOPvsIb9ytzVjVSjDAgcdqlmTavKvEWgPjLJc8/yUuqFL+SrThY9ndYbeXhs 3CDcEPi/TMm/xKU8ox9R6oyWUZoAfwCoJ+0IVJsX1cr0XBXBp5yHJLnxZkazwVnf495E oopGXkR6AN6xHIshEwj4t2qXYTEoztyQwwbuAq72gR4+AnTCaOkXNw/jT9t3m8snCmjT vD1dRP1pvvUTNORf33rM+fNJwyLrmR2/ESv82HjfcfxMeiBCuw1iLf/dxG9H0ISHgZbc MlLLAJHF5U6ktr3XkpMRezoywF80P1qQTpxtdeu/cWruL4dgD4qpwFjeLxWPGUrs2A8z RkgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Vpz6WqSYEj1xbsU7bl0EFtxY0Jdo72CGKjloYLxmr9U=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=fAgg7CA7vF8vmXvX9UsnNhvpKRLZH0MnaafG9wNvGDpAj7sKPRaLsEhD265BySRbBF nSfyRm2GLuzYpKCuWZv+BI93DWhf71JVQL6Dou1KGOXMO1fAueNFc0AOVUtrF7y2UVwS T0uJ21cYLWfwcYcDl9nPIOobVskIoyk9BWVxDB7foV4F4V11AK/ijD1t1UjNYeo5/Nvz H3vIWFaT7vrW57ef7yDDYE67lSX4CHL7fsN1uXIw8RlCm2MhLwy5sjnBu5tZpvLQ9EQ+ /LXcNKCX/gaDAVHf/G8vpr0drAWjBK2n2N7am7zBrcRnejjOOSpYriMdNAsMbDTZtQqI ARWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aBUIrDKL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 9-20020a05620a040900b00767d2097bd7si1188424qkp.322.2023.11.23.06.41.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:41:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aBUIrDKL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Aqy-00020Z-Lt; Thu, 23 Nov 2023 09:38:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Aqi-0001oO-8t for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:41 -0500 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Aqa-0002QM-P6 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:31 -0500 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-507be298d2aso1193933e87.1 for ; Thu, 23 Nov 2023 06:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750306; x=1701355106; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vpz6WqSYEj1xbsU7bl0EFtxY0Jdo72CGKjloYLxmr9U=; b=aBUIrDKLC3IQK0EYP/p1YT1iG3z/EEKUTBBt8iiZOH8ERfkIFUf3MdNf5EziD5GwOz gEH61vlNqPSg2Ksvp8OOQPRbeByn7YGPbcBkt2Zr6xmhpLd8vaP04fNtPw6IVShh4fmR bnOhm2Ls4SEDdszKOGnELGzAIc/cQc2BNkUbiLXX+4gIg1ROa1ppErWsh2PtKGhIZcQb ngQc9RluMGVOSbSBXkUyUM+ONNOV3m8ENdAwUVEr5MZs8GoPOQTTM697QQdX82KtcbYR 8HfVyXtmFhei84Pl5/a93N24v7JRKn7t5p5AhSLvYiU+7BX/0VVHkWvnIKM4Y0nykFcQ IwCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750306; x=1701355106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vpz6WqSYEj1xbsU7bl0EFtxY0Jdo72CGKjloYLxmr9U=; b=AOqd56C0lyk7AxXoTnvwGP7g6FiAeG8Eea4S8QAOOmBbEZU8EIbaADaMuIx1yXsp9L 0ny7VV1iuLu0JAvcsKh3atquMrB3Lq85VszDcAaP4x5iB3svq9/0N7/SWarVFRXNkk1c 7faTE+kxgjCIb+hHykFKoroSnaZiivqEmgSOfymWem20G22Fp9HOvbAE0cHzKF0GFatc 19LzKFy0FpU2zYeQxe7cJAcm/VAi1VZ4DJvHBGlsSm/jPk34n6tSug4pbs6PhkTKZy/b ny0m2N8sS6tJdI71ldwnN+MKFiHsOklKisvHJcDmcjBwYamb4mhKq1GqzUs5Ph+9Y+Rz qAYQ== X-Gm-Message-State: AOJu0YymVXZEA3R2bGReeRq/5UwCcc9p/GjFtLlXgKb4j3Plz1i59nAp g/IPsnkJ/njN37gKDH1q/XBiYQ== X-Received: by 2002:ac2:4348:0:b0:509:4c7b:c734 with SMTP id o8-20020ac24348000000b005094c7bc734mr3655236lfl.20.1700750306459; Thu, 23 Nov 2023 06:38:26 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id a7-20020a056000100700b00332d32efff5sm1791257wrx.74.2023.11.23.06.38.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 1/8] hw/ppc/spapr_cpu_core: Access QDev properties with proper API Date: Thu, 23 Nov 2023 15:38:05 +0100 Message-ID: <20231123143813.42632-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUState::start_powered_off field is part of the internal implementation of a QDev CPU. It is exposed as the QDev "start-powered-off" property. External components should use the qdev properties API to access it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Harsh Prateek Bora --- hw/ppc/spapr_cpu_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 91fae56573..24f759ba26 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -306,7 +306,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) * All CPUs start halted. CPU0 is unhalted from the machine level reset code * and the rest are explicitly started up by the guest using an RTAS call. */ - cs->start_powered_off = true; + qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); cs->cpu_index = cc->core_id + i; if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { return NULL; From patchwork Thu Nov 23 14:38:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746478 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp914154wru; Thu, 23 Nov 2023 06:40:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IHS1G4rdVcoB87a0Ou9zsYyQO2dvWTzTHmWe2cnsFjYWflrOVkHypYzVDNfIqBk/muxZg+I X-Received: by 2002:ac8:1418:0:b0:423:8345:369f with SMTP id k24-20020ac81418000000b004238345369fmr3539213qtj.7.1700750446361; Thu, 23 Nov 2023 06:40:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750446; cv=none; d=google.com; s=arc-20160816; b=kFN8EhCuIOCAY6QoAw5PLcOoHA1HHtFQMlKlC7LUhDnBgbKZJ3VqCavKXa/4oAB5J4 i2A5XmpgoELNHfo9aNwNGUBpagtoBdby8DcmbBqSaHxZcT0ULyt482XuofXTVwY9xswj LJ27WUYPC9JQiD7BWQC0s7EuTkYdj02r0DhL85OBqO8P7YbaMg6xXpZpgNaQJG4FyvL5 W32o8bTsz3EesfV8eFUL0P2Xd6DSwPkfKFtM7kdZw7JbzMS4BZH3V4NDmz48U1O5B2PP PDCPZ0jnCA+g2sjv9oEmvouhI2HnR26bjvfY2Iy7oytus7+YPgJTrfFFFEnXKwuDqiqs gNsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=77fFdvJTmm2pNTXteaORtoV0izbQYF6N9SGikVs/zTs=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=jOwfR1CBfVDinGZalDatQFWWmPxHHBXRRcZ8FaTMA5+5DK/8/jKJ7XkvAHxIUP+fZm LOuHP4oOFhJdGCdpSb/tWJuuLwp2pgyZqEqF5DxhmHXHq9XBYA4Kgppr/mjZD5kSxdS5 VWAjN3vc/Ge3gDmKvItzjjMrgedY8oVBsSGg4A7pToieKMIxvKw3YV2MpaPTvc87h6WR DKCl3hWjV+79CZ1NViKERi4URtRs+cyhxyksDRh+QdhSGmWlL48sJnztb2wSA9aJ/SZ8 OdQYe2zRgBw8F5rsA7VHaxex9dImhy7230gxD6V+k1FZqCVvFGhu27H8bxTrQ3SmHmVF 2V4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hsUBkAF1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 20-20020ac84e94000000b004237231d97esi1250266qtp.309.2023.11.23.06.40.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:40:46 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hsUBkAF1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Aqy-00020T-LY; Thu, 23 Nov 2023 09:38:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Aqm-0001od-Fq for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:41 -0500 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Aqi-0002RU-Sw for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:40 -0500 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-50aaaf6e58fso1326275e87.2 for ; Thu, 23 Nov 2023 06:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750314; x=1701355114; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=77fFdvJTmm2pNTXteaORtoV0izbQYF6N9SGikVs/zTs=; b=hsUBkAF15u2tF6OaS0hC6R0TUs+duo0yNyVuE+uBDj02b3LY9nm2WDm7BjuNN7uxZ0 xGg8Ja7cPXljTX6Axmxqwmb1BIFHVnvTI7BugnD/5SIiO72UZvXpuAR6flM7Za8X8YE0 G0au7mLeFJKbiKhMgAQgOk/yZdaq8NJOrFIFXEi+5IunjSffwPY7Un7hyyNy6FPtdzMb xnxTGzmJXaFyHXjsbyF7DwF/uTwWFU4Dt+2bDaryx84TlJxWfCBXOR/KT7drc9ty8xPS VURozB1UzQ1RoS5lsvZE72UjaMlMldoQCDDvhrvzz27a9poDcFseJqsr4UPbCTmSLk7J 0ZVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750314; x=1701355114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77fFdvJTmm2pNTXteaORtoV0izbQYF6N9SGikVs/zTs=; b=hF2e4o47EISeqak5YqwfMWIZlaBz+8faPJQGnx5w7q04431VRfXuzqII2g+gmWW4xy RRitD6pIZvq9WS2EIkuvwNU4o3yYdtqzaZp/rpyUgM3+h5cvV4vgNiVkbzwyJV8B1Xek G9ZlwBqwx6raQkib86dZy3vACL2ZvwLX+LyRTSwUn7lyABH8IKP8QxXSsHkVgC22Zny4 QntAZUVASxo1wyL6YgqXMmVisH6DjCSYeL/DSQsRr3hhKekLSx2Ffq82XNfJDDYg+tHV MEX7Ist9sluDAKvb2lTJmQ358/WGmtR4FPp3mC1N1zpM0pBdV/oKR5309gHNEZeUzuK/ KhEA== X-Gm-Message-State: AOJu0YwIe85zu8Kco23HGKbuaqZv2xRwVupr8u+uk5gW41ZDlhmw1KtR 7h5w56htDj0C0S3Ym1/JZCgkOw== X-Received: by 2002:a05:6512:4894:b0:50a:a9ec:1897 with SMTP id eq20-20020a056512489400b0050aa9ec1897mr2523896lfb.35.1700750314699; Thu, 23 Nov 2023 06:38:34 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id k24-20020a5d5258000000b00332c0aace23sm1817937wrc.105.2023.11.23.06.38.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 2/8] hw/arm/bcm2836: Simplify use of 'reset-cbar' property Date: Thu, 23 Nov 2023 15:38:06 +0100 Message-ID: <20231123143813.42632-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=philmd@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org bcm2836_realize() is called by - bcm2836_class_init() which sets: bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7") - bcm2837_class_init() which sets: bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53") Both Cortex-A7 / A53 have the ARM_FEATURE_CBAR set. If it isn't, then this is a programming error: use &error_abort. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 166dc896c0..a1bd1406e1 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -131,10 +131,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; /* set periphbase/CBAR value for CPU-local registers */ - if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", - bc->peri_base, errp)) { - return; - } + object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", + bc->peri_base, &error_abort); /* start powered off if not enabled */ if (!object_property_set_bool(OBJECT(&s->cpu[n].core), From patchwork Thu Nov 23 14:38:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746475 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp913922wru; Thu, 23 Nov 2023 06:40:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IH/XqaPu4q7hqePqvP3ddFFMjJeHPWDg6UlTcKCO1wwSpZnboi9QYI5ShgNw66G1GuND/Q7 X-Received: by 2002:a05:6871:4504:b0:1f9:5c66:3b31 with SMTP id nj4-20020a056871450400b001f95c663b31mr6980019oab.14.1700750418426; Thu, 23 Nov 2023 06:40:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750418; cv=none; d=google.com; s=arc-20160816; b=BEm8RVFm/TESr59u0AjxsyW8niiH3Q7IHjo4JCX5L5VMEP/dtfg+ENV/rQBUGu89ud EhT1TeBsNXO4RPKAZ+LdU9xsIbzlspsvTuAnyVhoSl/xI2toOc4b8hw+3HwggOStIqhw fO6z4hXm10Lucng9h4ImM7fF2HR6EpSzAY+HCQ79KRBmrzN/PEBkm1XkShTrkTU2Rw0O kMBUOevUXYYDHC9f4eY2aInf2iiM15aK7yKhOG0imx9LG4RHzXf+UKQE6OIyI+q0GH9E mYhTjV/edoATV96NY8yQVhmTrdMq+jSg4Fn9PbtG8vBh4ShOcxjW/Y/JQa+HDNPKpPHk W6PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+pOWYkpnIyztLHOzwZOLJUZ7Drb6F2CHVis+xLrcWw8=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=Ec6T06+suEwkPSRjn1hzCPjw9speyxSfeqUykaIkaTg6a28xuwu9M6DCwxT6/zbOkg BWf9RToPj2ocANH6n1Y6+f0/Fm/hsja1BVU15jGIiRq4wbU4JlYHIh6LCPmXAC9A6YpM cKWppRO7sE+8TmBWijTIJhxcmKaq6k2oytd5wVmVs3vpAImHiMU4DyD8uyrpCU4gIZC0 0yjBCyoQFT2IZ74/ZX5PmgsmOPSNBl94Aj/iHUecK/rtxUmP9jhL9NiXmYbO/1Uv5xeg bxsM4wUWu5R8+ZU7N/N0BKd6acW5on5NXJVq0ltHuT7ZCJ3CsnfMqh5UYWhj4spxP1Xi Ntew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L3qKQx03; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u13-20020ac858cd000000b004237255d271si1218293qta.660.2023.11.23.06.40.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:40:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L3qKQx03; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Ar5-000275-3v; Thu, 23 Nov 2023 09:39:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Aqt-0001sV-8k for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:47 -0500 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Aqq-0002Sf-AC for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:47 -0500 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c8880fbb33so12509531fa.0 for ; Thu, 23 Nov 2023 06:38:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750322; x=1701355122; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+pOWYkpnIyztLHOzwZOLJUZ7Drb6F2CHVis+xLrcWw8=; b=L3qKQx0328ylmhzgiJSfH3QQoAKzDtOEzbAtaXc61OoOoUsd6nydro6xNZMetDRtCk n4ZkXQ2TJv9H2ghrwxkd0gLZVAp5VqOMx3U5Dz/WDk0d31gyDkFgqxpv/NDY4OMNkAnA AuqiDi+j6rXYoHPK9TIX+Yq//m5rnU3HOhZ6UqLXEptAaPLuZxPodmUnEqQ9Q598T1uN LWZnby19lv4xGV8mXGhMP6wBCTk+LIugzS6S4nXxsMqZTW3mWUWV8T1Pw5titUF9K01R kpgtjw1XrA22gZlIHCPXZcObIOlF0gtXSx0U8SC2tLnqIrF085hFjtdfj6Rw+6kE/qcc XmyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750322; x=1701355122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+pOWYkpnIyztLHOzwZOLJUZ7Drb6F2CHVis+xLrcWw8=; b=cAKw/Takw6bM89ZiBkjW3KFW1Cd/WwJ0c79JFqPrvlNBBa+3W441gIsQodMu4IA6wv M5JWkWR7aPfM5iZRVEurcAAEnOlaDFnbWTJawN7sOIDAk7g4YxAMiZ8abj0hGaC1WqPy amWJhV3PmQcQFnTa/ZyXcLO8TS8eq7MaLpOMXKTEt9j1Xr8lb+pgibsiYn1b5DZv+56q 52zGzbGyjMEIOMtTkFCcuB9iMJbxE6MnUnEtaXSzK9MHJGji6JAZcsLS0snxrog7Aft1 cSbR4ciUWrxy2s222809k57TNXc0juFmYt2ZbTrZdU4pMxzTUBfqwppuQhXv8FaGI9OW zNOg== X-Gm-Message-State: AOJu0YwZxzQDwfdD9EaaHMDNRY6MZtsr7tvXbPXo/SNQoFcEg2MrHvvw X0EXEBQJMGRrXz2gdq3hTPT6uA== X-Received: by 2002:a2e:960c:0:b0:2be:54b4:ff90 with SMTP id v12-20020a2e960c000000b002be54b4ff90mr3797036ljh.53.1700750322683; Thu, 23 Nov 2023 06:38:42 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c1d0e00b0040b34409d43sm2188494wms.11.2023.11.23.06.38.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 3/8] hw/arm/bcm2836: Use ARM_CPU 'mp-affinity' property Date: Thu, 23 Nov 2023 15:38:07 +0100 Message-ID: <20231123143813.42632-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=philmd@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 'mp-affinity' property is present since commit 15a21fe028 ("target-arm: Add mp-affinity property for ARM CPU class"). Use it and remove a /* TODO */ comment. Since all ARM CPUs have this property, use &error_abort, because this call can not fail. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index a1bd1406e1..289c30e6b6 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -127,8 +127,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); for (n = 0; n < BCM283X_NCPUS; n++) { - /* TODO: this should be converted to a property of ARM_CPU */ - s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; + object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", + (bc->clusterid << 8) | n, &error_abort); /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", From patchwork Thu Nov 23 14:38:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746474 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp913731wru; Thu, 23 Nov 2023 06:40:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IECKFKi6eGAuT1uh4gAgV6AxFoSlCUQsNKTWhLQC03YIm42YJh/VGUAv7TiNMNg30wIDNrO X-Received: by 2002:a05:620a:2048:b0:774:30b7:ed93 with SMTP id d8-20020a05620a204800b0077430b7ed93mr5972406qka.29.1700750401042; Thu, 23 Nov 2023 06:40:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750401; cv=none; d=google.com; s=arc-20160816; b=LJgtN2zAeb9aqKBv/0nG4Jie9+rAtjvuGKFLNFmte8anvAUmhvEsgjA6mImxOoK4bW 3te9sF7rmVTNu7XLDNKSTMB4gXBIdnbju5qxNizVtL8vhOl2ECJpgx066Oh1W/KLduC2 sjNtFIq0yugBhQK8OI/ppGhYth+0v3HEQGI0veJpUpvzazF3RFYf/IECTVZ8ndVFZMyD Vj5/7Ra+1T1xFKv90HnTwNJ8kRQglUvyRElO/2a24zO0kZx8BjIxExxXB1L/sNKBR8Ld qEmYgw0M4SArV65jyT1WwKLjsB6R+GXiLk69y6jmsvcmRunAfDfAmOHdtqIKy0GknO6C WVzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UVWcie4bmzaB0d5l/X4mRechmHi5GyH0Jpi7gVis3Lc=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=RH/uFW7nN4x8QPmROc1KG6nUJNLzlWKBWRlgjnO/28KFcJf0Z6jHysX7qL6Pei5tYe n9F12sonm1P06DrcHypuZxppBuhT0JngFXgbOYLECnMctLvEI5wsepnXwwh9O0Ku6maZ Xpt0vdGZCwJyksL6yN04yZS64uPDwQyH+q9wwTpMVR2eIBh177/WgkMtWDtxoUupSD/w V8LzW/0gGlaC4XkebOshKxZ/WTDmBE5hTEkrCStiWLQLteK+7LMv/hF0EmtWbzJ9e4Ur 8u4jJEt9PIYHqUm+O+jP+6aq3YoDDnAyk1i7um9c2DWbUXA8ZuS4ArNbg2IRqTqVknAI yLjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cV4vnLZb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w6-20020a05620a444600b0077771ab761bsi1270492qkp.35.2023.11.23.06.40.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:40:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cV4vnLZb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6ArN-0002JL-VA; Thu, 23 Nov 2023 09:39:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Ar1-00025Y-Rw for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:56 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Aqy-0002UD-D7 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:55 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-332e7630a9dso15056f8f.1 for ; Thu, 23 Nov 2023 06:38:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750331; x=1701355131; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UVWcie4bmzaB0d5l/X4mRechmHi5GyH0Jpi7gVis3Lc=; b=cV4vnLZbO9huW2/0n7GwE6JNt5TGVEc9H4KNmIBe2yDGOAnioOGg/wH1BvZvRgstaZ iY9+1GbMNvuHbJsnf7Ps54zcJDZ4PilBznk+u4zZ+URiMOhGsNfw11iGxajHlfyn/DSs 1oZjsJ2bmMbXuvGvufVtEF6kberlgmNqkZWh8Y9afhzTCG+U12bQ2Es7MItguJ+1KUVx X+DBK+dJkKTxOpWsNAf4TM5TZhzC58KSsz/Y8DxmLqjFgGSKIqOCNBdFvNHIJvKYZcb/ hy/FN4r10h+77JyPYlCM04chEsNLx+1lYdJbGBGkMVupHcE3MRqqnzTU/n9OaYtfTd0f LUbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750331; x=1701355131; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UVWcie4bmzaB0d5l/X4mRechmHi5GyH0Jpi7gVis3Lc=; b=k82Bw/PCUCZKYYOYIHh2tZxbcovLoPqIRB2oCBSY4xu4h5l/JG1D8ktt/OThyYdCmC o6dRe4N7vxcwJJZEDGKsSNi8sknTPs+vrnXzmppxAv6dVUkqk/N1M4WQtBq0iGuZeRvL bTF7zfIMJhTs3DmCI4nCJINZs6FShf3IiO6HXxpMDyQ9qxTNN5NApELp/7ziTicuF3lp 3Usq2A5u121cmZBa9wJbmRIOtmw2ZQfc2n31TSubS73lThvScdFBYnI0GI0B7bFGO1rM MczZJ/pBjiSmwsOEdl9rA3Rz9nxXq4Ju8/E316XTpqiOgJZNaaIP1TScs8RNOgGwM8dK GwKg== X-Gm-Message-State: AOJu0YxhFg+aZuOACoNCfE7NtLCRhclfb1RbQgSsKU3HxNXz8Io2dVkO NxHZ4NWso1YFqQEVOscbYorigQ== X-Received: by 2002:a5d:5644:0:b0:32d:81fe:7104 with SMTP id j4-20020a5d5644000000b0032d81fe7104mr3649375wrw.63.1700750330739; Thu, 23 Nov 2023 06:38:50 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id cr6-20020a05600004e600b00332cc24a59bsm1802540wrb.109.2023.11.23.06.38.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 4/8] hw: Simplify accesses to the CPUState::'start-powered-off' property Date: Thu, 23 Nov 2023 15:38:08 +0100 Message-ID: <20231123143813.42632-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 'start-powered-off' property has been added to ARM CPUs in commit 5de164304a ("arm: Allow secondary KVM CPUs to be booted via PSCI"), then eventually got generalized to all CPUs in commit c1b701587e ("target/arm: Move start-powered-off property to generic CPUState"). Since all CPUs have it, no need to check whether it is available. Updating this property can't fail, so use &error_abort. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/arm/armsse.c | 6 ++---- hw/arm/armv7m.c | 8 ++------ hw/arm/bcm2836.c | 8 ++------ hw/mips/cps.c | 7 +++---- hw/ppc/e500.c | 2 +- hw/sparc/sun4m.c | 2 +- 6 files changed, 11 insertions(+), 22 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 31acbf7347..4672df180f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -1022,10 +1022,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) * later if necessary. */ if (extract32(info->cpuwait_rst, i, 1)) { - if (!object_property_set_bool(cpuobj, "start-powered-off", true, - errp)) { - return; - } + object_property_set_bool(cpuobj, "start-powered-off", true, + &error_abort); } if (!s->cpu_fpu[i]) { if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index d10abb36a8..cbaebe9bf8 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -318,12 +318,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } - if (object_property_find(OBJECT(s->cpu), "start-powered-off")) { - if (!object_property_set_bool(OBJECT(s->cpu), "start-powered-off", - s->start_powered_off, errp)) { - return; - } - } if (object_property_find(OBJECT(s->cpu), "vfp")) { if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) { return; @@ -334,6 +328,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } + object_property_set_bool(OBJECT(s->cpu), "start-powered-off", + s->start_powered_off, &error_abort); /* * Real M-profile hardware can be configured with a different number of diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 289c30e6b6..b0674a22a6 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -135,12 +135,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) bc->peri_base, &error_abort); /* start powered off if not enabled */ - if (!object_property_set_bool(OBJECT(&s->cpu[n].core), - "start-powered-off", - n >= s->enabled_cpus, - errp)) { - return; - } + object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", + n >= s->enabled_cpus, &error_abort); if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { return; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index b6612c1762..4f12e23ab5 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -78,10 +78,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) CPUMIPSState *env = &cpu->env; /* All VPs are halted on reset. Leave powering up to CPC. */ - if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, - errp)) { - return; - } + object_property_set_bool(OBJECT(cpu), "start-powered-off", true, + &error_abort); + /* All cores use the same clock tree */ qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 384226296b..566f1200dd 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -955,7 +955,7 @@ void ppce500_init(MachineState *machine) * when implementing non-kernel boot. */ object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, - &error_fatal); + &error_abort); qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); if (!firstenv) { diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 17bf5f2879..64895aebe3 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -804,7 +804,7 @@ static void cpu_devinit(const char *cpu_type, unsigned int id, qemu_register_reset(sun4m_cpu_reset, cpu); object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, - &error_fatal); + &error_abort); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); cpu_sparc_set_id(env, id); *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); From patchwork Thu Nov 23 14:38:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746473 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp913640wru; Thu, 23 Nov 2023 06:39:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEv51ejjGtq9bMdRCahnhbkLhTeFkc30zld59TM3BrQDpie5mZmpRErVwMBAsW9KF9U4Jcx X-Received: by 2002:a05:6102:2135:b0:462:7ca4:a538 with SMTP id f21-20020a056102213500b004627ca4a538mr5563942vsg.30.1700750392921; Thu, 23 Nov 2023 06:39:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750392; cv=none; d=google.com; s=arc-20160816; b=YmymI3QIqxtuEUGVTzlsN/Ml9ay7wvkPI2fjCHbSuoJx7xBYzkaMX3l0psbrd/F8vz HoY4oq+NJ6xEDl/OVjv2bMhcaM25tBx010hWJaOew2holl1RitQzDgWZP0vIXPxuhMgG qMNtrHAxquXzcUFhby4dzPxFgUkZmtCi/4bz5/Bb3ljJHIq/zpEii3evbuTyMYLOrE9o f+5JXka63YLzrQ1dWHhp8KszIPobtPlSwTkOz9Woom7FXXg6khs1+k9D3rvrZeZT64Ev wMG/+F5S1Zg3GDqOwxgqXk9EB1N9UhjWAtaCX/+oPegqMyBELLOZTkTFQCFX0RBsu7VH jiVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=W/6GhqTQcfqlcNRrFtgYEKVU2TeYfnuYg2H0Cp/aYxk=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=XpL5JYUBrqugzy3sLBsnn61ZbTMRfUkjJj2OHcWyT8xzD+NqsP0AVb6CUSvVAqRgpG /Ip3JqQZO7BBqH86gpPRutmBNY3y656UYEt4AN0kUVfodgG7WWlioS3Nesb9u261Mrhx IvTJRAWPpdIEgzYD2cTpgUG05avrgeHw+xS406kA16kY0Fthm3MTAr91IfQJkpfosgkC c6Tub8fBDQkOaGBXkV1VB2UfgIh8SrTnjlsgaPnayux6Oa0EF3ANCsMTFhICS5IjjmiY 00TKCBkaOsFZg8CKJpYMPo19a/1PxtHVfzhbjnkYMUfd+3cLR6mQdFI+3Nm92h65AjRI Ko1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EIqqd4WI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a18-20020a05610222d200b004627183d886si222941vsh.58.2023.11.23.06.39.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:39:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EIqqd4WI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Arc-0002WY-Ol; Thu, 23 Nov 2023 09:39:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6ArC-0002Bc-C7 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:09 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Ar7-0002Ui-F4 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:06 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4084de32db5so6416395e9.0 for ; Thu, 23 Nov 2023 06:39:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750339; x=1701355139; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W/6GhqTQcfqlcNRrFtgYEKVU2TeYfnuYg2H0Cp/aYxk=; b=EIqqd4WIz125yNdi260msYTdi+7NBJW7ZBQQ7NFppc6HSIFdaSILHMEGIFnSA954Ct 0/W4fXW23NiuonJaraD1YYUIRMxPWSsPZJWkRuErgDN2cExg+2uqfTI5WIBsRejSGHQ2 Ut307Oy8nFMQmSTDa9xK0nq7aXZrSKw5e8QYw6wa7B8Cf+3VCnWbqPDSgnYqaOIe5FkV NSmnQrFjyqI2RnhXCFQy7YtIFnWYcrfE1AQg+NwnKzDhzOIfHXngI+cjvAshx5aqP3d9 E3gSoayMf/K22+zO/pJ0M9g2cEyG4q+4eCUn/U9qn8EExoJVqbHvsuYGSiLaGMa6m5HN M0+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750339; x=1701355139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W/6GhqTQcfqlcNRrFtgYEKVU2TeYfnuYg2H0Cp/aYxk=; b=AyArZLCzp6GCsDcfyOcWsIwDnSjy97P/1+ydi3NR3gcpMV+DwgRnQ9fliK9ho+hiS3 MZVX31WpuVqRQ82OUT5vJEAwvWmJj8coyamIksTRBNwuIQQSu+mExVnvFQGkSpof90U5 UkAnEIJgJ9MWTaBCgGECH/vTXwyfiGwofJ4cqBF1rP/ycjuCzQm/e/ds9i6/vnzQKmCh ARWhGPgma80q4NfTBdrR+S39ZduBpv+wO/gAonp8qNyh/eT5jc4/WbvXuktyQxM63cIc W8vp2r/F+eECqzOMRrHlKa6FuYH/IjKCBKUf42P8kvulaC04rJ/bkQNDoJwvfZjaUFFf YhKw== X-Gm-Message-State: AOJu0YzJibAo9E987dFAB49rV8IkH5Panh2Uq8XePb1WsPgHKkmBW7Kl vGj1oeM2gqZbK3aLOI4Bwym7Kw== X-Received: by 2002:adf:e852:0:b0:332:e6ec:8306 with SMTP id d18-20020adfe852000000b00332e6ec8306mr427376wrn.25.1700750338912; Thu, 23 Nov 2023 06:38:58 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id k24-20020a5d5258000000b00332d04514b9sm1813510wrc.95.2023.11.23.06.38.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 5/8] hw: Prefer qdev_prop_set_bit over object_property_set_bool for QDev Date: Thu, 23 Nov 2023 15:38:09 +0100 Message-ID: <20231123143813.42632-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The QOM API is lower level than the QDev one. When an instance is QDev and setting the property can not fail (using &error_abort), prefer qdev_prop_set_bit() over object_property_set_bool(). Mechanical transformation using the following coccinelle patch: @@ expression o, p, v; @@ - object_property_set_bool(OBJECT(o), p, v, &error_abort) + qdev_prop_set_bit(DEVICE(o), p, v) @@@@ - object_property_set_bool(o, p, v, &error_abort) + qdev_prop_set_bit(DEVICE(o), p, v) manually adding the missing "hw/qdev-properties.h" header. In hw/arm/armsse.c we use the available 'cpudev' instead of 'cpuobj'. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Reviewed-by: Harsh Prateek Bora Reviewed-by: Peter Maydell --- hw/acpi/cpu_hotplug.c | 7 +++---- hw/acpi/ich9.c | 4 ++-- hw/acpi/piix4.c | 4 ++-- hw/arm/armsse.c | 3 +-- hw/arm/armv7m.c | 3 +-- hw/arm/aspeed_ast2400.c | 3 +-- hw/arm/aspeed_ast2600.c | 9 +++------ hw/arm/bcm2835_peripherals.c | 3 +-- hw/arm/bcm2836.c | 4 ++-- hw/arm/boot.c | 4 ++-- hw/arm/fsl-imx25.c | 3 +-- hw/arm/fsl-imx31.c | 3 +-- hw/arm/fsl-imx6.c | 12 ++++-------- hw/arm/fsl-imx6ul.c | 8 ++++---- hw/arm/fsl-imx7.c | 10 ++++------ hw/arm/npcm7xx.c | 9 +++------ hw/arm/xlnx-versal.c | 9 +++------ hw/arm/xlnx-zynqmp.c | 9 +++------ hw/core/bus.c | 2 +- hw/core/qdev.c | 2 +- hw/i386/pc_piix.c | 19 ++++++------------- hw/microblaze/petalogix_ml605_mmu.c | 5 ++--- hw/microblaze/xlnx-zynqmp-pmu.c | 18 +++++++----------- hw/mips/cps.c | 3 +-- hw/ppc/e500.c | 3 +-- hw/ppc/spapr_pci.c | 3 +-- hw/rx/rx-gdbsim.c | 4 ++-- hw/sparc/sun4m.c | 3 +-- 28 files changed, 64 insertions(+), 105 deletions(-) diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c index 634bbecb31..1338c037b5 100644 --- a/hw/acpi/cpu_hotplug.c +++ b/hw/acpi/cpu_hotplug.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "hw/acpi/cpu_hotplug.h" #include "qapi/error.h" +#include "hw/qdev-properties.h" #include "hw/core/cpu.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" @@ -41,8 +42,7 @@ static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, */ if (addr == 0 && data == 0) { AcpiCpuHotplug *cpus = opaque; - object_property_set_bool(cpus->device, "cpu-hotplug-legacy", false, - &error_abort); + qdev_prop_set_bit(DEVICE(cpus->device), "cpu-hotplug-legacy", false); } } @@ -66,8 +66,7 @@ static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, CPUState *cpu) cpu_id = k->get_arch_id(cpu); if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) { - object_property_set_bool(g->device, "cpu-hotplug-legacy", false, - &error_abort); + qdev_prop_set_bit(DEVICE(g->device), "cpu-hotplug-legacy", false); return; } diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 25e2c7243e..64b00673fe 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -30,6 +30,7 @@ #include "hw/pci/pci.h" #include "migration/vmstate.h" #include "qemu/timer.h" +#include "hw/qdev-properties.h" #include "hw/core/cpu.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -197,8 +198,7 @@ static bool vmstate_test_use_cpuhp(void *opaque) static int vmstate_cpuhp_pre_load(void *opaque) { ICH9LPCPMRegs *s = opaque; - Object *obj = OBJECT(s->gpe_cpu.device); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); + qdev_prop_set_bit(DEVICE(s->gpe_cpu.device), "cpu-hotplug-legacy", false); return 0; } diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index dd523d2e4c..215929ac6a 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -203,8 +203,8 @@ static bool vmstate_test_use_cpuhp(void *opaque) static int vmstate_cpuhp_pre_load(void *opaque) { - Object *obj = OBJECT(opaque); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); + DeviceState *dev = DEVICE(opaque); + qdev_prop_set_bit(dev, "cpu-hotplug-legacy", false); return 0; } diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 4672df180f..546b15e658 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -1022,8 +1022,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * later if necessary. */ if (extract32(info->cpuwait_rst, i, 1)) { - object_property_set_bool(cpuobj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(cpudev, "start-powered-off", true); } if (!s->cpu_fpu[i]) { if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index cbaebe9bf8..3a6d72b0f3 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -328,8 +328,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } - object_property_set_bool(OBJECT(s->cpu), "start-powered-off", - s->start_powered_off, &error_abort); + qdev_prop_set_bit(DEVICE(s->cpu), "start-powered-off", s->start_powered_off); /* * Real M-profile hardware can be configured with a different number of diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index a4334c81b8..4a247bfcbb 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -420,8 +420,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) /* Net */ for (i = 0; i < sc->macs_num; i++) { - object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->ftgmac100[i]), "aspeed", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b965fbab5e..5ec8ad73cd 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -317,10 +317,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, &error_abort); - object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, - &error_abort); - object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, - &error_abort); + qdev_prop_set_bit(DEVICE(&a->cpu[i]), "neon", false); + qdev_prop_set_bit(DEVICE(&a->cpu[i]), "vfp-d32", false); object_property_set_link(OBJECT(&a->cpu[i]), "memory", OBJECT(s->memory), &error_abort); @@ -500,8 +498,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) /* Net */ for (i = 0; i < sc->macs_num; i++) { - object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->ftgmac100[i]), "aspeed", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 0233038b95..c07ca8817b 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -303,8 +303,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_uint(OBJECT(&s->sdhci), "capareg", BCM2835_SDHC_CAPAREG, &error_abort); - object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->sdhci), "pending-insert-quirk", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index b0674a22a6..1fdc3be6bb 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -135,8 +135,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) bc->peri_base, &error_abort); /* start powered off if not enabled */ - object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", - n >= s->enabled_cpus, &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[n].core), "start-powered-off", + n >= s->enabled_cpus); if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { return; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 84ea6a807a..ebed887e5e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include +#include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" #include "sysemu/kvm.h" @@ -1287,8 +1288,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) * CPU. */ if (cs != first_cpu) { - object_property_set_bool(cpuobj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(cpuobj), "start-powered-off", true); } } } diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 9aabbf7f58..fc6a7c8a8b 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -272,8 +272,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) } /* Watchdog */ - object_property_set_bool(OBJECT(&s->wdt), "pretimeout-support", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt), "pretimeout-support", true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0, diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index def27bb913..71f50ca802 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -171,8 +171,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } }; - object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", false, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->gpio[i]), "has-edge-sel", false); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { return; } diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 7dc42cbfe6..17c399a37e 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -128,8 +128,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) /* All CPU but CPU 0 start in power off mode */ if (i) { - object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "start-powered-off", true); } if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { @@ -288,10 +287,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) }, }; - object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, - &error_abort); - object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->gpio[i]), "has-edge-sel", true); + qdev_prop_set_bit(DEVICE(&s->gpio[i]), "has-upper-pin-irq", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { return; } @@ -412,8 +409,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) FSL_IMX6_WDOG2_IRQ, }; - object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt[i]), "pretimeout-support", true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index e37b69a5e1..4f4f2a6f41 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -410,8 +410,8 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) * and we have to set all properties before calling sysbus_realize(). */ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { - object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", - s->phy_connected[i], &error_abort); + qdev_prop_set_bit(DEVICE(&s->eth[i]), "phy-connected", + s->phy_connected[i]); /* * If the MDIO bus on this controller is not connected, assume the * other controller provides support for it. @@ -542,8 +542,8 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_WDOG3_IRQ, }; - object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt[i]), "pretimeout-support", + true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 474cfdc87c..3138ffeb08 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -192,8 +192,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) * Secondary CPUs start in powered-down state (and can be * powered up via the SRC system reset controller) */ - object_property_set_bool(o, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(o), "start-powered-off", true); } qdev_realize(DEVICE(o), NULL, &error_abort); @@ -424,8 +423,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) * and we have to set all properties before calling sysbus_realize(). */ for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { - object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", - s->phy_connected[i], &error_abort); + qdev_prop_set_bit(DEVICE(&s->eth[i]), "phy-connected", + s->phy_connected[i]); /* * If the MDIO bus on this controller is not connected, assume the * other controller provides support for it. @@ -513,8 +512,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_WDOG4_IRQ, }; - object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt[i]), "pretimeout-support", true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d047..7022df3cfa 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -478,12 +478,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); - object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "reset-hivecs", true); /* Disable security extensions. */ - object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "has_el3", false); if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { return; @@ -613,8 +611,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) } /* USB Host */ - object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->ehci), "companion-enable", true); sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 9600551c44..e3b730f5f5 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -48,8 +48,7 @@ static void versal_create_apu_cpus(Versal *s) obj = OBJECT(&s->fpd.apu.cpu[i]); if (i) { /* Secondary CPUs start in powered-down state */ - object_property_set_bool(obj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); } object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), @@ -150,8 +149,7 @@ static void versal_create_rpu_cpus(Versal *s) "rpu-cpu[*]", &s->lpd.rpu.cpu[i], XLNX_VERSAL_RCPU_TYPE); obj = OBJECT(&s->lpd.rpu.cpu[i]); - object_property_set_bool(obj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), @@ -536,8 +534,7 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic) &s->pmc.iou.ospi.dma_src, TYPE_XLNX_CSU_DMA); - object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", - false, &error_abort); + qdev_prop_set_bit(DEVICE(&s->pmc.iou.ospi.dma_src), "is-dst", false); object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), "dma", OBJECT(mr_dac), &error_abort); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5905a33015..f3ca3a7527 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -237,14 +237,12 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, /* * Secondary CPUs start in powered-down state. */ - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), - "start-powered-off", true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->rpu_cpu[i]), "start-powered-off", true); } else { s->boot_cpu_ptr = &s->rpu_cpu[i]; } - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->rpu_cpu[i]), "reset-hivecs", true); if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { return; } @@ -518,8 +516,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) /* * Secondary CPUs start in powered-down state. */ - object_property_set_bool(OBJECT(&s->apu_cpu[i]), - "start-powered-off", true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->apu_cpu[i]), "start-powered-off", true); } else { s->boot_cpu_ptr = &s->apu_cpu[i]; } diff --git a/hw/core/bus.c b/hw/core/bus.c index c7831b5293..a24ebe5886 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -176,7 +176,7 @@ bool qbus_realize(BusState *bus, Error **errp) void qbus_unrealize(BusState *bus) { - object_property_set_bool(OBJECT(bus), "realized", false, &error_abort); + qdev_prop_set_bit(DEVICE(bus), "realized", false); } static bool bus_get_realized(Object *obj, Error **errp) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 43d863b0c5..f4aa99ed77 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -303,7 +303,7 @@ bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp) void qdev_unrealize(DeviceState *dev) { - object_property_set_bool(OBJECT(dev), "realized", false, &error_abort); + qdev_prop_set_bit(dev, "realized", false); } static int qdev_assert_realized_properly_cb(Object *obj, void *opaque) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index eace854335..6733652120 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -263,20 +263,13 @@ static void pc_init1(MachineState *machine, size_t i; pci_dev = pci_new_multifunction(-1, pcms->south_bridge); - object_property_set_bool(OBJECT(pci_dev), "has-usb", - machine_usb(machine), &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-acpi", - x86_machine_is_acpi_enabled(x86ms), - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pic", false, - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pit", false, - &error_abort); - qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); - object_property_set_bool(OBJECT(pci_dev), "smm-enabled", - x86_machine_is_smm_enabled(x86ms), - &error_abort); dev = DEVICE(pci_dev); + qdev_prop_set_bit(dev, "has-usb", machine_usb(machine)); + qdev_prop_set_bit(dev, "has-acpi", x86_machine_is_acpi_enabled(x86ms)); + qdev_prop_set_bit(dev, "has-pic", false); + qdev_prop_set_bit(dev, "has-pit", false); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + qdev_prop_set_bit(dev, "smm-enabled", x86_machine_is_smm_enabled(x86ms)); for (i = 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); } diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index fb7889cf67..626f9b0b56 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -88,9 +88,8 @@ petalogix_ml605_init(MachineState *machine) * root instructions */ object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); - object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, - &error_abort); - object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort); + qdev_prop_set_bit(DEVICE(cpu), "dcache-writeback", true); + qdev_prop_set_bit(DEVICE(cpu), "endianness", true); qdev_realize(DEVICE(cpu), NULL, &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index 5a2016672a..19cc5efee3 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "exec/address-spaces.h" +#include "hw/qdev-properties.h" #include "hw/boards.h" #include "cpu.h" #include "boot.h" @@ -79,19 +80,14 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) object_property_set_uint(OBJECT(&s->cpu), "base-vectors", XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-stack-protection", true); object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort); object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true, - &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true, - &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true, - &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "endianness", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-barrel", true); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-msr-instr", true); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-pcmp-instr", true); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-mmu", false); + qdev_prop_set_bit(DEVICE(&s->cpu), "endianness", true); object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b", &error_abort); object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4f12e23ab5..ee2a8d5563 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -78,8 +78,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) CPUMIPSState *env = &cpu->env; /* All VPs are halted on reset. Leave powering up to CPC. */ - object_property_set_bool(OBJECT(cpu), "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", true); /* All cores use the same clock tree */ qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 566f1200dd..a63d48c512 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -954,8 +954,7 @@ void ppce500_init(MachineState *machine) * Secondary CPU starts in halted state for now. Needs to change * when implementing non-kernel boot. */ - object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, - &error_abort); + qdev_prop_set_bit(DEVICE(cs), "start-powered-off", i != 0); qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); if (!firstenv) { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 6760823e13..266cf6c9e6 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2490,8 +2490,7 @@ static int spapr_switch_one_vga(DeviceState *dev, void *opaque) || object_dynamic_cast(OBJECT(dev), "secondary-vga") || object_dynamic_cast(OBJECT(dev), "bochs-display") || object_dynamic_cast(OBJECT(dev), "virtio-vga")) { - object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, - &error_abort); + qdev_prop_set_bit(dev, "big-endian-framebuffer", be); } return 0; } diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 47c17026c7..53d3d560c8 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -21,6 +21,7 @@ #include "qemu/error-report.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include "hw/qdev-properties.h" #include "hw/loader.h" #include "hw/rx/rx62n.h" #include "sysemu/qtest.h" @@ -103,8 +104,7 @@ static void rx_gdbsim_init(MachineState *machine) &error_abort); object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", rxc->xtal_freq_hz, &error_abort); - object_property_set_bool(OBJECT(&s->mcu), "load-kernel", - kernel_filename != NULL, &error_abort); + qdev_prop_set_bit(DEVICE(&s->mcu), "load-kernel", kernel_filename != NULL); if (!kernel_filename) { if (machine->firmware) { diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 64895aebe3..d631d555d8 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -803,8 +803,7 @@ static void cpu_devinit(const char *cpu_type, unsigned int id, env = &cpu->env; qemu_register_reset(sun4m_cpu_reset, cpu); - object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, - &error_abort); + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", id != 0); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); cpu_sparc_set_id(env, id); *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); From patchwork Thu Nov 23 14:38:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746476 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp913946wru; Thu, 23 Nov 2023 06:40:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IH4KjRNazVvXOt5iPYHmUOha3zcweBlYWazbXBJqa+9vj51bfhd//wWCY+a3aMttcSsB2t0 X-Received: by 2002:ad4:5dcc:0:b0:66d:6526:d605 with SMTP id m12-20020ad45dcc000000b0066d6526d605mr5679834qvh.63.1700750421357; Thu, 23 Nov 2023 06:40:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750421; cv=none; d=google.com; s=arc-20160816; b=IxADH6aEil1OYb7ujCVtKTJpyAYuA5UPVtIe26EToZihEiBWjqk/MhFxiS591KqKSE kqMuIiW/fRvkUPI71tO+OtvlexDmVfo0vKi/AkysUJUsYOpBZVfJcPTe9MMeL9vuoYi2 Ht+S8KCXiYB+LuitRRwkRb8D3Yz92gQ6kHp1De5LzAowwKITLYrZwmAYFL7naxtSUzjO mI1vtBQ7lrusE1eht/0Ah/o36RgT7Yf2D28Gpa1ekXiaNnEXb0JVIqqCNBeqHCZq4Bqc FQdTN1Pgv6gqYff8hI1RVKuNDGv6dEP8WTeUDDbAeQ3HFdi6mOuDRAT58rCddJjrSPWG cpYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dGiTJB8vH4At7R/cLAjNpyQTepWZvh1pzfnI30rm26o=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=owjMse3OphRfb+uJSBOf2pXTVZprH6Le2bkVYapsVUv7RIrHIP6DznN6++6PF7NMAi iQjbuLMi02iGFlmQQ3U9VGLiWUELFYYHx47DJE7w7zyMROs0ar4gBVuF3dZQw2rkVCpT qH2mf61HC2ioJQPT8BcDHtTfo7e8YKtmDciDKdnGof8jUQT/SRCZxcOrdBwklcvTe9C+ qF/Q5ufimj7KY6XpDcckFkKMhkSAm8HEnC+jjA4gcw6o0aDvDj1OPedrUfa+jTiTkCp3 9J102zfyLBr4eoDoqibZy454BIzY5B19XaFcL4R3VGO0PEOZzzo/OGLgj/KnQ8xM38BL wchw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a4rnnAa7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k13-20020ad4450d000000b0067a058155fasi1240953qvu.116.2023.11.23.06.40.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:40:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a4rnnAa7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6As9-0003X3-V4; Thu, 23 Nov 2023 09:40:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6ArG-0002Dt-Jr for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:13 -0500 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6ArE-0002Vt-Ou for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:10 -0500 Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2c83d37a492so12016231fa.3 for ; Thu, 23 Nov 2023 06:39:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750347; x=1701355147; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dGiTJB8vH4At7R/cLAjNpyQTepWZvh1pzfnI30rm26o=; b=a4rnnAa7w1+vrwFNFCdho6mZBoQJx9Cmlz9oa5gkUMbcN46fPNbWuP5vIi5l54KCmz O73nY0jl2DnvnUjC0bGF5uaFSKI7ZyVIXJQGEOzEwAOHHKcFhPtYmtRqZEy986WnI8JJ LTssH2/8tYEar04i0K7QgopFFnmCHdDzEOkRy+coY/CKl/QFC8bjjJuJ1A4vHNj1YFrC uE1xNMqGICKxuxwm+pbF/eYnRkwN2dkIhAKDhEg/pWDCL+z/TUXxg61/SL0tsj4Cg1RO XIIwmy4K/yhY7/2X4Ydsqo5u6olDF+bGP3obXWTaF0pg1DuCRxZMJoqStp5gUdB6B520 iCow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750347; x=1701355147; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGiTJB8vH4At7R/cLAjNpyQTepWZvh1pzfnI30rm26o=; b=DwdaZavxhzdisaR6Tp88q1t4tVrwcmHgGyoEnDjkV/nfp2JRjfaN+fKiBUK+YD4vzh UMeFL12ZMBqZlxA6yqnNwq7GvR4DftgzE1nzTFmLD0vH1o7LA0EwybxgE3MqIab0hM/z sVk+zW+h01u4W+9L3akZPn0pw6oWnGN5fVHWQy5jGXFmQSX1214omy2zYjUInhc4yprb 9hKFjs9ggZUBZNqcFL3dMvfZ53haECdINEYYmofLz7iW2kFUWfXA5pjwVg23dzT06PRi 53WBgDgrgeJjRZKodfePNrt2dY4fnf9J00G4Md6djEkUEydjlWJlLwu661xLcILtX9aH cIAg== X-Gm-Message-State: AOJu0YySzDLTdgmZJXqJQcmNLcBMxqQpL1SSqgVPXf1mi7vABpq+ieyn m6Jr80Rj0/FQIxNvnJdJBczpBg== X-Received: by 2002:a05:651c:19a4:b0:2c8:3888:bbb2 with SMTP id bx36-20020a05651c19a400b002c83888bbb2mr4569717ljb.38.1700750347065; Thu, 23 Nov 2023 06:39:07 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id d5-20020a05600c34c500b0040b349c91acsm2922438wmq.16.2023.11.23.06.39.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:39:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 6/8] hw: Simplify uses of qdev_prop_set_bit(dev, 'start-powered-off') Date: Thu, 23 Nov 2023 15:38:10 +0100 Message-ID: <20231123143813.42632-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Simplify few qdev_prop_set_bit("start-powered-off") and re-indent. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/arm/allwinner-h3.c | 3 +-- hw/arm/allwinner-r40.c | 3 +-- hw/arm/bcm2836.c | 4 ++-- hw/arm/fsl-imx6.c | 4 +--- hw/arm/fsl-imx7.c | 12 +++++------- 5 files changed, 10 insertions(+), 16 deletions(-) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index f05afddf7e..593244464a 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -251,8 +251,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) * Disable secondary CPUs. Guest EL3 firmware will start * them via CPU reset control registers. */ - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", - i > 0); + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", i > 0); /* All exception levels required */ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index a0d367c60d..202a158fb8 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -304,8 +304,7 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp) * Disable secondary CPUs. Guest EL3 firmware will start * them via CPU reset control registers. */ - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", - i > 0); + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", i > 0); /* All exception levels required */ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 1fdc3be6bb..03e6eb2fb2 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -99,9 +99,9 @@ static void bcm2835_realize(DeviceState *dev, Error **errp) /* Connect irq/fiq outputs from the interrupt controller. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); } static void bcm2836_realize(DeviceState *dev, Error **errp) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 17c399a37e..b7f1738a89 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -127,9 +127,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) } /* All CPU but CPU 0 start in power off mode */ - if (i) { - qdev_prop_set_bit(DEVICE(&s->cpu[i]), "start-powered-off", true); - } + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "start-powered-off", i > 0); if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { return; diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 3138ffeb08..451801f7e8 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -187,13 +187,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) &error_abort); } - if (i) { - /* - * Secondary CPUs start in powered-down state (and can be - * powered up via the SRC system reset controller) - */ - qdev_prop_set_bit(DEVICE(o), "start-powered-off", true); - } + /* + * Secondary CPUs start in powered-down state (and can be + * powered up via the SRC system reset controller) + */ + qdev_prop_set_bit(DEVICE(o), "start-powered-off", i > 0); qdev_realize(DEVICE(o), NULL, &error_abort); } From patchwork Thu Nov 23 14:38:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746477 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp914079wru; Thu, 23 Nov 2023 06:40:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IE6x96tJbrtddH8bfgvHjv194qP28W2fiDFZsULzBpM0Ew8YfodazVfnUuermjVBFYUnSJC X-Received: by 2002:a05:6830:13d5:b0:6d6:47e5:af6d with SMTP id e21-20020a05683013d500b006d647e5af6dmr5895923otq.13.1700750437220; Thu, 23 Nov 2023 06:40:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750437; cv=none; d=google.com; s=arc-20160816; b=VrAugTWdexBiRhjIqmiYHk2q9wyoooLj0+9Fr4csab/EaeOlQ9pOEnHK6FLSyrznXs AaLXznNzQU4yd3fp2JblZVho/ezDjGYiU4C1WFHqgXSfSJK82YR9j823Zb98pxMvPk0F hLgu+uKp5jio+J0LooIrqMkrRjDcJfzvKEz2wLEuuK/WvXSnw7DhYKTX2MkeF1OdzvIi HaSf/07gr82LA9lqc1K4a2HV55VRGhBLDctFCFDB4BsydyAkU5Kqpl05zPkAH03XwFM8 isWGvNdO+qibhFJW8oC7z/cEw5uSsbOKz/2d3GqvX5vT22k1YY8+fX3uabpWcu3ktG47 92XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1237N1r1qCpcYS004kuUN2TuaGy1OnSXggczIa7nXrE=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=Cpuen7B+PDGVJnmwNQSHcTUT/IG6JWGgYCeHRYZ3QgTAZyg9V/jGeLHoN6vb7TF+x8 IXARaO6QlzJ28jhoycl2Mzszdufk6OZhYtxbs2Rk1EWAEgS6ia7tXSLs7rDr6bJiBcGE aGMuWZGq3usCZ6BCeaiVNow3GuZOUEo+M+RKvox+24ifu3GXFLdVJuMtBsWiRAKovx+G 9hPy3ACn2CJxtYwBSC1fYXD32YKaPJVOk9x7jBVTRTd2hG0m7t0Go8J8oq1+nJ366nn7 7gyFk8OmED6KKfzQ/zh74JN+gHnDrOQhk720rNf1pn94irSp13KYqJ6qk2ihHuxNWAej +cvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A6cMCvgE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id pm17-20020ad446d1000000b0065afe121fc8si1281321qvb.150.2023.11.23.06.40.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:40:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A6cMCvgE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6As3-0003VB-MO; Thu, 23 Nov 2023 09:39:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6ArO-0002Os-VH for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:20 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6ArM-0002XD-FI for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:18 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40b27b498c3so6520395e9.0 for ; Thu, 23 Nov 2023 06:39:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750355; x=1701355155; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1237N1r1qCpcYS004kuUN2TuaGy1OnSXggczIa7nXrE=; b=A6cMCvgEw1QkQiHYWTKMdIVR+vq7ld76SmijW1AfxYgE0sxaPNxHg+zHx3jdHOWyYW P/nRmi3ZR3Gr50yWlrx/7PFFEEjDCHxtqH2p5NDDJANwXOPDAWLuyKizuK/UO/gcnYBj 4MS42ogdGmA5I0ws/YUdmHTeX0ebJjB7HdBPIQFVip+MATOfGcfXSpTpXqzmv2cUjEKI yu1jmlktpxmbBfYwoDyZbPx/XCkkX6rr9tSQXxLbQhNDk9bYg+JGS1oBz/b25OYui8yc uVByGRhNsTtPG5edemKqk60R+diIGn80LoOwBemn4ZF5Xx/GydRsbzsqvF2tvb8KWauy z2sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750355; x=1701355155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1237N1r1qCpcYS004kuUN2TuaGy1OnSXggczIa7nXrE=; b=tUc0pp9ODFqUPb1LpAmdGzdd6Uzhj281H4Q4VBMMXevmqBy/cLSeFTm/hIKS+Cxtuj YPQL3lH0DWaIQYAB2zCnbWWb1diE08NRJCtu+zDCBRtnTQcrjQm4iNXX+yY/UbZ/euIx H7e7959Bd3KfP6Rtj6iDgmGq1BXMus9hf9v3Rqi4dHpLluGS/znbsPzwnibbVOgqnoKD PeOisSBPGH6Cwp+/13toUzxy1srcdzmXOTT54dgc+29VognhAdxvzBlw0nx0vReRuPRx nn9CdUFoWoNI9zeTetk1ce8GIYGDF42Xe/t+6MWq4/9fcczLUHfkzx+6s18zcSy//B+N jY2g== X-Gm-Message-State: AOJu0YzkI5Y0qSXFEme5sb4wvOaR28YegVcXlumQYQ/7ntZDyiq/fOQO uDhuSUQqisOHg2QAExTfsxXly8gs1CVtuUvSEwU= X-Received: by 2002:a05:600c:4703:b0:40b:38a8:6c65 with SMTP id v3-20020a05600c470300b0040b38a86c65mr405199wmo.26.1700750355139; Thu, 23 Nov 2023 06:39:15 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id z4-20020a1c4c04000000b0040b32edf626sm2163708wmf.31.2023.11.23.06.39.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:39:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 7/8] hw/arm/bcm2836: Move code after error checks Date: Thu, 23 Nov 2023 15:38:11 +0100 Message-ID: <20231123143813.42632-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org First run the code that can return errors, then on success run what alters the instance state. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 03e6eb2fb2..e56935f3e5 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -119,13 +119,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); - for (n = 0; n < BCM283X_NCPUS; n++) { object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", (bc->clusterid << 8) | n, &error_abort); @@ -158,6 +151,13 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, + qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, + qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); } static void bcm283x_class_init(ObjectClass *oc, void *data) From patchwork Thu Nov 23 14:38:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746479 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp914372wru; Thu, 23 Nov 2023 06:41:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IFl8i6eirLZwnH9UhopY5facE1gFXx24B8xxHlQ0zwq1kPpeiK00EH9IKJnGBb/B34ALJpO X-Received: by 2002:a05:6214:c63:b0:655:d9b1:7980 with SMTP id t3-20020a0562140c6300b00655d9b17980mr5844778qvj.62.1700750471469; Thu, 23 Nov 2023 06:41:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700750471; cv=none; d=google.com; s=arc-20160816; b=Gpu7aQBQpLLT0CLBD/wSJMsKapbCDKvOIsxMNiKxhtgf6ogaTOzKHwaiAVPNafaVXL ShkgiNlUBj0hRuXuEERBUEBUfUxASkFrCfkDZqrGrtEBBSthKeuGmNJ2E+Jbcg3YlIpr PBLoaTsKFZvLLZbOlju/IsbnZfPrO18OhkSS8WlUBSpyWMvXzPUnF+dHwWuqDfHUC4nK BXaOuWD8vjU63Dc1+WmgsLUPxLsbJXcKFHWj2kLqlGfh/moJiWML+NcT1cdn9MA4SB8M TqO3zSnS+KP9o5TPL7tlNQxNzgkETn8aVpMhLZ9ssuX3wUKwzbavxgRoJdf8+R/060wM 1iUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SliH/Dd/Fz40g7/vYVgjwfZm7k8MHl78S5VUvr4CFSQ=; fh=xd8Hqo+FyqINTpmMuSlnP3D7Rh8IYP9KQ4AY72o61pU=; b=UL44KzvgkB7LI0im6yodzx4c2dyUg1sEbJGfjlyNAdIaoNId9X/ERNjj94sTWQpOEd Ol0fAxEDcEUBkED22aEaLI124ZQNgpH5/24/IHJMVqD3o1uXOtavH371pGTQAflOmgJS BsJ/pnDk1fAtzUWnJDADgoNwvhG6LcXG6UTybPgb3z4cek6D4rn1Ayzsn6Pzo0EYPyHU ykA9aVIa3sjjOk4woMcHTTj42JQqkUyzi69cwTdnLzhjkVBw5YIjbC+qlfDiZU0DCDwc 2rlV2x4woF7VuN1WiT1cYheBYcknr3D5pV8q6TZeY3GnRZ5Sur7vXpeRIWVpANPPEL3E BQ9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iFafsJXZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id nh6-20020a056214390600b0067a085aaaf0si1037771qvb.4.2023.11.23.06.41.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 23 Nov 2023 06:41:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iFafsJXZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6As1-0003I1-3h; Thu, 23 Nov 2023 09:39:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6ArW-0002Xj-FI for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:28 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6ArU-0002Zs-Rb for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:39:26 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-332cc1f176bso626535f8f.2 for ; Thu, 23 Nov 2023 06:39:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750363; x=1701355163; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SliH/Dd/Fz40g7/vYVgjwfZm7k8MHl78S5VUvr4CFSQ=; b=iFafsJXZxbcp88GW/FzAYVOkEQPtcwTIZzLN0TTUmNJ17DhomDt2bF+WmiUQi7+cya npUHLlF3rJNtxx9X2a7SRXYKJPM6xisYGjXsfASR2P6hx3yVbFsxWnZvvND9k44m91VE btDJ3YLLE5/cS3BqND+YCjPqv8fCcsgaA4vBO4YFh4JsVZvd1m9eaj9EIn8ANEzvWy3N gP8Oo2sxkOljQVQ7V7BoI8/dqtkmBcmgcIOKd20RBvGn2qbRUwd7Av0uE0Ob7JS9P4W9 lwEXWZa5cvcOLPTWNHxe1eKu6DylEmUPetzg6kiAIgcCSsqVUMZEf0P8VGCa0+mPw/S+ c4eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750363; x=1701355163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SliH/Dd/Fz40g7/vYVgjwfZm7k8MHl78S5VUvr4CFSQ=; b=fNMRqwBGGgBp1H6y0exjRRz+szU/CFvSr8DCY2rUfa4+2SksP4dDoYDzXO238YjWn/ 3YHfaOozmauUXo5XYCDHeNYeMBgk8mnuwAvC1vmmppuYae15LsZDrkHQHbgnaBiW8JWY 2vOFMFCmaprEdG3z2fa/kNlBvz0d108dPYAm/Q8b6RLkN4R/7IeoAAdFcktytTEher/3 Og4QjU0jpF+wuGuAV6/P8BRfpIKJb13vk8WXiUQNI6tQLIuJ5PaPji4L5NlWDCc2EOXr rq+3rRDwIXK1wgQsA4I2dR3SjgWfcluMxkqWqwSRmOsuFH1WBwTbMHsgCiPR6bSWW/kg uP1g== X-Gm-Message-State: AOJu0YzMRb2REkfHT7O9uzWvsqDFlAbc2CMShfi5HiPGPbwrjt/A1LQm isQ/So9oBeiQ8Z30HXCSmd3HIA== X-Received: by 2002:a5d:47c7:0:b0:332:cb51:34ed with SMTP id o7-20020a5d47c7000000b00332cb5134edmr4585550wrc.54.1700750363110; Thu, 23 Nov 2023 06:39:23 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id t15-20020a5d6a4f000000b0033169676e83sm1806159wrw.13.2023.11.23.06.39.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:39:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 8/8] hw/arm/bcm2836: Add local variable to remove various DEVICE() casts Date: Thu, 23 Nov 2023 15:38:12 +0100 Message-ID: <20231123143813.42632-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Cast the CPU to DeviceState once. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index e56935f3e5..013cee853d 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -120,6 +120,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } for (n = 0; n < BCM283X_NCPUS; n++) { + DeviceState *cpudev = DEVICE(&s->cpu[n].core); + object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", (bc->clusterid << 8) | n, &error_abort); @@ -128,27 +130,26 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) bc->peri_base, &error_abort); /* start powered off if not enabled */ - qdev_prop_set_bit(DEVICE(&s->cpu[n].core), "start-powered-off", - n >= s->enabled_cpus); + qdev_prop_set_bit(cpudev, "start-powered-off", n >= s->enabled_cpus); - if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + if (!qdev_realize(cpudev, NULL, errp)) { return; } /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, + qdev_connect_gpio_out(cpudev, GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, + qdev_connect_gpio_out(cpudev, GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, + qdev_connect_gpio_out(cpudev, GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, + qdev_connect_gpio_out(cpudev, GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); }