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Wed, 22 Nov 2023 07:23:06 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Wed, 22 Nov 2023 23:23:03 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Tim Lunn , Jagan Teki , Rob Herring , linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 2/9] ARM: dts: rockchip: rv1126: Serial aliases Date: Wed, 22 Nov 2023 23:22:25 +1100 Message-Id: <20231122122232.952696-3-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231122122232.952696-1-tim@feathertop.org> References: <20231122122232.952696-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add serial aliases for uart nodes so that serial devices are created Signed-off-by: Tim Lunn --- (no changes since v1) arch/arm/boot/dts/rockchip/rv1126.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 9ccd1bad6229..6c5c928f06c7 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -21,6 +21,11 @@ / { aliases { i2c0 = &i2c0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; }; cpus { From patchwork Wed Nov 22 12:22:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 746177 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=feathertop.org header.i=@feathertop.org header.b="Za2T+ROj"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="hZ/mwYQn" Received: from wout2-smtp.messagingengine.com (wout2-smtp.messagingengine.com [64.147.123.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DE5C98 for ; Wed, 22 Nov 2023 04:23:45 -0800 (PST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.west.internal (Postfix) with ESMTP id 2F3823200B11; Wed, 22 Nov 2023 07:23:44 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 22 Nov 2023 07:23:45 -0500 DKIM-Signature: v=1; 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Wed, 22 Nov 2023 07:23:38 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Wed, 22 Nov 2023 23:23:35 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Tim Lunn , Jagan Teki , Rob Herring , linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 5/9] ARM: dts: rockchip: rv1126: Split up rgmii1 pinctrl Date: Wed, 22 Nov 2023 23:22:28 +1100 Message-Id: <20231122122232.952696-6-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231122122232.952696-1-tim@feathertop.org> References: <20231122122232.952696-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Split up the pinctrl definitions for rgmii1 so it can be shared with devices using an RMII PHY. Signed-off-by: Tim Lunn --- (no changes since v1) .../dts/rockchip/rv1126-edgeble-neu2-io.dts | 2 +- .../arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 46 +++++++++++++------ 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index f09be8405964..0c2396b8f8db 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -61,7 +61,7 @@ &gmac { phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>; tx_delay = <0x2a>; rx_delay = <0x1a>; status = "okay"; diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 167a48afa3a4..06b1d7f2d858 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -115,36 +115,56 @@ pwm11m0_pins: pwm11m0-pins { }; rgmii { /omit-if-no-ref/ - rgmiim1_pins: rgmiim1-pins { + rgmiim1_miim: rgmiim1-miim { rockchip,pins = /* rgmii_mdc_m1 */ <2 RK_PC2 2 &pcfg_pull_none>, /* rgmii_mdio_m1 */ - <2 RK_PC1 2 &pcfg_pull_none>, - /* rgmii_rxclk_m1 */ - <2 RK_PD3 2 &pcfg_pull_none>, + <2 RK_PC1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_rxer: rgmiim1-rxer { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_bus2: rgmiim1-bus2 { + rockchip,pins = /* rgmii_rxd0_m1 */ <2 RK_PB5 2 &pcfg_pull_none>, /* rgmii_rxd1_m1 */ <2 RK_PB6 2 &pcfg_pull_none>, - /* rgmii_rxd2_m1 */ - <2 RK_PC7 2 &pcfg_pull_none>, - /* rgmii_rxd3_m1 */ - <2 RK_PD0 2 &pcfg_pull_none>, /* rgmii_rxdv_m1 */ <2 RK_PB4 2 &pcfg_pull_none>, - /* rgmii_txclk_m1 */ - <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd0_m1 */ <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd1_m1 */ <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_bus4: rgmiim1-bus4 { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd2_m1 */ <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd3_m1 */ - <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txen_m1 */ - <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_mclkinout: rgmiim1-mclkinout { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>; }; }; sdmmc0 { From patchwork Wed Nov 22 12:22:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 746176 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=feathertop.org header.i=@feathertop.org header.b="MiO1O0W5"; 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Wed, 22 Nov 2023 07:23:58 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Wed, 22 Nov 2023 23:23:55 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Tim Lunn , Jagan Teki , Rob Herring , linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 7/9] ARM: dts: rockchip: Add rv1109 SoC Date: Wed, 22 Nov 2023 23:22:30 +1100 Message-Id: <20231122122232.952696-8-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231122122232.952696-1-tim@feathertop.org> References: <20231122122232.952696-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Rockchip rv1109 SoC is a dual core version of the rv1126. It is otherwise identical and shares the same device tree config. This patch introduces a dtsi file to drop the additional cpu nodes. Taken from Rockchip BSP kernel. Signed-off-by: Tim Lunn --- Changes in v2: - new patch arch/arm/boot/dts/rockchip/rv1109.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip/rv1109.dtsi diff --git a/arch/arm/boot/dts/rockchip/rv1109.dtsi b/arch/arm/boot/dts/rockchip/rv1109.dtsi new file mode 100644 index 000000000000..9cbaa08ab1b8 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1109.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1126.dtsi" + +/ { + compatible = "rockchip,rv1109"; + + cpus { + /delete-node/ cpu@f02; + /delete-node/ cpu@f03; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; From patchwork Wed Nov 22 12:22:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 746175 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=feathertop.org header.i=@feathertop.org header.b="orAdH6jK"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="o26A5FaI" Received: from wout2-smtp.messagingengine.com (wout2-smtp.messagingengine.com [64.147.123.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B0FCBB for ; Wed, 22 Nov 2023 04:24:25 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 0F8AA3200B1D; Wed, 22 Nov 2023 07:24:23 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Wed, 22 Nov 2023 07:24:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=feathertop.org; h=cc:cc:content-transfer-encoding:content-type:date:date:from :from:in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1700655863; x= 1700742263; bh=5N+6zMeQUJaK0yTZzxT4LTC1/MrDx41jPB5ONB6aYCc=; b=o rAdH6jK6kl0cou2igxniaKRkUsdQYSFVOX5h2BXQ9tHN7LiiPBGQoI8uNSIddZ06 DUfPKlsIuyjrIa+zu0UoEDJUNNCnhnyB03Ecxey7IA39Nhisy18GFAa5m/uA/8TV 3SM6Bk/+ff47XFxP4HF5pLfFjGqOoJZ6G7/tmVZrKo2viNIb4f/C7gX+wkyyQ+iN 6KNizMnB/muBNj4Zigje0mH6J95u3OIU5zUf0aNwRUXUOnsA0XqlgfNFFTOaC90E enFJrAz7tn/HE90c9S4uMa6TbpAYbihQil6iXfUcapPGT8kcgWcg2Uy9qJI+8ZYf 2dtaNrEOyWODo2Ja5rhKw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1700655863; x= 1700742263; bh=5N+6zMeQUJaK0yTZzxT4LTC1/MrDx41jPB5ONB6aYCc=; b=o 26A5FaIsNCQeega88cpk0h/3fh7X7Sfkrf17GmXhTeW1iiQBaWvxC5bkOerxcJJU 4jjNKauHcvEMIRuwc9U4MJq/TYbAEsdm7FzY8SdsFZTA1ClloLfz6Tdw47DgaKTC HEtyRBVfrhKyk+vvV5fYSHXHv1B0Ev6FXl5sYA/d+ryGzHYqT4755mi/JHLvaOtV nhJqXs/hMoJN0xuhoETpnxJySc8I7z6kOLihwnXE0KW6RQbzFxRyypdz6qtv89xd maJQY/pZx97QQR/ddEcMCLjsVR9gcJs1zdVQt7cM2pm4GEqu4Fj7JBraUByWst7E Bgtkfb7SwXnCnP6S55GRg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrudehuddgfeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepvfhimhcu nfhunhhnuceothhimhesfhgvrghthhgvrhhtohhprdhorhhgqeenucggtffrrghtthgvrh hnpeefffeuhfetgeeikeejvefgtdefteehgfdvhfetfeeuffeuhffhfeekgfekgeehieen ucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehtihhmse hfvggrthhhvghrthhophdrohhrgh X-ME-Proxy: Feedback-ID: i1f8241ce:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 22 Nov 2023 07:24:18 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Wed, 22 Nov 2023 23:24:15 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Tim Lunn , Jagan Teki , Rob Herring , linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Krzysztof Kozlowski , Conor Dooley , Rob Herring Subject: [PATCH v2 9/9] dt-bindings: arm: rockchip: Add Sonoff iHost Date: Wed, 22 Nov 2023 23:22:32 +1100 Message-Id: <20231122122232.952696-10-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231122122232.952696-1-tim@feathertop.org> References: <20231122122232.952696-1-tim@feathertop.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sonoff iHost is a smart home hub with built in radios for wifi/bt and Zigbee. It is based off the Rockchip RV1126 (or RV1109) SoC. Signed-off-by: Tim Lunn Acked-by: Rob Herring --- Changes in v2: - Collect Robh Ack for dt-bindings patch Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 5f7c6c4aad8f..a26bbcd00deb 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -922,6 +922,13 @@ properties: - const: rockchip,rk3568-bpi-r2pro - const: rockchip,rk3568 + - description: Sonoff iHost Smart Home Hub + items: + - const: itead,sonoff-ihost + - enum: + - rockchip,rv1126 + - rockchip,rv1109 + additionalProperties: true ...