From patchwork Wed Nov 22 14:14:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 746160 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UOYPKGnr" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 122C018E; Wed, 22 Nov 2023 06:14:48 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 166E2E000A; Wed, 22 Nov 2023 14:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1700662487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ABQkvnbU9jREL+xGEduT9Jz440AQVxL+9NX8sRWpyl0=; b=UOYPKGnr7sOyxEsQY3xpDVSRRGBZINCji7asEbWpRM803LzqHZWc45iqwkf6AbjKlWKvjI FxfR1WGV6IKEaFYUpUBU6T8z0wnOLgvJVXLXF7fJiAmxbrbMf3HAHiHnz9woxoT6o6IjoV fANbhFgt7lRAJUBPV/vlsDbH/bYeialQuZPUp/ACdQ/6k+Ka59dMxDiiycLCWiEpKVuu4t JyvCqDr5ZePlFwWBKyBOK5PPmN3IoneyuHOTyPx2iRQely6KIozj+MQTnc/IKbRimK1W18 cml8a1t27JJp4x3hW5XyimZLnmBevRq6GZIFwCJnCI/u+d9qhKPJj2dJATzdZA== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Laurent Pinchart , Michael Turquette , Stephen Boyd , Paul Kocialkowski Subject: [PATCH v7 2/7] ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect Date: Wed, 22 Nov 2023 15:14:20 +0100 Message-ID: <20231122141426.329694-3-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> References: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: paul.kocialkowski@bootlin.com The V3s uses the mbus interconnect to provide DRAM access for a number of blocks. The SoC can only map 2 GiB of DRAM, which is reflected in the dma-ranges property. Signed-off-by: Paul Kocialkowski Reviewed-by: Samuel Holland --- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index 3b9a282c2746..506e98f4f69d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -579,6 +579,21 @@ int_mii_phy: ethernet-phy@1 { }; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun8i-v3s-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0x80000000>; + #interconnect-cells = <1>; + }; + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; From patchwork Wed Nov 22 14:14:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 746159 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="eMuKTIP+" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C92E497; Wed, 22 Nov 2023 06:14:50 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id BC234E0007; Wed, 22 Nov 2023 14:14:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1700662489; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zkdHkQjq3zn+cr3h8O6hniqwb4wqvOUf1cWWpN7DY+s=; b=eMuKTIP+3smNdNoRBrZEeMbsJjG0CWGQ6wjhR+xyz4LO5SxAm7+b5yxQUdS4igDJG7Obr+ 2NAwGIeKs3kv/ZY0/2Pdt1q4pt1CLSd9LC7vT79bPx+cKN3wYO/r2k9UT+TyHxbl/FR+a+ 3mRk4Jq20XyzteKkuKtwW01wqj2PBbx/7R7z1Kl6dpEqto5LNLlePHRT4X72pQgSYPmfF+ hmGgnMMXWWDURMHrx+N6d4At2kFO4iZ8xZil4o0hVCvPYKMvrUQIl9Um8ks+yMMfoNhc7+ 2F+GtkLXKV2t7s+nQLScgQq5VFksionhGslwoB6qzTE+mTxipnS3pXxw8cAePA== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Laurent Pinchart , Michael Turquette , Stephen Boyd , Paul Kocialkowski Subject: [PATCH v7 4/7] ARM: dts: sun8i: v3s: Add support for the ISP Date: Wed, 22 Nov 2023 15:14:22 +0100 Message-ID: <20231122141426.329694-5-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> References: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: paul.kocialkowski@bootlin.com The V3s (and related platforms) come with an instance of the A31 ISP. Even though it is very close to the A31 ISP, it is not exactly register-compatible and a dedicated compatible only is used as a result. Just like most other blocks of the camera pipeline, the ISP uses the common CSI bus, module and ram clock as well as reset. A port connection to the ISP is added to CSI0 for convenience since CSI0 serves for MIPI CSI-2 interface support, which is likely to receive raw data that will need to be processed by the ISP to produce a final image. The interconnects property is used to inherit the proper DMA offset. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index d57612023aa4..1a1dcd36cba4 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -645,6 +645,14 @@ csi0_in_mipi_csi2: endpoint { remote-endpoint = <&mipi_csi2_out_csi0>; }; }; + + port@2 { + reg = <2>; + + csi0_out_isp: endpoint { + remote-endpoint = <&isp_in_csi0>; + }; + }; }; }; @@ -703,5 +711,32 @@ csi1: camera@1cb4000 { resets = <&ccu RST_BUS_CSI>; status = "disabled"; }; + + isp: isp@1cb8000 { + compatible = "allwinner,sun8i-v3s-isp"; + reg = <0x01cb8000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isp_in_csi0: endpoint { + remote-endpoint = <&csi0_out_isp>; + }; + }; + }; + }; }; }; From patchwork Wed Nov 22 14:14:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 746158 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZwSqH+8l" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D28F18E; Wed, 22 Nov 2023 06:14:54 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 0924DE0005; Wed, 22 Nov 2023 14:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1700662493; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RMUiNYYrSJTJpIrbqVmKd1nt/unZDdKv9MD9/KuRjYU=; b=ZwSqH+8lCJrY2dcdvuLfcyUKWscKeAFuIdhGlMmMEJhRsMlUdaxjRRhbQ34NPkIQ/qOE19 iXLRl9FZIKxlPwHGd/Ru7l9BfhiKQT0hwj5QrjHPBjOoUeENgW9/PpftveMyDsl7zVDOV6 B/raDGP1i8+aaBcNSYagiXiDRpvHkNvuaoWf+x5DZ4uIS+bNYORAh4nyO3sHuxLCDI6B11 QebxJvcY69UBGKLF1zARAUH9PT7S+hzFI7WVTWD8s3sLq84eZ228OyFTe9I+LBt7OYNknO s65gs4Lrh1xWQpS7OJgWXbEdKUJZ+RbM7aSbj/begvkf6/XOPg+sGv5TMmK2Ng== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Laurent Pinchart , Michael Turquette , Stephen Boyd , Paul Kocialkowski Subject: [PATCH v7 7/7] ARM: dts: sun8i-a83t: Add BananaPi M3 OV8865 camera overlay Date: Wed, 22 Nov 2023 15:14:25 +0100 Message-ID: <20231122141426.329694-8-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> References: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: paul.kocialkowski@bootlin.com Add an overlay supporting the OV8865 from the BananaPi Camera v3 peripheral board. The board has two sensors (OV5640 and OV8865) which cannot be supported in parallel as they share the same reset pin and the kernel currently has no support for this case. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/allwinner/Makefile | 1 + .../sun8i-a83t-bananapi-m3-camera-ov8865.dtso | 109 ++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index a0a9aa6595e4..980ac88634e3 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -278,6 +278,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-bananapi-m3-camera-ov5640.dtbo \ + sun8i-a83t-bananapi-m3-camera-ov8865.dtbo \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ sun8i-h2-plus-bananapi-m2-zero.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso new file mode 100644 index 000000000000..0656ee8d4bfe --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2022 Bootlin + * Author: Kévin L'hôpital + * Author: Paul Kocialkowski + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * These regulators actually have DLDO4 tied to their EN pin, which is + * described as input supply here for lack of a better representation. + * Their actual supply is PS, which is always-on. + */ + + ov8865_avdd: ov8865-avdd { + compatible = "regulator-fixed"; + regulator-name = "ov8865-avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_dldo4>; + }; + + ov8865_dovdd: ov8865-dovdd { + compatible = "regulator-fixed"; + regulator-name = "ov8865-dovdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_dldo4>; + }; + + ov8865_dvdd: ov8865-dvdd { + compatible = "regulator-fixed"; + regulator-name = "ov8865-dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_dldo4>; + }; +}; + +&ccu { + assigned-clocks = <&ccu CLK_CSI_MCLK>; + assigned-clock-parents = <&osc24M>; + assigned-clock-rates = <24000000>; +}; + +&csi { + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pe_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + ov8865: camera@36 { + compatible = "ovti,ov8865"; + reg = <0x36>; + + clocks = <&ccu CLK_CSI_MCLK>; + assigned-clocks = <&ccu CLK_CSI_MCLK>; + assigned-clock-parents = <&osc24M>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&ov8865_avdd>; + dovdd-supply = <&ov8865_dovdd>; + dvdd-supply = <&ov8865_dvdd>; + + powerdown-gpios = <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */ + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ + + port { + ov8865_out_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in_ov8865>; + link-frequencies = /bits/ 64 <360000000>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_csi2 { + status = "okay"; +}; + +&mipi_csi2_in { + mipi_csi2_in_ov8865: endpoint { + remote-endpoint = <&ov8865_out_mipi_csi2>; + data-lanes = <1 2 3 4>; + }; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&csi_mclk_pin>; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +};