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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c431500b00403b63e87f2sm176451wme.32.2023.11.22.10.30.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:30:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 01/11] qom: Introduce the TypeInfo::can_register() handler Date: Wed, 22 Nov 2023 19:30:37 +0100 Message-ID: <20231122183048.17150-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a helper to decide at runtime whether a type can be registered to the QOM framework or not. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 4 ++++ qom/object.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/include/qom/object.h b/include/qom/object.h index afccd24ca7..0d42fe17de 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -372,6 +372,8 @@ struct Object * struct TypeInfo: * @name: The name of the type. * @parent: The name of the parent type. + * @can_register: This optional function is called before a type is registered. + * If it exists and returns false, the type is not registered. * @instance_size: The size of the object (derivative of #Object). If * @instance_size is 0, then the size of the object will be the size of the * parent object. @@ -414,6 +416,8 @@ struct TypeInfo const char *name; const char *parent; + bool (*can_register)(void); + size_t instance_size; size_t instance_align; void (*instance_init)(Object *obj); diff --git a/qom/object.c b/qom/object.c index 95c0dc8285..f09b6b5a92 100644 --- a/qom/object.c +++ b/qom/object.c @@ -150,6 +150,9 @@ static TypeImpl *type_register_internal(const TypeInfo *info) TypeImpl *type_register(const TypeInfo *info) { assert(info->parent); + if (info->can_register && !info->can_register()) { + return NULL; + } return type_register_internal(info); } From patchwork Wed Nov 22 18:30:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746032 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475477wru; Wed, 22 Nov 2023 10:33:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IFzCnQUYoRFPdgSgzfY52VegrV8O7ZoeKzi5kNOcdoMiYyqVTlT5Z6EGZRc0v/n3FC7Rtzl X-Received: by 2002:a25:8388:0:b0:d8b:1407:f61d with SMTP id t8-20020a258388000000b00d8b1407f61dmr3002390ybk.26.1700677983162; Wed, 22 Nov 2023 10:33:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677983; cv=none; d=google.com; s=arc-20160816; b=x5WsCJl9wjyIGCUE+ZGyl94ujRNwFs88Kf2Qe28PIjDbq/h677Fkb531W3ChNN092W YEUCX+/SGxNLOFHpEj33PF77iJ/aDVkiRoLknLs5y0aqdtae2DPZigtCut7oSR+K+68O 0MZNqM/IGzClhf43hoJgs9/MLvotWv4lGiagw1it9+G/wsWnh08e/yL1ppT/izP4g0HL QXftdqMPPiLHuSoHehn5//gLYdeBvs8H0dj3H2IIAHGr0IjFLT7L0fNFx/dkBYrdOeF0 PExoFMIokrW/UQJtYcenFlhG7I2xKTfQpLNR95aTlxO6KMouRQ9xyt1Ymns8rGEpyDAE nsnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E7103XOFxT5bJSMqrbJRnaAZtCqt8Oh3G3I/DOAsQEM=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=CVYTkgJVb6qD4zPVqlbqQEjm2DPXAu3XaDkrF988dK5Do4MBE+35R6JM0R90ZMg819 hOxhpbj56kojgTdqy/9hsCVB0ajc2bHdFeVeQ+YavBa3FgIO131K1EfxJtqXKTq6AoCk 7cnckHCmue7g6iKW1CRfaB9YFLLoe5+6U5NUuEGCAP4RtaGD1DAlXZyDxYZK/Z4ligM6 z8PSvrYS3EXGIuLd93YXPmgm2BP2W/buQOULtIBsVugixwU3l4mrodaIR2NDwicot9Gq 2UiM8iRWarh4xSppPEzYwr9KIOyJgCYdtCruhACigLg9CNxOhzGRHQupHpd655y3iJt1 mm9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XudJ9G9i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id f3-20020a05600c43c300b003fc0505be19sm176312wmn.37.2023.11.22.10.31.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 02/11] target/arm: Add target_aarch64_available() helper Date: Wed, 22 Nov 2023 19:30:38 +0100 Message-ID: <20231122183048.17150-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to build HW models once, but don't want to register types when all prerequisites are satisfied. Add the target_aarch64_available() to know at runtime whether TARGET_AARCH64 is built-in. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-qom.h | 2 ++ target/arm/cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 02b914c876..bf6b3604ed 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,4 +33,6 @@ typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) +bool target_aarch64_available(void); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 25e9d2ae7b..1990c04089 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2548,3 +2548,12 @@ static void arm_cpu_register_types(void) } type_init(arm_cpu_register_types) + +bool target_aarch64_available(void) +{ +#ifdef TARGET_AARCH64 + return true; +#else + return false; +#endif +} From patchwork Wed Nov 22 18:30:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746029 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475411wru; Wed, 22 Nov 2023 10:32:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IGeC5kqN1ZsJ8g0L4Yd0xAEUqo4FAtu3HFVypi9viYMvNGLMx5N73B0SCPKnXm1CnTuX9z+ X-Received: by 2002:a05:6870:fbab:b0:1ea:3f79:defb with SMTP id kv43-20020a056870fbab00b001ea3f79defbmr3612979oab.52.1700677972788; Wed, 22 Nov 2023 10:32:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677972; cv=none; d=google.com; s=arc-20160816; b=Tj7oHyqwSKy3wlsyX9TkyoKLbEg1kZtdJo1Q2WUgsAt5UwDf1YNE4/4ovcdX3GCfOz sax6cGQNDCtQQD5DpxhcKENY/+RZMEt/ze19+5laOpgWADMWOYWKuSpbmZvBFYAbdXIe UOTh7PasiLBHU4OsGsrHv2H+UQR1Dvv/Z48cVyBs8BPXR6MACI5qfhHE9vmPrMsH/Tpo CHw3nfbBk4DCpCDaHbkvDmKmNDN/xrvrVpqsNxB7AOSrmEkY8u+ytlI0GcJAyTAdursD iAsahMt46bERj4caBlKO5mfISn9gyqLCFM/Hyb9zPqhZwVgA5D+weqlQN4q+yi7YXP/+ xdgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aGx5XygnULFFxHYgrgUAbmNY2b76PBI4xDcz2zCtY2c=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=OAgZtVyO/k+YWcE9+XhyTsH8RmC97GJAPEXPSMD9w4XFd2W8GwhJpaZWQAS7RFPhSu oTLY123MK8rap7QJojNbVuOHXc71DxXeGEp2R4rbkEGE4QuX2Qs/EQdeWMBFA0nVBhkW Al6k4LCIIaXl+z0R60YpTgpy30vVWkSviqUy6A5vhZp4fg0H00f01ssaOUd0gdq+Xqh1 ZZZJWCh9PeT9dCn05isKy4Y99nDRpEDQuZ4LOMLmhytXFzHZ8B/ljfb4ZUGc2iwWAlsE iqyqMPCS0Q67bZJ9tIxCQf/MFIzzqTfBMEw1CRUr6LsHR11SBCyPluRRO5ciIO985tgb VnHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QyMYn8Lc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id dh10-20020a0560000a8a00b0032d8eecf901sm61377wrb.3.2023.11.22.10.31.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 03/11] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Date: Wed, 22 Nov 2023 19:30:39 +0100 Message-ID: <20231122183048.17150-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Missed in commit 2d56be5a29 ("target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See it for more details. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index bf6b3604ed..be307037ff 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,6 +33,9 @@ typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) + bool target_aarch64_available(void); #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0282e0d28..d369275827 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2834,8 +2834,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU -#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU From patchwork Wed Nov 22 18:30:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746030 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475413wru; Wed, 22 Nov 2023 10:32:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEWlMWhTbn5XeJpJ8ws6Pm+v3ACoH3vY13BfP6O7s4nwZdd1FSE+JkPMPy7EtokVTXiIy46 X-Received: by 2002:a05:6870:1f14:b0:1d0:d9e2:985f with SMTP id pd20-20020a0568701f1400b001d0d9e2985fmr4289906oab.57.1700677973140; Wed, 22 Nov 2023 10:32:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677973; cv=none; d=google.com; s=arc-20160816; b=sBjlDMRfbvPRExjitVFRinJxoGHrEZRLiyb1ZbQ8UpbG2It8IBveuyyOs6yNPMcLP3 3vr1fqyKKgNvI6xY7VUbFyJn2zniiHejlz8nk94tiHM5wnXHybe9OJR75WRl5z6T2rhd EvrMGWTz1vNsHdavcLyUSbqNP+ybFU7j85N9u7Q3L8P47rfCn36RQDhKEC+qXqueITeU YQ1e8JaZGE/tBgZqpdW1lad2b+xDYGvluA+a07h3CnWhN0VBbPNIK9laQaLqdfi6Nekv vBsBsG2XlI+gCEp/BYuaBIv2hRt98ZVhL8CpfOJ1OVendR0bn/0Qm93QbwIxFVgdfHq9 tfhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iZrZRIxKP0fr1EzlYqN5VDWsI9Qt1x4ludh/rJlYbBI=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=fuSZMd1OsC0117tZcmGHEYkDDSxZ9ioGBFZr8zYscvhXDN0DjzUH+2ywIxD4lSZnGQ qBA7utJ+HKii3+JK4y9YPCSfv2kNx6Sw3i+H6i8oBgYELro2NSh91voHty/TSOft4PBr btveE+XfLi8Dglvng40eI6NodoRdAXbQ/7UUGCp7RFc97KP5qJalYiImTWTz8K35b86o 2R0HbQFMXFUylFh3qAUJgOm4eHtxGmsiwFdfLfZ0qQzQXwucd+RZKQyVetVMY7PUWu6s HQWWKsVSuUFew3p2hn7jgqZy3N/rxnF4yEyMTQzxTRkdC5JIySF2MsbrZEAUKwpmAS4c ZqDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u7bcKp1l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id d11-20020adfa40b000000b003232380ffd7sm36991wra.102.2023.11.22.10.31.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 04/11] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' Date: Wed, 22 Nov 2023 19:30:40 +0100 Message-ID: <20231122183048.17150-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ARM_CPU_IRQ/FIQ definitions are meant for the ARM CPU QOM model. Move them to "cpu-qom.h" so any QOM code can use them. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Or do these definitions belong to cpu-defs.h? --- target/arm/cpu-qom.h | 6 ++++++ target/arm/cpu.h | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index be307037ff..38030450f7 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,6 +36,12 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +/* Meanings of the ARMCPU object's four inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + bool target_aarch64_available(void); #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d369275827..124d829742 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -107,12 +107,6 @@ enum { #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's four inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 - /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts From patchwork Wed Nov 22 18:30:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746035 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475655wru; Wed, 22 Nov 2023 10:33:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbO6NfumZ1//fmyARgxS7iDEa3CGPb739Tmzg166s+O/twVgrTGGggiMHedruBF/4m+5E8 X-Received: by 2002:ac8:5bc2:0:b0:423:785a:ef5c with SMTP id b2-20020ac85bc2000000b00423785aef5cmr454494qtb.13.1700678005066; Wed, 22 Nov 2023 10:33:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700678005; cv=none; d=google.com; s=arc-20160816; b=O2qDtxhd7yB0m6UZcte7AbX4RyCzXbJeo6ZXyCKdWMHnANNlE106NeeIXDTFflAXRE P3+F0KojkvdmWL4xe45Vzbyhvlrf669jSqCuiXUQxvkWdOW5lbzCB+UlXEr7ei73mhIC WP5LjkBdKnmfJ0RK+dT8mhawmxODUYpyoPesc9szEt7JLGNKcaMDhNRJ1KnLisulfOsv kDhLgzWevym7Kgk1x04vuI0LtnEGIgifXc/sgtk8XbHWXuqHlmsmXH/ELlT6kj6hACqw lbB6C22XqmKA0aridH5KlsZ+0PvD11tXtDQEawoWx75IP7zMmU9x7u8AQAgxKfNPLZrZ jBgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=emiroLvN4ZFzV0iGKy2RcqyAnliELrYGvZjH5AAzbJU=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=BaGub7D324oUrLtj1wem5JAo9W4QUawdnhl3791MbtxELcoj9dLbjC6BOePQSp43qb 1nwymB4QUQSbZfwmwrKXm/plPoMUJTEi8Qb1RgjEDVtN9t13yf1jal/WyLHilOgNOeRU LaoiXfQAURUKY1UD3DTKY3dAplzipodcwLyJChptlNzWQzq7EBX4jPA1EpMoE3/m7q1y Jp9Y6bfOomh014PTsPfGBzFnk0XAT8900z2HkeJJYG4vGxqaUW+8RIVBGjhpNNtuuNRw UddmCQFExKl52lEUg2aokPXs0ab4PM/Xj82k9+8/k2eutMocKlVagDgV+EtJ4LnVFz2X caiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FVlhk34m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id t3-20020a5d6903000000b0032da49e18fasm66146wru.23.2023.11.22.10.31.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 05/11] target/arm: Move GTIMER definitions to 'cpu-defs.h' Date: Wed, 22 Nov 2023 19:30:41 +0100 Message-ID: <20231122183048.17150-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To allow GTIMER_* definitions to be used by non-ARM specific hardware models, move them to a new target agnostic "cpu-defs.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-defs.h | 19 +++++++++++++++++++ target/arm/cpu.h | 8 +------- hw/arm/bcm2836.c | 1 + 3 files changed, 21 insertions(+), 7 deletions(-) create mode 100644 target/arm/cpu-defs.h diff --git a/target/arm/cpu-defs.h b/target/arm/cpu-defs.h new file mode 100644 index 0000000000..1ad76aff14 --- /dev/null +++ b/target/arm/cpu-defs.h @@ -0,0 +1,19 @@ +/* + * ARM "target agnostic" CPU definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ARM_CPU_DEFS_H +#define ARM_CPU_DEFS_H + +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 124d829742..8107e4d446 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -24,6 +24,7 @@ #include "qemu/cpu-float.h" #include "hw/registerfields.h" #include "cpu-qom.h" +#include "target/arm/cpu-defs.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" @@ -154,13 +155,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 166dc896c0..6986b71cb4 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -15,6 +15,7 @@ #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +#include "target/arm/cpu-defs.h" struct BCM283XClass { /*< private >*/ From patchwork Wed Nov 22 18:30:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746031 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475445wru; Wed, 22 Nov 2023 10:32:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IHypdgcEIfqNJ+QODfqQw6AevtjQ/MRS+LbRWnADMJN3WTs8c3uGV+PZhM/UA7HL5ALNSL1 X-Received: by 2002:a05:622a:6a8e:b0:423:7f54:a755 with SMTP id ih14-20020a05622a6a8e00b004237f54a755mr1875002qtb.46.1700677978778; Wed, 22 Nov 2023 10:32:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677978; cv=none; d=google.com; s=arc-20160816; b=Ml7eVdiHMzn+UXVyfgc4dx++cERGZIMg+n/r/MDqNe38Q+K24jl/R0eKwv8Eh3uuZv 9HMf+zbzFKIC0TXQIAWvKGGnOyIZFOa1XF/rcTh4O9Go9z1/M2AHct5Q3IN4LI3qKNHR BAUhXuOYG148yXvx4BOyJgi2UVYSwhYq1v8mCjP1aR7yj5B3lkd6agqXRUWpsLf1yUqa Yn4JqltiH1b3aehJ7lIMZKBQ30Sfp+vhEsEJQtlBEcWuwiyAy37WvI6IIy0Z+2YtOcB5 jwyKiZugOfqZlMn/gZ5vAj/VT+6vjQPDZXRmpYwqViUP2KfDEJ/Bsg/5Rqu9v9RXGvjY lTfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wy7RMjyw0Q7UvKTe0+LJtz1uxwDhQNO7f4wPUgjAVa0=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=Q0O5+FeaqzJy8ehp1TLVHKlaiaPMA3cgUpdql+aSmxHC/uvruLTv47EghztRwwa/aN 6YSXFj9QTbTuRJzx5730Fo2GLc/q8cSPLueql9ZjlhJKfV7NzX/soCqTFestS5STgRPG 6HTfAS1/qhjMas4r/n+wo1wyYUQ8BpYNyfZpehY3TTKmoA1aX7XnEHr3+tbvl79CjqOf LZ5I7IO/nAnN4OqQJkNXQFh9o3L4LrjHf/o44Tsv2Kt/dJ71BCuG2YUPpV24nKU3iIcd 6+VDpLtgFG5R2efoZM8+WJ5Uv1dCROH3sJJmjWq+IuJKNgZSXFz795dKRpWYdnPWKEoH fRjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X/N2pG9l"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id n17-20020a5d6b91000000b003140f47224csm67155wrx.15.2023.11.22.10.31.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 06/11] hw/arm/bcm2836: Simplify use of 'reset-cbar' property Date: Wed, 22 Nov 2023 19:30:42 +0100 Message-ID: <20231122183048.17150-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org bcm2836_realize() is called by - bcm2836_class_init() which sets: bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7") - bcm2837_class_init() which sets: bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53") Both Cortex-A7 / A53 have the ARM_FEATURE_CBAR set. If it isn't, then this is a programming error: use &error_abort. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/bcm2836.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 6986b71cb4..055c909e95 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -132,10 +132,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; /* set periphbase/CBAR value for CPU-local registers */ - if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", - bc->peri_base, errp)) { - return; - } + object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", + bc->peri_base, &error_abort); /* start powered off if not enabled */ if (!object_property_set_bool(OBJECT(&s->cpu[n].core), From patchwork Wed Nov 22 18:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746033 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475545wru; Wed, 22 Nov 2023 10:33:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVSFV/PHbg28RXUBPxopsVOB2USEQbZBPNjyugl3eBAXgX1wTOyq4iQ7t7cLLI62l7Ow2p X-Received: by 2002:ad4:5968:0:b0:679:f49b:bb1a with SMTP id eq8-20020ad45968000000b00679f49bbb1amr3180756qvb.6.1700677992642; Wed, 22 Nov 2023 10:33:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677992; cv=none; d=google.com; s=arc-20160816; b=NEjQzWVA+JTocHGCdIcixdQWdQfCX+jZgufu6hiJSFtyEqPcaJlmE1B9W8Ml6fRvIL nRC3wTR62CV3V/ZBulzCJX2fEpZtS+mLmqRdR/jskAI+UQgR6R9OVok6348TtnasnMUB gnlTVEvINZ1H0uY97GsOECrAycdun5xIi0Abfw90L07XQST/ljWh5UvXh8ST7O1ZYm8F bmVd2iFZNqx1Bffu86SOhCONdw0wivvvSPEiMY3N4arKuo1yUqk4zz+OJExt7JJ42ucH Q2PyGdrRzcpprQLQG3eLQdNkXZ5Dt0IsSXgZqt688S51AC2bTjuFG1NaJWXnjep5ZGWo 2/+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Lb2/44LPlczFh1Mivxhuq3Cei7H/G9D4OqWoSqq23Aw=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=vPberZqOTunyEIu5/7VWrax2s09NG1sBANqY8BeJPTEZmvL49Rab30rsINFv8yPTTR adQyCjv+5iN48k/J6XiqDSsPDRAgv4cwiLUrqDfwHCLlHejPR6fxMgkcun3vbiGnxl11 dge70PB4CzVpth69ySVhOeqX5r6rXYUpyzLGu1L8JbsinQE7Vec7jmusXsLFMQaV0pMv aPKyHniR57HEgjrdUXRYMLlstxY8M3EcwZSRBvQ1MbcCL0lkjzEYyIAaqDjLRP7fTKEz KbIbn7GXq3ZWvu6P4eHJWTxG36o+/ws2vB7O5V/0Jei+g+upZoktNCb0yugKhfdLsIN1 7+GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q5iEMtP4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id q19-20020a05600c46d300b004064e3b94afsm280976wmo.4.2023.11.22.10.31.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 07/11] hw/arm/bcm2836: Simplify access to 'start-powered-off' property Date: Wed, 22 Nov 2023 19:30:43 +0100 Message-ID: <20231122183048.17150-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All ARM CPUs have the 'start-powered-off' property since commit 5de164304a ("arm: Allow secondary KVM CPUs to be booted via PSCI"). Note: since commit c1b701587e ("target/arm: Move start-powered-off property to generic CPUState"), all CPUs for all targets have it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/bcm2836.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 055c909e95..198f9b5730 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -136,12 +136,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) bc->peri_base, &error_abort); /* start powered off if not enabled */ - if (!object_property_set_bool(OBJECT(&s->cpu[n].core), - "start-powered-off", - n >= s->enabled_cpus, - errp)) { - return; - } + object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", + n >= s->enabled_cpus, &error_abort); if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { return; From patchwork Wed Nov 22 18:30:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746034 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475548wru; Wed, 22 Nov 2023 10:33:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IHlgJ9VZGQ+IQu5uwlpsxKsQETPs3lvDNoox8Er+MNVfxMGjXuPktKRwL8o1Ij/KO8wsHHB X-Received: by 2002:a05:620a:8387:b0:77b:9a8c:b0ae with SMTP id pb7-20020a05620a838700b0077b9a8cb0aemr3467236qkn.40.1700677993154; Wed, 22 Nov 2023 10:33:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677993; cv=none; d=google.com; s=arc-20160816; b=znJBdH6mz4t6xYSofgFsbm0RiMJHMrjSsGsxj0gI5cmOKmJMrQCRlXMeal1rVewuYK zPe8jFFAstJ+b3IOIwPZcC8XroMJWinIcX9VvVg8Cb649ODVmNVHzVAFblcBYeBgocYF II/35CCPxSac/2lY9KqDDXRy8lb3kiHfwSU+PQ14auUyi4r1vxlH/ocjES66TxeE/Phv CEoxESkK5pqIQ1MrH35JVAsQlo9dVNKTGmnRLLddrKOW8oKMPJCZELfH8QF6BAsfBeGo AZh6+PUHdrMK6lixLrxGCTh7OjiqjtCHM3cmlt7yvugWfvRjRTs84rUiRdd4ou1Rt3f9 No6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=auZXV6u0sdeAtdGoHPpNxl3A34os5kR+ZbHub0QBvt4=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=ajHqDRT3ZComzau2lT3JfD/UqOWL/L0PP4RL3eC11OeSb4tg9Fn/udZLLBaCMmx9jS 9ilnxs4ABeJcMihyK/COIR89p4gxW32Hy3nu/T2Jq8wiJ6b+j5N5R2mRjPr51yHtbtAJ 5EmB1oTYFi5FztBn30CO3fqkncSLOkihJofpdc6QwlaburUWhWD/7kuWb4BtPy7RhiRm 6tQCJlyf8ZK2p3dgaGNUUfStMsF4XaylJhVOWchSPqKdd1KCQoCU4pgQiWHAOuaMaF71 n/IixkkUrdioMdPhR/QIQjdXxZ40E00cwzw2i9SaLoftqM9AwERVeLZH25DcVesDqNyu kbKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PQQL0H6R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id u14-20020a05600c138e00b004063ea92492sm187101wmf.22.2023.11.22.10.31.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH-for-9.0 08/11] hw/arm/bcm2836: Use ARM_CPU 'mp-affinity' property Date: Wed, 22 Nov 2023 19:30:44 +0100 Message-ID: <20231122183048.17150-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 'mp-affinity' property is present since commit 15a21fe028 ("target-arm: Add mp-affinity property for ARM CPU class"). Use it and remove a /* TODO */ comment. Since all ARM CPUs have this property, use &error_abort, because this call can not fail. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/bcm2836.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 198f9b5730..8031a74600 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -128,8 +128,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); for (n = 0; n < BCM283X_NCPUS; n++) { - /* TODO: this should be converted to a property of ARM_CPU */ - s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; + object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", + (bc->clusterid << 8) | n, &error_abort); /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", From patchwork Wed Nov 22 18:30:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746036 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475707wru; Wed, 22 Nov 2023 10:33:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IEUDlVJNwKpaSSUYaIoeqFaWUymy9eAaUKDrJLzNCV4z+/xofjvSwJhnsmDTzaP1U6YDZRb X-Received: by 2002:a05:620a:4504:b0:77a:510f:3b5d with SMTP id t4-20020a05620a450400b0077a510f3b5dmr3608322qkp.28.1700678012542; Wed, 22 Nov 2023 10:33:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700678012; cv=none; d=google.com; s=arc-20160816; b=bPnFlXRcOqWNQ/1lAJyPFrP8NmB5xaif1vyQNNVfAcK/BZN37vWnDRal1UARngK/5l FndtiGn4ItxjUknd580ZK9h6/zhxVHQb3Fv6ymyHw2UjgA4a/+/+MNznXNQo1cXewSge ai07SxFMbieakbSrlVwh5mtaSNZ2zJ9O6mm6qpoYxnbbIwD55kth7XhuAsXJm1AQcpCp VcZSQrRAPEPs9M0bJK+ESYL2m1KYN6sVjOR7Y/4gXHzAgVXmjk6WE2krPJiEVdT3/yAs IXjZCzGyGavz3VzSKfMlHb5BNG2wdulu079ljbMxOi/lAOGAHX1PPmDDtxEirYqHD/R9 RRtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=juSImIqOFX4cBg5Zc+Do2T+lJUxoOW0iOapk4mN+Z7o=; fh=aTzmneatFEDiKMS1saCdxZb39+p//OutFupiUjvLGTw=; b=TnChS3p+Oo1rY86lveJlQpYTRtBXts0DodxCVjmBPl0rzc1wM4d2tXLvFNr3+9mr8w qCM3EFPZofh34bdEoLU1Ck5u4YOpGzy1lFBtj36R5E0QBz4bsOEPLgsgaN9BbdJCMK7v +vAvBOnpGeGtVDywQJ1gPQQDwSCTFOY13/pYrVrtS3AX5T2jXWF6jlJDlV6G0zECgsZd cwxNlfguJJagz6Abri3sltv3JuU196sPugk5jtVju1UEAnvpRJzkudgm08v8Ye3/2DON 7dykResfzFE4Hyd7/SbHIJDQJlpphQx0cwWe+neJL7DzcQ4AIEgAMn1mFteL52pMivCZ i5/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HYm4Qm6T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id b5-20020a05600c4e0500b003feae747ff2sm261799wmq.35.2023.11.22.10.31.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 09/11] hw/arm/bcm2836: Allocate ARM CPU state with object_new() Date: Wed, 22 Nov 2023 19:30:45 +0100 Message-ID: <20231122183048.17150-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ARMCPU type is forward declared as a pointer to all hw/ files. Its declaration is restricted to target/arm/ files. By using a pointer in BCM283XState instead of embedding the whole CPU state, we don't need to include "cpu.h" which is target-specific. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/arm/bcm2836.h | 4 ++-- hw/arm/bcm2836.c | 19 ++++++++++--------- hw/arm/raspi.c | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 6f90cabfa3..784bab0aad 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -14,7 +14,7 @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #include "qom/object.h" #define TYPE_BCM283X "bcm283x" @@ -38,7 +38,7 @@ struct BCM283XState { uint32_t enabled_cpus; struct { - ARMCPU core; + ARMCPU *core; } cpu[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 8031a74600..4f5acee77e 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -39,8 +39,9 @@ static void bcm2836_init(Object *obj) int n; for (n = 0; n < bc->core_count; n++) { - object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, - bc->cpu_type); + s->cpu[n].core = ARM_CPU(object_new(bc->cpu_type)); + object_property_add_child(obj, "cpu[*]", OBJECT(s->cpu[n].core)); + qdev_realize_and_unref(DEVICE(s->cpu[n].core), NULL, &error_abort); } if (bc->core_count > 1) { qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); @@ -139,24 +140,24 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", n >= s->enabled_cpus, &error_abort); - if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu[n].core), NULL, errp)) { return; } /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu[n].core), ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu[n].core), ARM_CPU_FIQ)); /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); } } diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index cc4c4ec9bf..01c391b90a 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -252,7 +252,7 @@ static void setup_boot(MachineState *machine, RaspiProcessorId processor_id, s->binfo.firmware_loaded = true; } - arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); + arm_load_kernel(s->soc.cpu[0].core, machine, &s->binfo); } static void raspi_machine_init(MachineState *machine) From patchwork Wed Nov 22 18:30:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 746028 Delivered-To: patch@linaro.org Received: by 2002:a5d:6706:0:b0:32d:baff:b0ca with SMTP id o6csp475385wru; Wed, 22 Nov 2023 10:32:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IEGu0TBVkMUMKWRbdQ2NETqcYWabb0/PdrgluN8dWOeBNh8PWyWUXv8OZy1g/b83U4Wgfdc X-Received: by 2002:a05:622a:120e:b0:421:c3a9:1e52 with SMTP id y14-20020a05622a120e00b00421c3a91e52mr3519811qtx.31.1700677969892; Wed, 22 Nov 2023 10:32:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700677969; cv=none; d=google.com; s=arc-20160816; b=Q664dIraBdJEKvdHHFsVsUTNL4x5v9zSP5Mkf+1zEBePrLMkkuwxKxChd+9kQFc0XJ EMoO+gl+TWLHMAsV2htFjgQNy2z8YMGIQyUzRBP+nz8dcL2hlJfYjZb0h2gaH8MyOn5F kooQPBfNTIsMvrBUBLuKnqlihNMSbfw+iwXbQQRudZq/YWx/sgJpZyhbjHpOi3iEUVn3 Lz9GpSDFFRR5Cs4xJFxyOPIUtIhhY1s6E8MlaH/glL5yZLuwiVbj4hfXWgPUZe1urQft 6na8djKuzP4JZ4wrH8Y64PskkI+yZUUbBzwHowmt3axn/S7yxlcOO8Uwcu8rsW8G7IXA bzZw== ARC-Message-Signature: i=1; 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id hg15-20020a05600c538f00b0040849ce7116sm242754wmb.43.2023.11.22.10.31.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 10/11] hw/arm/raspi: Build bcm2836.o and raspi.o objects once Date: Wed, 22 Nov 2023 19:30:46 +0100 Message-ID: <20231122183048.17150-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the target_aarch64_available() method to restrict Aarch64 specific models. They will only be added at runtime if TARGET_AARCH64 is built in. The Raspberry Pi models can now be built once for all targets. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 5 +---- hw/arm/raspi.c | 6 ++---- hw/arm/meson.build | 6 ++++-- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 4f5acee77e..ecf434c8ce 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -194,7 +194,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) dc->realize = bcm2836_realize; }; -#ifdef TARGET_AARCH64 static void bcm2837_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -207,7 +206,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) bc->clusterid = 0x0; dc->realize = bcm2836_realize; }; -#endif static const TypeInfo bcm283x_types[] = { { @@ -218,12 +216,11 @@ static const TypeInfo bcm283x_types[] = { .name = TYPE_BCM2836, .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, -#ifdef TARGET_AARCH64 }, { .name = TYPE_BCM2837, .parent = TYPE_BCM283X, .class_init = bcm2837_class_init, -#endif + .can_register = target_aarch64_available, }, { .name = TYPE_BCM283X, .parent = TYPE_DEVICE, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 01c391b90a..979937b9ac 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -349,7 +349,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data) raspi_machine_class_common_init(mc, rmc->board_rev); }; -#ifdef TARGET_AARCH64 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -367,7 +366,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = 0xa02082; raspi_machine_class_common_init(mc, rmc->board_rev); }; -#endif /* TARGET_AARCH64 */ static const TypeInfo raspi_machine_types[] = { { @@ -382,16 +380,16 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3ap_machine_class_init, + .can_register = target_aarch64_available, }, { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, -#endif + .can_register = target_aarch64_available, }, { .name = TYPE_RASPI_MACHINE, .parent = TYPE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 68245d3ad1..15d60685d0 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -38,7 +38,6 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) @@ -68,7 +67,10 @@ arm_ss.add(when: 'CONFIG_XEN', if_true: files('xen_arm.c')) system_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) -system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +system_ss.add(when: 'CONFIG_RASPI', if_true: files( + 'bcm2835_peripherals.c', + 'bcm2836.c', + 'raspi.c')) system_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) hw_arch += {'arm': arm_ss} From patchwork Wed Nov 22 18:30:47 2023 Content-Type: text/plain; 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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id d11-20020adfa40b000000b003232380ffd7sm38237wra.102.2023.11.22.10.31.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 11/11] hw/intc/meson: Simplify how arm_gicv3_kvm.o objects are built Date: Wed, 22 Nov 2023 19:30:47 +0100 Message-ID: <20231122183048.17150-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the target_aarch64_available() to build the ARM_GIC_KVM types regardless the ARM/AARCH64 targets are selected, but restrict its registration to TARGET_AARCH64 presence at runtime. This will help to have a single binary running both ARM/Aarch64. Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/arm_gicv3_its_kvm.c | 1 + hw/intc/arm_gicv3_kvm.c | 1 + hw/intc/meson.build | 6 ++++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index f7df602cff..b3063c4cd7 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -261,6 +261,7 @@ static const TypeInfo kvm_arm_its_info = { .instance_size = sizeof(GICv3ITSState), .class_init = kvm_arm_its_class_init, .class_size = sizeof(KVMARMITSClass), + .can_register = target_aarch64_available, }; static void kvm_arm_its_register_types(void) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 77eb37e131..33321dee5d 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -909,6 +909,7 @@ static const TypeInfo kvm_arm_gicv3_info = { .instance_size = sizeof(GICv3State), .class_init = kvm_arm_gicv3_class_init, .class_size = sizeof(KVMARMGICv3Class), + .can_register = target_aarch64_available, }; static void kvm_arm_gicv3_register_types(void) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index ed355941d1..d45eb76f36 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -40,8 +40,10 @@ endif specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) -specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files( + 'arm_gic_kvm.c', + 'arm_gicv3_kvm.c', + 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))