From patchwork Mon Nov 20 13:50:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 745436 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="G9XHnbFt" Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BCEA116; Mon, 20 Nov 2023 05:51:16 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4084de32db5so19083985e9.0; Mon, 20 Nov 2023 05:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488275; x=1701093075; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mDe+pQVEhH3Sr9b4984YEcBYZXzy8ixz3G1rWEEdZm8=; b=G9XHnbFtyXO/Q9ohweCu+fSUhIFx9cm7Ka51CQ21tkCLQwZl//z0nhWiaYaQmPwkBm TpjQJB/fSOO+shR7YHd7qyWdgcLfRc3PDUYQtjW8T2u9CapDnKje552Xc/xfBP82jmCP a4oOLWlfpTDCGTj91bhakUjy8DO22Spc8arm9j5xdfPThEmxZRCtAJzklGJvOS/hbbXg 6B+v/MyKLz16RBcpw0HlK32w9MddlGDvzsIyCtlyKzoy8bZlkkNI+idefexwcLBhunjN UCf/i8Upbd4S7hrV8pgS/A8veQt3MCxm+0mjdOmdF03Jzz4GRUIMLWVIHd9ua4DP+Sdz SZUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488275; x=1701093075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mDe+pQVEhH3Sr9b4984YEcBYZXzy8ixz3G1rWEEdZm8=; b=BOAx2JpRIXlZJe6Siujm0q9rA5+cK8fcb0oebvrSsNgAHQI6AMeqxaE3vCJsrPPkXu tGBcLvmxGv3wlvdt45PcUA3W2wZHMClXyK5qK3KQHKuIEH+E6iUGAZusiUuI1rf37OBi W/7uTRIqSRjsDVHBK8gQ8k39RVnrmlxW3jpC4rI4ppIyB7Bd2gzW7aV9YHoUxDM12Oil CzemwA3a1E1dZD/XCQ1JYkPPFaK3769GLvNcOLoIQvCDZxOppphmLtf6lrfksVxGFd5c Z5jc5GCGaMa5Oi7ckEOnhnDWB51YOhjbGzKewa9S3nl2DSAgu/C3Geqdak+Zwy35X8MK YD3Q== X-Gm-Message-State: AOJu0YxREjsbdmwv4FWLZ+oxwIiKgmd9m79sYhKKYdlRY3F/zgRZuRTJ V5DQW/HR7zr03mpGtvMW7pE= X-Google-Smtp-Source: AGHT+IHVHnzgf8EEZJbwbHrD1fJrQtGhYDQUh/AnVfNHdAOlAXGB/wAsBqejt0p1a7rxHshO7e2S9w== X-Received: by 2002:a05:600c:5248:b0:408:3ab3:a029 with SMTP id fc8-20020a05600c524800b004083ab3a029mr6210181wmb.38.1700488274368; Mon, 20 Nov 2023 05:51:14 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:14 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 02/14] dt-bindings: net: move PHY modes to common PHY mode types definition Date: Mon, 20 Nov 2023 14:50:29 +0100 Message-Id: <20231120135041.15259-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move PHY modes from ethernet-controller schema to dedicated common PHY mode types definition. This is needed to have a centralized place to define PHY interface mode and permit usage and reference of these modes in other schemas. Signed-off-by: Christian Marangi --- .../bindings/net/ethernet-controller.yaml | 47 +------ .../bindings/net/ethernet-phy-mode-types.yaml | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+), 46 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 9f6a5ccbcefe..40c1daff2a48 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -55,55 +55,10 @@ properties: const: mac-address phy-connection-type: + $ref: /schemas/net/ethernet-phy-mode-types.yaml#definitions/phy-connection-type description: Specifies interface type between the Ethernet device and a physical layer (PHY) device. - enum: - # There is not a standard bus between the MAC and the PHY, - # something proprietary is being used to embed the PHY in the - # MAC. - - internal - - mii - - gmii - - sgmii - - psgmii - - qsgmii - - qusgmii - - tbi - - rev-mii - - rmii - - rev-rmii - - moca - - # RX and TX delays are added by the MAC when required - - rgmii - - # RGMII with internal RX and TX delays provided by the PHY, - # the MAC should not add the RX or TX delays in this case - - rgmii-id - - # RGMII with internal RX delay provided by the PHY, the MAC - # should not add an RX delay in this case - - rgmii-rxid - - # RGMII with internal TX delay provided by the PHY, the MAC - # should not add an TX delay in this case - - rgmii-txid - - rtbi - - smii - - xgmii - - trgmii - - 1000base-x - - 2500base-x - - 5gbase-r - - rxaui - - xaui - - # 10GBASE-KR, XFI, SFI - - 10gbase-kr - - usxgmii - - 10gbase-r - - 25gbase-r phy-mode: $ref: "#/properties/phy-connection-type" diff --git a/Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml b/Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml new file mode 100644 index 000000000000..6d15743b4ffa --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-mode-types.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Common Mode Types + +maintainers: + - David S. Miller + +definitions: + phy-connection-type: + # const: "internal" + allOf: + - $ref: /schemas/types.yaml#/definitions/string + - oneOf: + # There is not a standard bus between the MAC and the PHY, + # something proprietary is being used to embed the PHY in the + # MAC. + - items: + - type: string + const: internal + - items: + - type: string + const: mii + - items: + - type: string + const: gmii + - items: + - type: string + const: sgmii + - items: + - type: string + const: psgmii + - items: + - type: string + const: qsgmii + - items: + - type: string + const: qusgmii + - items: + - type: string + const: tbi + - items: + - type: string + const: rev-mii + - items: + - type: string + const: rmii + - items: + - type: string + const: rev-rmii + - items: + - type: string + const: moca + + # RX and TX delays are added by the MAC when required + - items: + - type: string + const: rgmii + + # RGMII with internal RX and TX delays provided by the PHY, + # the MAC should not add the RX or TX delays in this case + - items: + - type: string + const: rgmii-id + + # RGMII with internal RX delay provided by the PHY, the MAC + # should not add an RX delay in this case + - items: + - type: string + const: rgmii-rxid + + # RGMII with internal TX delay provided by the PHY, the MAC + # should not add an TX delay in this case + - items: + - type: string + const: rgmii-txid + + - items: + - type: string + const: rtbi + + - items: + - type: string + const: smii + + - items: + - type: string + const: xgmii + + - items: + - type: string + const: trgmii + + - items: + - type: string + const: 1000base-x + + - items: + - type: string + const: 2500base-x + + - items: + - type: string + const: 5gbase-r + + - items: + - type: string + const: rxaui + + - items: + - type: string + const: xaui + + # 10GBASE-KR, XFI, SFI + - items: + - type: string + const: 10gbase-kr + + - items: + - type: string + const: usxgmii + + - items: + - type: string + const: 10gbase-r + + - items: + - type: string + const: 25gbase-r From patchwork Mon Nov 20 13:50:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 745435 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dIAJDECF" Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D05E126; Mon, 20 Nov 2023 05:51:18 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2c5b7764016so53079351fa.1; Mon, 20 Nov 2023 05:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488276; x=1701093076; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mSkXFy8s0m4FAo3hSta1RKyG8KAPqujjDp76lrQjrQM=; b=dIAJDECFtovM/SqF68vyMyKsts4M+lf79QkH/pCP22SLdmmmGHLLZ1eJ7qC2dEAzI/ kjgf6qiq8UVTe3qjqohF1ukPaB5fKv19SJcupSZxU8zvAtWAFWExY4M48cQdsG7MJ/Qe zlNN6WHPjbmR5Ya1X6mGNKgnswouIoA7SRx7o+gCPtuP+E0S4OMHewkK+xYnJER0gj0i ny8/IxRggIVSBLnE/gcD0MJ7QrtEdw++k0+U2buDeP8N7RpROXej3aslqlJcDWS3U1N6 cldVDOvRj1L7WD6KNLRT/SrEb4uyx5Jb2tOb9BFXGtLtzRH5pEJTB0ihOTBFNhFIgoCe WK8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488276; x=1701093076; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mSkXFy8s0m4FAo3hSta1RKyG8KAPqujjDp76lrQjrQM=; b=eIeqSH555xEJ5PiHh+TI0F8nGGQ9n1zABnFgDFb+r5kTLB5Xj4jKzqJzipuL8xCgbP OYRi/MHDZ5jFu2uIVLBgGs+HpT1WCeFP6r5FBxf0SEfNitnUFV0O2ndwigMCfGvqPSRf 8m4wxtNQyce6Rniq/AxTNLhYoU3BN6kxUA+jbknzReXvBjDzUmbyQC3AZMiEiKK3WvEC 1pvubN/t+ZVkYlpSyHwZz7uZG06sh9kyPE/rEkOqtZt6OlDoNM3tQKUTCRT4j9+4kghB /uu2+ihTKcCOWdtbJ9UrLghQWRhQp0yCLFJiwRVQPjuWnWvMNWMxgCxf851p9qUot/4Z sNlw== X-Gm-Message-State: AOJu0YzVOIppXrVzxjXmaqQsV/twC7bzZ9EHXQoZR3aavxPsVSVOSO4M YAZIj882jsE20wyqSEMGfV0= X-Google-Smtp-Source: AGHT+IGRWPskxjGA2rJREXkXtdcG94gsGR4fcmJx18lPkb4K8zHD6Ut0hUV6FgYsk/XQHGBG6tApZg== X-Received: by 2002:a2e:9192:0:b0:2c5:2eaa:5398 with SMTP id f18-20020a2e9192000000b002c52eaa5398mr4967418ljg.25.1700488276123; Mon, 20 Nov 2023 05:51:16 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:15 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 03/14] dt-bindings: net: document ethernet PHY package nodes Date: Mon, 20 Nov 2023 14:50:30 +0100 Message-Id: <20231120135041.15259-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document ethernet PHY package nodes used to describe PHY shipped in bundle of 4-5 PHY. These particular PHY require specific PHY in the package for global onfiguration of the PHY package. Example are PHY package that have some regs only in one PHY of the package and will affect every other PHY in the package, for example related to PHY interface mode calibration or global PHY mode selection. The PHY package node should use the global-phys property and the global-phy-names to define PHY in the package required by the PHY driver for global configuration. It's also possible to specify the property phy-mode to specify that the PHY package sets a global PHY interface mode and every PHY of the package requires to have the same PHY interface mode. Signed-off-by: Christian Marangi --- .../bindings/net/ethernet-phy-package.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy-package.yaml diff --git a/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml new file mode 100644 index 000000000000..2aa109e155d9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Package Common Properties + +maintainers: + - Christian Marangi ; + #size-cells = <0>; + + ethernet-phy-package { + compatible = "ethernet-phy-package"; + #address-cells = <1>; + #size-cells = <0>; + + global-phys = <&phy4>; + global-phy-names = "base"; + + ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + }; From patchwork Mon Nov 20 13:50:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 745434 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lR9zlysf" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77F2CD4C; Mon, 20 Nov 2023 05:51:21 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40806e4106dso10789515e9.1; Mon, 20 Nov 2023 05:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488280; x=1701093080; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TooJwdKX/NbwarJe/arvXU+/yWQ/ijJnXp3t5io/O14=; b=lR9zlysfLiOA/JebJWYcU0QaVOVjrPpSRo6Qf8eYzGzQ3QV1H2l8+KKsTCzo5mvkP4 +mDS7PF5tBX0ywO+zPxZLAedhZ5eobXFISp9tCLsqLg9nWBmA1AnkByU3XxdhXsW9orj b39TqSZOVh1ZVR/t1ZkEv0m9N5WGBRPUlvHGNzNm26RxLc3E+nmiA6StHBDh9TI+MA0d WSG+go6FLtN1UADyF7fdif3jD+gmrZwiyBrHT36WHHFwWR51SoKbrIkL7M6jqTnba6B9 9n/t2RtBVLtLOHYwPObFwAk/6NREnRqYrwplxutMb/N4M/LiOiUWVSU8VAhZZCNpT2Lg mWcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488280; x=1701093080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TooJwdKX/NbwarJe/arvXU+/yWQ/ijJnXp3t5io/O14=; b=AK8IF78/6+OHrIod9k0D65JltuecX99PDWGdlHsE7MJb+21X+y9PwnG6zr3/zF9KW1 t4X6Kk/YQus02r1AIi6TAjAnchdEc8OMsMdbU+ORSi8UnOlullotfWRt0dm7BFlfCrKd IUjQHTpuE434JkDF/UNRfo73w4tdP9MKUhNkcL9mOjxq/Wdo5vtRqauC/HUwsWsmcW09 0Dv8efPtZnrCaoZy8jd/g9Oj4vZIXgYpVDiUKOZVdGnrodY5uF6OPzIue64xna1ICNBU HDKhPjhO4zBCRSlHLwsz9ylt2GBRKfXGcd+n4LfcwdUrTApOdqn5g53pBkgsUtmRJq2/ 8iiw== X-Gm-Message-State: AOJu0YxuJYVWtinj20vzWfz9Uly+K1VlgY8Il5zZ/B4ajPj3mtNKaqdC QtlDuZPUK6FsYuMC5i16pZo= X-Google-Smtp-Source: AGHT+IGbR/jLe62wvESEe8CFVjFJBQOHE36zG4blKfXpV72kg2YCPBmafC4MW5hggXNjObGvZiPqSQ== X-Received: by 2002:a05:600c:1c22:b0:40a:4c6c:c87a with SMTP id j34-20020a05600c1c2200b0040a4c6cc87amr6787606wms.3.1700488279771; Mon, 20 Nov 2023 05:51:19 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:19 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 05/14] net: phy: add support for named global PHY in DT PHY package Date: Mon, 20 Nov 2023 14:50:32 +0100 Message-Id: <20231120135041.15259-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for named global PHY in DT PHY package definition. A phy-package node can provide the property "global-phy-names" to provide named global PHY to correctly reference the phandle defined in the global-phys list. Each PHY driver has to define the .phy_package_global_phy_names list to verify correct order of named PHY phandle defined in DT with the expected order in the PHY driver. If the list is not defined or "global-phy-names" is not defined in DT, global phy addresses are insered in order defined in the "global-phys" property. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 13 +++++++++++++ include/linux/phy.h | 6 +++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 9ff76d84dca0..452fd69e8924 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3198,6 +3198,7 @@ static int of_phy_package(struct phy_device *phydev) struct device_node *node = phydev->mdio.dev.of_node; struct of_phandle_args phy_phandle; struct device_node *package_node; + const char *global_phy_name; int i, global_phys_num, ret; int *global_phy_addrs; @@ -3236,6 +3237,18 @@ static int of_phy_package(struct phy_device *phydev) if (ret) goto exit; + ret = of_property_read_string_index(package_node, "global-phy-names", + i, &global_phy_name); + if (!ret && phydev->drv->phy_package_global_phy_names) { + const char *name; + + name = phydev->drv->phy_package_global_phy_names[i]; + if (strcmp(global_phy_name, name)) { + ret = -EINVAL; + goto exit; + } + } + global_phy_addrs[i] = addr; } diff --git a/include/linux/phy.h b/include/linux/phy.h index 5bf90c49e5bd..5e595a0a43b6 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -892,6 +892,10 @@ struct phy_led { * @driver_data: Static driver data * @phy_package_global_phy_num: Num of the required global phy * for PHY package global configuration. + * @phy_package_global_phy_names: List of global PHY names used + * for PHY package global init. If defined, list is compared + * with DT values to match correct PHY phandle order. List + * last element MUST BE an empty string. * * All functions are optional. If config_aneg or read_status * are not implemented, the phy core uses the genphy versions. @@ -910,6 +914,7 @@ struct phy_driver { u32 flags; const void *driver_data; unsigned int phy_package_global_phy_num; + const char * const *phy_package_global_phy_names; /** * @soft_reset: Called to issue a PHY software reset @@ -1154,7 +1159,6 @@ struct phy_driver { */ int (*led_hw_control_get)(struct phy_device *dev, u8 index, unsigned long *rules); - }; #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ struct phy_driver, mdiodrv) From patchwork Mon Nov 20 13:50:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 745433 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J1+btUUb" Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23D24D65; Mon, 20 Nov 2023 05:51:25 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4083dbc43cfso13342015e9.3; Mon, 20 Nov 2023 05:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488283; x=1701093083; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BkZZkQ+fhxkG3W91GuOjhKRxuNJAr/jVw9bM/JNE+9s=; b=J1+btUUb5WrurF6QYxTmgcKDcBACAHe7JecqQG9TaU/nGjgjop+jVcw2UQwd8WD/zT qTDGlnckUUg5WW/j0+38PGul3U7gP3YxWTG4fJFwPAsepM5vFu8wwc35hdWldFSFAqRW tX+HHQLCDRv47891OnVmT+Oc424B+olrIast+XdLvX2LmnCL1baWlGZoXc9yzhoAD9zO FWk/zGq3Ukfx7NKJw4Jmq2m3OFAdixqvSAGP4I75A2V9kSverqRZSeB7W34XpF7ogD3l f8M94ws1diEFoAeFvq2i49Gk7/NQF4aK+TnTnvP5zrzdxKBVfQceY1GKCukfSvx4Ku40 psIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488283; x=1701093083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BkZZkQ+fhxkG3W91GuOjhKRxuNJAr/jVw9bM/JNE+9s=; b=stdnmm8qSa9QElTAyfvX67b42xAa5++eTyBcrTR316hCI3MILRXebDCZ6sq/YKghFo xde2+fUnECCJHqMfeY+My2PmgjRVFnvxDlDR/HX8GjvGwyIGyUBbiO4o4DJTUJwqNSy5 Kap7h8jMBRc8wTogYTDB+/sETDg0LhGbBW2SG9H7x0wNXfxJY/oqiRXupxLhttoypcUe fZb+DADfK8SSEujFu4bP6lBrJvnnP2yW0KIvhbDZ+wptQHV+FUvm/lvbPnkX3ePAb/xb zoxhjX0t/sL2mVrVqsiDoWzyOeWiA4kLN8gsabpxZHnpHLPzuJF5M6j8cdhcJjPynWyG kPzQ== X-Gm-Message-State: AOJu0YzlDcGdYhlStmYAG2xt6J0BmumwSdCd/pWc0lbI48J/cNZO0QQP vSnepkRDCKGWOf/wkRWm128= X-Google-Smtp-Source: AGHT+IHHHmLbo0ls+ZfdjXnfQDFKRg9UMz3ucecEJfw4iq5blHC0EFBdWzjf+AlCouNSkFhaXzhm/Q== X-Received: by 2002:a05:600c:3b8c:b0:407:5b54:bb10 with SMTP id n12-20020a05600c3b8c00b004075b54bb10mr5935396wms.8.1700488283168; Mon, 20 Nov 2023 05:51:23 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:22 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 07/14] net: phy: add support for driver specific PHY package probe/config Date: Mon, 20 Nov 2023 14:50:34 +0100 Message-Id: <20231120135041.15259-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add PHY driver specific function to probe and configure PHY package. These function are run only once before the PHY probe and config_init. They are used in conjunction with DT PHY package define for basic PHY package implementation to setup and probe PHY package with simple functions directly defined in the PHY driver struct. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 14 ++++++++++++++ include/linux/phy.h | 21 +++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 91d17129b774..0b7ba6995929 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1246,6 +1246,13 @@ int phy_init_hw(struct phy_device *phydev) if (ret < 0) return ret; + if (phydev->drv->phy_package_config_init_once && + phy_package_init_once(phydev)) { + ret = phydev->drv->phy_package_config_init_once(phydev); + if (ret < 0) + return ret; + } + if (phydev->drv->config_init) { ret = phydev->drv->config_init(phydev); if (ret < 0) @@ -3386,6 +3393,13 @@ static int phy_probe(struct device *dev) /* Deassert the reset signal */ phy_device_reset(phydev, 0); + if (phydev->drv->phy_package_probe_once && + phy_package_probe_once(phydev)) { + err = phydev->drv->phy_package_probe_once(phydev); + if (err) + goto out; + } + if (phydev->drv->probe) { err = phydev->drv->probe(phydev); if (err) diff --git a/include/linux/phy.h b/include/linux/phy.h index 7c47c12cffa0..1849fc637196 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -924,12 +924,33 @@ struct phy_driver { */ int (*soft_reset)(struct phy_device *phydev); + /** + * @phy_package_config_init_once: Driver specific PHY package + * config init call + * @def: PHY device to use to probe PHY package + * + * Called to initialize the PHY package, including after + * a reset. + * Called BEFORE PHY config_init. + */ + int (*phy_package_config_init_once)(struct phy_device *dev); + /** * @config_init: Called to initialize the PHY, * including after a reset */ int (*config_init)(struct phy_device *phydev); + /** + * @phy_package_probe_once: Driver specific PHY package probe + * @def: PHY device to use to probe PHY package + * + * Called during discovery once per PHY package. Used to set + * up device-specific PHY package structures, if any. + * Called BEFORE PHY probe. + */ + int (*phy_package_probe_once)(struct phy_device *dev); + /** * @probe: Called during discovery. Used to set * up device-specific structures, if any From patchwork Mon Nov 20 13:50:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 745432 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mz+Mv7wx" Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FA7610C0; Mon, 20 Nov 2023 05:51:28 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4083f613272so19033615e9.1; Mon, 20 Nov 2023 05:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488286; x=1701093086; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aMjjq9qLyKnXGA+eO91BLzIpEsWi8EWdg29zu6S5n/U=; b=mz+Mv7wx085TBN6rp/PGnQRCgBjfhDqDbQ4jGkavcfhFCno4iA1ibrWKK17O4lXHaC ShBGUkDARpSuj4iifEf2FywsjDVLdOswNTTz7j+KV37zDomUN0S0sjSLWtM4JfvRwups VkC8BHJX9iCxbV/GUSQ6dCRWcRne2amgxkaWIkGjaGRsUQSYCrMxQeLQjn0quEJKgeLY fXdifrhnFndEP387lljtsTc5mj4INsVH+HAsRuDC310pq3d2H4upeeuLL8LFxKfvk7in Ys5XjeMRlYxDQxpIfhnCOHMxHHNYbd6RD1AD6/B5ezUAwm6Oz3DmKU1er9osXZ6bNfXA fC/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488286; x=1701093086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aMjjq9qLyKnXGA+eO91BLzIpEsWi8EWdg29zu6S5n/U=; b=LvQ9/VUuXIubFGsirVrSNvDEN4oiFqSQxBimPPkigMEohI2boAGTnGxs9t/WvhXctx Cf00kJ8xacXGCmQv604cy30FVmt+zyEhW/plk676hL9wQZ6OFOZy5B6elgTjpUCjaUdN uRr93qE67f7OX+JaRVsm6Sl6rvWI78W6MN10h/lQneSgCoxnP74LC8IaIHm9mqutc8ve jKHCutMg/PzeAYoBnfdC1HYn91V7RDFka0bOELMNMqXNS9YEOjBLT0V4KVAxa6/ehCAX W2S5uzyn0yR0+Mnuzj1cQtchEYyYfZc0e6HcozV02o09S4Sc0TvCMoo8nNOjOTlXik3n Jj8w== X-Gm-Message-State: AOJu0YwCClhedLnv6gteV3p18DfgcM+Irf8bfYvwlDPgPP/Klx6RwrUg xykzJo3gBODHJRkteQU01mM= X-Google-Smtp-Source: AGHT+IELaaTlk2hOemekBls41C7RViCTII0CDMoPho0KjrhB6Lc/w0Sv0fdqN6PCiINS6TOvzE03Tg== X-Received: by 2002:a05:600c:1d1a:b0:40a:49bc:fa9d with SMTP id l26-20020a05600c1d1a00b0040a49bcfa9dmr6576777wms.26.1700488286520; Mon, 20 Nov 2023 05:51:26 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:26 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 09/14] net: phy: move mmd_phy_indirect to generic header Date: Mon, 20 Nov 2023 14:50:36 +0100 Message-Id: <20231120135041.15259-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move mmd_phy_indirect function from phy-core to generic phy.h to permit future usage for PHY package read/write_mmd. Signed-off-by: Christian Marangi --- drivers/net/phy/phy-core.c | 14 -------------- include/linux/phy.h | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..b4f80847eefd 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -526,20 +526,6 @@ int phy_speed_down_core(struct phy_device *phydev) return 0; } -static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, - u16 regnum) -{ - /* Write the desired MMD Devad */ - __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); - - /* Write the desired MMD register address */ - __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); - - /* Select the Function : DATA with no post increment */ - __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, - devad | MII_MMD_CTRL_NOINCR); -} - /** * __phy_read_mmd - Convenience function for reading a register * from an MMD on a given PHY. diff --git a/include/linux/phy.h b/include/linux/phy.h index 8af0a8a72b88..dd2381652dd1 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1361,6 +1361,20 @@ static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum, regnum, mask, set); } +static inline void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, + u16 regnum) +{ + /* Write the desired MMD Devad */ + __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); + + /* Select the Function : DATA with no post increment */ + __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, + devad | MII_MMD_CTRL_NOINCR); +} + /* * phy_read_mmd - Convenience function for reading a register * from an MMD on a given PHY. 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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:29 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 11/14] dt-bindings: net: add QCA807x PHY defines Date: Mon, 20 Nov 2023 14:50:38 +0100 Message-Id: <20231120135041.15259-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Robert Marko Add DT bindings defined for Qualcomm QCA807x PHY series related to calibration and DAC settings. Signed-off-by: Robert Marko Signed-off-by: Christian Marangi --- include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/net/qcom-qca807x.h diff --git a/include/dt-bindings/net/qcom-qca807x.h b/include/dt-bindings/net/qcom-qca807x.h new file mode 100644 index 000000000000..42c45c7d5210 --- /dev/null +++ b/include/dt-bindings/net/qcom-qca807x.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Device Tree constants for the Qualcomm QCA807X PHYs + */ + +#ifndef _DT_BINDINGS_QCOM_QCA807X_H +#define _DT_BINDINGS_QCOM_QCA807X_H + +#define PSGMII_QSGMII_TX_DRIVER_140MV 0 +#define PSGMII_QSGMII_TX_DRIVER_160MV 1 +#define PSGMII_QSGMII_TX_DRIVER_180MV 2 +#define PSGMII_QSGMII_TX_DRIVER_200MV 3 +#define PSGMII_QSGMII_TX_DRIVER_220MV 4 +#define PSGMII_QSGMII_TX_DRIVER_240MV 5 +#define PSGMII_QSGMII_TX_DRIVER_260MV 6 +#define PSGMII_QSGMII_TX_DRIVER_280MV 7 +#define PSGMII_QSGMII_TX_DRIVER_300MV 8 +#define PSGMII_QSGMII_TX_DRIVER_320MV 9 +#define PSGMII_QSGMII_TX_DRIVER_400MV 10 +#define PSGMII_QSGMII_TX_DRIVER_500MV 11 +/* Default value */ +#define PSGMII_QSGMII_TX_DRIVER_600MV 12 + +/* Full amplitude, full bias current */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0 +/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1 +/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2 +/* Both amplitude and bias current follow DSP */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3 +/* Full amplitude, half bias current */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4 +/* Amplitude follow DSP setting; 1/4 bias current when cable<10m, + * otherwise half bias current + */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5 +/* Full amplitude; same bias current setting with “010” and “011”, + * but half more bias is reduced when cable <10m + */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6 +/* Amplitude follow DSP; same bias current setting with “110”, default value */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7 + +#endif From patchwork Mon Nov 20 13:50:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 745430 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MIyUMT8P" Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC186D4B; Mon, 20 Nov 2023 05:51:36 -0800 (PST) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2c87acba73bso17908651fa.1; Mon, 20 Nov 2023 05:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488295; x=1701093095; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GIf/7OpP8VtEJNt4sR3DXzoJdNlezeJaMEZxH0YUM0o=; b=MIyUMT8PelQ67olLv87UXHhxjI/iyYzIpcE7MB8VsB89H20cJ2nFoNBO0NrzWb+5Yn YrIwlpYjZTyw1jtUxbdbo0KSVMyu1KsAwPobUaKyQhz8nyj8Ju0OeogEp/3SlE9adC86 odY5xKHtMdWL3CxbfF3xvaQQDi7CAQrJIP9kON0Zce6UD3JqwYRSfHvgr7tIPNjpknLc T/SsL7zp79atKX1wG3X/Ifbqcoxh+iZNy9yQj+DDXeLufplN5czqrcBE34yCkvr/boq5 Tb/vQojqATc5naYmUUwIKMkQvtfTP26aXRohigRPTHli/U9CeUo3aIGx8VE+W6vIa5Br VYVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488295; x=1701093095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GIf/7OpP8VtEJNt4sR3DXzoJdNlezeJaMEZxH0YUM0o=; b=ioYxNpExWLWtXJKbL/ioc3MV6MmaIiNMd2/xrGTEvaaAYG3D5XHyJdDIDMmN4Nhbbo JXeQcskfMyw9EuV5ndOP4mDJMe3nf3a3kxCIv71an7y2e4lAu+X0qy2m/o0VaehwwdGz Dww0EqnLPNQVLZogegRV8Fu2ZZSeqDUJRbVvsp3jZKHX9utap8IHauiPnuoQvcKfAhSs KRpNuQHKLbEJWoicZs9toTSoFiZWEPdjIpRwzn77sbV7oFwGI46+4xWu5qMhWEhyYFcH c5g2FAnlo5Psb+Nv2VlaqWcSm2QT/qKGSqlTGrzRPVf6h+sRTJi9WqqAz3kLi78vCjKn 9BJg== X-Gm-Message-State: AOJu0Yy6qGViDtMklo0SzR25DVitlv5jl9CzsS5+VmdQ1pxjXh8eXq1V mVLCo07NV3YP17DUnRP0q+F4JCvJ3ZQ= X-Google-Smtp-Source: AGHT+IGNG/CqatG35iNvkBw+BbCu3x+dR7FxjR/Rwbwjxh+7pqa/JRoV2sSvFgNdFxXPxvvTAa8z6A== X-Received: by 2002:a05:651c:311:b0:2c8:5b9b:397c with SMTP id a17-20020a05651c031100b002c85b9b397cmr4630573ljp.32.1700488294817; Mon, 20 Nov 2023 05:51:34 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:34 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 14/14] net: phy: qca807x: Add support for configurable LED Date: Mon, 20 Nov 2023 14:50:41 +0100 Message-Id: <20231120135041.15259-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 QCA8072/5 have up to 2 LEDs attached for PHY. LEDs can be configured to be ON/hw blink or be set to HW control. Hw blink mode is set to blink at 4Hz or 250ms. PHY can support both copper (TP) or fiber (FIBRE) kind and supports different HW control modes based on the port type. HW control modes supported for netdev trigger for copper ports are: - LINK_10 - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX HW control modes supported for netdev trigger for fiber ports are: - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX LED support conflicts with GPIO controller feature and must be disabled if gpio-controller is used for the PHY. Signed-off-by: Christian Marangi --- drivers/net/phy/qca807x.c | 382 +++++++++++++++++++++++++++++++++++++- 1 file changed, 375 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/qca807x.c b/drivers/net/phy/qca807x.c index 5b82af52778a..a0daf65d872d 100644 --- a/drivers/net/phy/qca807x.c +++ b/drivers/net/phy/qca807x.c @@ -80,17 +80,60 @@ #define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a #define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0) +#define QCA807X_MMD7_LED_GLOBAL 0x8073 +#define QCA807X_LED_BLINK_1 GENMASK(11, 6) +#define QCA807X_LED_BLINK_2 GENMASK(5, 0) +/* Values are the same for both BLINK_1 and BLINK_2 */ +#define QCA807X_LED_BLINK_FREQ_MASK GENMASK(5, 3) +#define QCA807X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x0) +#define QCA807X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x1) +#define QCA807X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x2) +#define QCA807X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x3) +#define QCA807X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x4) +#define QCA807X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x5) +#define QCA807X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x6) +#define QCA807X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x7) +#define QCA807X_LED_BLINK_DUTY_MASK GENMASK(2, 0) +#define QCA807X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x0) +#define QCA807X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x1) +#define QCA807X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x2) +#define QCA807X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x3) +#define QCA807X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x4) +#define QCA807X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x5) +#define QCA807X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x6) +#define QCA807X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x7) #define QCA807X_MMD7_LED_100N_1 0x8074 #define QCA807X_MMD7_LED_100N_2 0x8075 #define QCA807X_MMD7_LED_1000N_1 0x8076 #define QCA807X_MMD7_LED_1000N_2 0x8077 -#define QCA807X_LED_TXACT_BLK_EN_2 BIT(10) -#define QCA807X_LED_RXACT_BLK_EN_2 BIT(9) -#define QCA807X_LED_GT_ON_EN_2 BIT(6) -#define QCA807X_LED_HT_ON_EN_2 BIT(5) -#define QCA807X_LED_BT_ON_EN_2 BIT(4) -#define QCA807X_GPIO_FORCE_EN BIT(15) -#define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13) +/* Values are the same for LED1 and LED2 */ +/* Values for control 1 */ +#define QCA807X_LED_COPPER_ON_BLINK_MASK GENMASK(12, 0) +#define QCA807X_LED_FDX_ON_EN BIT(12) +#define QCA807X_LED_HDX_ON_EN BIT(11) +#define QCA807X_LED_TXACT_BLK_EN BIT(10) +#define QCA807X_LED_RXACT_BLK_EN BIT(9) +#define QCA807X_LED_GT_ON_EN BIT(6) +#define QCA807X_LED_HT_ON_EN BIT(5) +#define QCA807X_LED_BT_ON_EN BIT(4) +/* Values for control 2 */ +#define QCA807X_LED_FORCE_EN BIT(15) +#define QCA807X_LED_FORCE_MODE_MASK GENMASK(14, 13) +#define QCA807X_LED_FORCE_BLINK_1 FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x3) +#define QCA807X_LED_FORCE_BLINK_2 FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x2) +#define QCA807X_LED_FORCE_ON FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x1) +#define QCA807X_LED_FORCE_OFF FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x0) +#define QCA807X_LED_FIBER_ON_BLINK_MASK GENMASK(11, 1) +#define QCA807X_LED_FIBER_TXACT_BLK_EN BIT(10) +#define QCA807X_LED_FIBER_RXACT_BLK_EN BIT(9) +#define QCA807X_LED_FIBER_FDX_ON_EN BIT(6) +#define QCA807X_LED_FIBER_HDX_ON_EN BIT(5) +#define QCA807X_LED_FIBER_1000BX_ON_EN BIT(2) +#define QCA807X_LED_FIBER_100FX_ON_EN BIT(1) + +/* Some device repurpose the LED as GPIO out */ +#define QCA807X_GPIO_FORCE_EN QCA807X_LED_FORCE_EN +#define QCA807X_GPIO_FORCE_MODE_MASK QCA807X_LED_FORCE_MODE_MASK #define QCA807X_INTR_ENABLE 0x12 #define QCA807X_INTR_STATUS 0x13 @@ -338,6 +381,320 @@ static int qca807x_cable_test_start(struct phy_device *phydev) return ret; } +static int qca807x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, + u16 *offload_trigger) +{ + /* Parsing specific to netdev trigger */ + switch (phydev->port) { + case PORT_TP: + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA807X_LED_TXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA807X_LED_RXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) + *offload_trigger |= QCA807X_LED_BT_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA807X_LED_HT_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA807X_LED_GT_ON_EN; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_HDX_ON_EN; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FDX_ON_EN; + break; + case PORT_FIBRE: + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_TXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_RXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_100FX_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_1000BX_ON_EN; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_HDX_ON_EN; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_FDX_ON_EN; + break; + default: + return -EOPNOTSUPP; + } + + if (rules && !*offload_trigger) + return -EOPNOTSUPP; + + return 0; +} + +static int qca807x_led_hw_control_enable(struct phy_device *phydev, u8 index) +{ + int val, reg, ret; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~QCA807X_LED_FORCE_EN; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + return ret; +} + +static int qca807x_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 offload_trigger = 0; + + if (index > 1) + return -EINVAL; + + return qca807x_led_parse_netdev(phydev, rules, &offload_trigger); +} + +static int qca807x_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int val, ret, copper_reg, fibre_reg; + u16 offload_trigger = 0; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + ret = qca807x_led_parse_netdev(phydev, rules, &offload_trigger); + if (ret) + return ret; + + ret = qca807x_led_hw_control_enable(phydev, index); + if (ret) + return ret; + + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + val &= ~QCA807X_LED_COPPER_ON_BLINK_MASK; + val |= offload_trigger; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, copper_reg, val); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + val &= ~QCA807X_LED_FIBER_ON_BLINK_MASK; + val |= offload_trigger; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, fibre_reg, val); + break; + default: + return -EINVAL; + } + + return ret; +} + +static bool qca807x_led_hw_control_status(struct phy_device *phydev, u8 index) +{ + int val, reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return false; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + + return !(val & QCA807X_LED_FORCE_EN); +} + +static int qca807x_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + int val, copper_reg, fibre_reg; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + default: + return -EINVAL; + } + + /* Check if we have hw control enabled */ + if (qca807x_led_hw_control_status(phydev, index)) + return -EINVAL; + + /* Parsing specific to netdev trigger */ + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + if (val & QCA807X_LED_TXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA807X_LED_RXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA807X_LED_BT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_10, rules); + if (val & QCA807X_LED_HT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA807X_LED_GT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA807X_LED_HDX_ON_EN) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA807X_LED_FDX_ON_EN) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + if (val & QCA807X_LED_FIBER_TXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA807X_LED_FIBER_RXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA807X_LED_FIBER_100FX_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA807X_LED_FIBER_1000BX_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA807X_LED_FIBER_HDX_ON_EN) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA807X_LED_FIBER_FDX_ON_EN) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int qca807x_led_hw_control_reset(struct phy_device *phydev, u8 index) +{ + int val, copper_reg, fibre_reg, ret; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + default: + return -EINVAL; + } + + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + val &= ~QCA807X_LED_COPPER_ON_BLINK_MASK; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, copper_reg, val); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + val &= ~QCA807X_LED_FIBER_ON_BLINK_MASK; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, fibre_reg, val); + break; + default: + return -EINVAL; + } + + return ret; +} + +static int qca807x_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + int val, ret; + u16 reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + /* If we are setting off the LED reset any hw control rule */ + if (!value) { + ret = qca807x_led_hw_control_reset(phydev, index); + if (ret) + return ret; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~(QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_MODE_MASK); + val |= QCA807X_LED_FORCE_EN; + if (value) + val |= QCA807X_LED_FORCE_ON; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + return ret; +} + +static int qca807x_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + int val, ret; + u16 reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + /* Set blink to 50% off, 50% on at 4Hz by default */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_GLOBAL); + val &= ~(QCA807X_LED_BLINK_FREQ_MASK | QCA807X_LED_BLINK_DUTY_MASK); + val |= QCA807X_LED_BLINK_FREQ_4HZ | QCA807X_LED_BLINK_DUTY_50_50; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_GLOBAL, val); + + /* We use BLINK_1 for normal blinking */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~(QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_MODE_MASK); + val |= QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_BLINK_1; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + /* We set blink to 4Hz, aka 250ms */ + *delay_on = 250 / 2; + *delay_off = 250 / 2; + + return ret; +} + #ifdef CONFIG_GPIOLIB static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) { @@ -716,6 +1073,12 @@ static int qca807x_probe(struct phy_device *phydev) ret = qca807x_gpio(phydev); if (ret) return ret; + + phydev->drv->led_brightness_set = NULL; + phydev->drv->led_blink_set = NULL; + phydev->drv->led_hw_is_supported = NULL; + phydev->drv->led_hw_control_set = NULL; + phydev->drv->led_hw_control_get = NULL; } } @@ -843,6 +1206,11 @@ static struct phy_driver qca807x_drivers[] = { .suspend = genphy_suspend, .cable_test_start = qca807x_cable_test_start, .cable_test_get_status = qca807x_cable_test_get_status, + .led_brightness_set = qca807x_led_brightness_set, + .led_blink_set = qca807x_led_blink_set, + .led_hw_is_supported = qca807x_led_hw_is_supported, + .led_hw_control_set = qca807x_led_hw_control_set, + .led_hw_control_get = qca807x_led_hw_control_get, /* PHY package define */ .phy_package_global_phy_num = ARRAY_SIZE(qca807x_global_phy_names), .phy_package_global_phy_names = qca807x_global_phy_names,