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[209.51.188.17]) by mx.google.com with ESMTPS id n4-20020a0cbe84000000b00647290d544bsi6025660qvi.296.2023.11.19.14.52.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 19 Nov 2023 14:52:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QSuoeG0T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r4qdI-0004ui-VC; Sun, 19 Nov 2023 17:51:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r4qdH-0004sx-Vv for qemu-devel@nongnu.org; Sun, 19 Nov 2023 17:51:16 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r4qdG-0002CN-3p for qemu-devel@nongnu.org; Sun, 19 Nov 2023 17:51:15 -0500 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-5484ef5e3d2so3162830a12.3 for ; Sun, 19 Nov 2023 14:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700434272; x=1701039072; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h4OQ2JZwpVK0ANfHSLEyOk1u/diKUfR9mXGb8Hv9bX8=; b=QSuoeG0T1X9eWDSn/tteZrUv6rDp3+k8Vu6nsTuFDa+4tNDxdHoCyfOC/xPzU/7hEJ P7PB0pUv4SgjSX7My1zYNaQdGcvkPp2eRdtGDj8fJ2ryP2nKsVocP9fXc9cOOBR9zonK KvD3aFulhtMIw4wYke39fNMaRboyySNtJFnjqQ+jCRDDjVXFWHoU0tY/FXjzi8Wqyxlc f4PQIYXvKiqqlAka6Rzj62nXHYntAv4DouZ0tJPkZHfRA+P1lAOw7b7P1R1znOdHdjZM 9hZmsn80rGJBBbUOel0K8D5vahtTUva8czs91WYbLU2gmUOY7fE/4AeThvHRNaB1humZ TT2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700434272; x=1701039072; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h4OQ2JZwpVK0ANfHSLEyOk1u/diKUfR9mXGb8Hv9bX8=; b=ZPFUvMcfMRabI/0izazEWUItEQr9cDLyq7L4FHTDDcRfc1CMuNGOOtiEhtrK1DX6Cg 2NGZ7h/7F1sixOxGyOAYIcDzt6SHs7ggpcc6C2MY64liaWyKuULlT+uWIlL08SSO/Z+N /vmzjxJ70C0eWdX0zuD2f+7aZ9S2ljMQG/meDFe8pP4yZwqop/N/oPCHeRi9nLYwHJqM +Mra14AR0hSVbcng14TB1s2GS1FaNw4v9tg0PVjN2A9BhUi2oS4E1NsXkoG/lP7CGjXj O7YNglCk3x6UL+d+VxT4ACUp3deZjQFUxIZtzcdlUQ/JsXimWjjdVXHX8oNAeYUDB4Qz Wnsg== X-Gm-Message-State: AOJu0Yy2iUowAtHZrExRlDFNH8bfLm1ruz3RinG8soQAf0FyKBPVUeul vvSeepr4smkl50K9h28YESiCNluPSlUkxS/t2do= X-Received: by 2002:aa7:d648:0:b0:543:5364:33b4 with SMTP id v8-20020aa7d648000000b00543536433b4mr4292607edr.11.1700434272299; Sun, 19 Nov 2023 14:51:12 -0800 (PST) Received: from m1x-phil.lan ([176.187.211.133]) by smtp.gmail.com with ESMTPSA id p9-20020a056402044900b0054868b36118sm2058684edw.32.2023.11.19.14.51.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 19 Nov 2023 14:51:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Anton Kochkov , Francisco Iglesias , Vikram Garhwal , Jason Wang , Pavel Pisa , Vikram Garhwal , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Qiang Liu Subject: [PATCH-for-8.2 v2 1/2] hw/net/can/xlnx-zynqmp: Avoid underflow while popping TX FIFOs Date: Sun, 19 Nov 2023 23:51:01 +0100 Message-ID: <20231119225102.49227-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231119225102.49227-1-philmd@linaro.org> References: <20231119225102.49227-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format Message Format The same message format is used for RXFIFO, TXFIFO, and TXHPB. Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. There is no mention in this reference manual about what the hardware does when not all four words are written. To fix the reported underflow behavior when DATA2 register is written, I choose to fill the data with the previous content of the ID / DLC / DATA1 registers, which is how I expect hardware would do. Note there is no hardware flag raised under such condition. Reported-by: Qiang Liu Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425 Signed-off-by: Philippe Mathieu-Daudé Francisco Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal --- hw/net/can/xlnx-zynqmp-can.c | 49 +++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index e93e6c5e19..58938b574e 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -434,6 +434,51 @@ static bool tx_ready_check(XlnxZynqMPCANState *s) return true; } +static void read_tx_frame(XlnxZynqMPCANState *s, Fifo32 *fifo, uint32_t *data) +{ + unsigned used = fifo32_num_used(fifo); + bool is_txhpb = fifo == &s->txhpb_fifo; + + assert(used > 0); + used %= CAN_FRAME_SIZE; + + /* + * Frame Message Format + * + * Each frame includes four words (16 bytes). Software must read and write + * all four words regardless of the actual number of data bytes and valid + * fields in the message. + * If software misbehave (not writting all four words), we use the previous + * registers content to initialize each missing word. + */ + if (used > 0) { + /* ID, DLC, DATA1 missing */ + data[0] = s->regs[is_txhpb ? R_TXHPB_ID : R_TXFIFO_ID]; + } else { + data[0] = fifo32_pop(fifo); + } + if (used == 1 || used == 2) { + /* DLC, DATA1 missing */ + data[1] = s->regs[is_txhpb ? R_TXHPB_DLC : R_TXFIFO_DLC]; + } else { + data[1] = fifo32_pop(fifo); + } + if (used == 1) { + /* DATA1 missing */ + data[2] = s->regs[is_txhpb ? R_TXHPB_DATA1 : R_TXFIFO_DATA1]; + } else { + data[2] = fifo32_pop(fifo); + } + /* DATA2 triggered the transfer thus is always available */ + data[3] = fifo32_pop(fifo); + + if (used) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Incomplete CAN frame (only %u/%u slots used)\n", + TYPE_XLNX_ZYNQMP_CAN, used, CAN_FRAME_SIZE); + } +} + static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) { qemu_can_frame frame; @@ -451,9 +496,7 @@ static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) } while (!fifo32_is_empty(fifo)) { - for (i = 0; i < CAN_FRAME_SIZE; i++) { - data[i] = fifo32_pop(fifo); - } + read_tx_frame(s, fifo, data); if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { /* From patchwork Sun Nov 19 22:51:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 745167 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1004976wrt; Sun, 19 Nov 2023 14:52:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IG2pZtBQTlDPOYoq7kPZNIhAupF8c4Cfqg07WjDbEVtJ925MDZYU2MxFIl5o88tYoTEqLvG X-Received: by 2002:a05:6214:b6d:b0:65d:afc:3a52 with SMTP id ey13-20020a0562140b6d00b0065d0afc3a52mr5601951qvb.49.1700434333113; Sun, 19 Nov 2023 14:52:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700434333; cv=none; d=google.com; s=arc-20160816; b=imJyt7eUCGXtWV2TIQmVmwbwxjoeJ8MqEywsEA4oI4TRMpTdSJRu4Lj8Alxp0CFM9U l+QejACaCxufPxpvI3tY/W0oUWxvWmUHGC3NPIttIT14GWTALl4N2wpMnYN/s5yq+3lc jlEgxpH4DXSVNibEYl6lknzrbjIU8ZPGm/4prRByNTifKva7N5qhhBiuVhAUKGKAVwq3 klMitic92dehco98WU+2YHcipuhtiNrYcYj12J4+hF9dQOpPtvtxoqtN4O0fUIr8cr8r N+3Ci038kHOmn1LOHeGrqWcsB9FvTMBHSxU6LDY3rjhh0t66IBmYxuMrUkcsWol+O9Sm WfgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=l+TRmFh4XF/6EizUthtIP3l2xJd8V/WH+CN52HJC1Pc=; fh=E+IIPxsux72z/SZO0QcIq2xbtRtMS5ItqK5FSbXRijY=; b=tfGwDXv9XHcyWbPNuLdP3ctu5P/XIQbU3bjarm0tC74Z1Wbwy9ETVs/QNgrLG6sDP9 3WTyjG5int04sOkqkiyBDjRcObl0U/T0QMZ/LQIHLI8VXoYP5GOzrkWuFMYrquHtsZBQ /QSTF4wVtR7bgTMtHcDD3X7y7jnqc03md0/Mgb0RjLCJOMg1ZA9xXwvc6kRHaEOwjva1 C/CJ/H/bRx/GFYuBIqbm5ynRPFqVOL0wqu1pxlOK27njNup6YR5dEDYyxZtdTKSQax2n N7tqAj8jtxT34Vy86Z4/tyZv57wdjqUu80kCqHY2WtDjgU7bYeMDC54vHIfSPWuqOIkH JZqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O1XTQe4A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Each message includes four words (16 bytes). Software must read and write all four words regardless of the actual number of data bytes and valid fields in the message. There is no mention in this reference manual about what the hardware does when not all four words are read. To fix the reported underflow behavior, I choose to fill the 4 frame data registers when the first register (ID) is accessed, which is how I expect hardware would do. Reported-by: Qiang Liu Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1427 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Vikram Garhwal --- hw/net/can/xlnx-zynqmp-can.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index 58938b574e..c63fb4a83c 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -777,14 +777,18 @@ static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame) } } -static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val) +static uint64_t can_rxfifo_post_read_id(RegisterInfo *reg, uint64_t val) { XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); + unsigned used = fifo32_num_used(&s->rx_fifo); - if (!fifo32_is_empty(&s->rx_fifo)) { - val = fifo32_pop(&s->rx_fifo); - } else { + if (used < CAN_FRAME_SIZE) { ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); + } else { + val = s->regs[R_RXFIFO_ID] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DLC] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DATA1] = fifo32_pop(&s->rx_fifo); + s->regs[R_RXFIFO_DATA2] = fifo32_pop(&s->rx_fifo); } can_update_irq(s); @@ -945,14 +949,11 @@ static const RegisterAccessInfo can_regs_info[] = { .post_write = can_tx_post_write, },{ .name = "RXFIFO_ID", .addr = A_RXFIFO_ID, .ro = 0xffffffff, - .post_read = can_rxfifo_pre_read, + .post_read = can_rxfifo_post_read_id, },{ .name = "RXFIFO_DLC", .addr = A_RXFIFO_DLC, .rsvd = 0xfff0000, - .post_read = can_rxfifo_pre_read, },{ .name = "RXFIFO_DATA1", .addr = A_RXFIFO_DATA1, - .post_read = can_rxfifo_pre_read, },{ .name = "RXFIFO_DATA2", .addr = A_RXFIFO_DATA2, - .post_read = can_rxfifo_pre_read, },{ .name = "AFR", .addr = A_AFR, .rsvd = 0xfffffff0, .post_write = can_filter_enable_post_write,