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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00001504.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Fri, 17 Nov 2023 17:42:46 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 11:42:45 -0600 Received: from xsjtanmays50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Fri, 17 Nov 2023 11:42:44 -0600 From: Tanmay Shah To: , , , , , , , CC: , , , , Radhey Shyam Pandey , Rob Herring Subject: [PATCH v7 1/4] dt-bindings: remoteproc: add Tightly Coupled Memory (TCM) bindings Date: Fri, 17 Nov 2023 09:42:35 -0800 Message-ID: <20231117174238.1876655-2-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231117174238.1876655-1-tanmay.shah@amd.com> References: <20231117174238.1876655-1-tanmay.shah@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001504:EE_|SJ1PR12MB6098:EE_ X-MS-Office365-Filtering-Correlation-Id: 83b6faa2-8198-497e-dd38-08dbe7949c54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 17:42:46.6103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83b6faa2-8198-497e-dd38-08dbe7949c54 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001504.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6098 From: Radhey Shyam Pandey Introduce bindings for TCM memory address space on AMD-xilinx Zynq UltraScale+ platform. It will help in defining TCM in device-tree and make it's access platform agnostic and data-driven. Tightly-coupled memories(TCMs) are low-latency memory that provides predictable instruction execution and predictable data load/store timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory banks on the ATCM and BTCM ports, for a total of 128 KB of memory. The TCM resources(reg, reg-names and power-domain) are documented for each TCM in the R5 node. The reg and reg-names are made as required properties as we don't want to hardcode TCM addresses for future platforms and for zu+ legacy implementation will ensure that the old dts w/o reg/reg-names works and stable ABI is maintained. It also extends the examples for TCM split and lockstep modes. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Tanmay Shah Acked-by: Rob Herring --- .../remoteproc/xlnx,zynqmp-r5fss.yaml | 131 +++++++++++++++--- 1 file changed, 113 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml index 78aac69f1060..9ecd63ea1b38 100644 --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml @@ -20,6 +20,17 @@ properties: compatible: const: xlnx,zynqmp-r5fss + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: + description: | + Standard ranges definition providing address translations for + local R5F TCM address spaces to bus addresses. + xlnx,cluster-mode: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] @@ -37,7 +48,7 @@ properties: 2: single cpu mode patternProperties: - "^r5f-[a-f0-9]+$": + "^r5f@[0-9a-f]+$": type: object description: | The RPU is located in the Low Power Domain of the Processor Subsystem. @@ -54,8 +65,19 @@ patternProperties: compatible: const: xlnx,zynqmp-r5f + reg: + items: + - description: ATCM internal memory region + - description: BTCM internal memory region + + reg-names: + items: + - const: atcm + - const: btcm + power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 mboxes: minItems: 1 @@ -102,34 +124,107 @@ patternProperties: required: - compatible - power-domains + - reg + - reg-names unevaluatedProperties: false required: - compatible + - "#address-cells" + - "#size-cells" + - ranges additionalProperties: false examples: - | - remoteproc { - compatible = "xlnx,zynqmp-r5fss"; - xlnx,cluster-mode = <1>; - - r5f-0 { - compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware 0x7>; - memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; - mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; - mbox-names = "tx", "rx"; + #include + + //Split mode configuration + soc { + #address-cells = <2>; + #size-cells = <2>; + + remoteproc@ffe00000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; }; + }; - r5f-1 { - compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware 0x8>; - memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; - mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; - mbox-names = "tx", "rx"; + - | + //Lockstep configuration + soc { + #address-cells = <2>; + #size-cells = <2>; + + remoteproc@ffe00000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x20000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x20000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x20000>, <0x0 0x20000 0x0 0x20000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; }; }; ... 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Fri, 17 Nov 2023 11:42:46 -0600 From: Tanmay Shah To: , , , , , , , CC: , , , Subject: [PATCH v7 2/4] dts: zynqmp: add properties for TCM in remoteproc Date: Fri, 17 Nov 2023 09:42:36 -0800 Message-ID: <20231117174238.1876655-3-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231117174238.1876655-1-tanmay.shah@amd.com> References: <20231117174238.1876655-1-tanmay.shah@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD0:EE_|DS7PR12MB6048:EE_ X-MS-Office365-Filtering-Correlation-Id: f4d746f6-fdaa-4c85-3e69-08dbe7949d70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XIsWsXbCxqoRGtqgUIdsWd6s606rhTsnv61IV+pidZmeXRwuOc/eN7us9baoqAf2Vm7Va+1WespQdKpTDo0s0X8SZz8MggEncYZT5sBLufaKoXNGFKp9qnjwdBVfNsfDi4GxW+PUcf9A/Chf9fpbGhzd6jqX+wV75JXpHAlL9obY9pprztSuZa4Vs6A5WPqqujUT2DpjX9UEoOX5gyhrYmywex6hHnRSHcDkO0uGZgBlUP35vjHwnZ/Sh79HhInI1uKgQjaVgYBi+s7LuIne1qsJm7U4R9ZOoJNq9GEpCttufHtWMgQuepH/+xvef5ZEbQSab3CfYK1sqUveMBLTuPJ/DtHq+XCEQEnwnbhLZy4cu8NSVSqPx4H2XuvZOOSS1eMvMgwHyotMgm4Z30BZbhlkcQWWGAbJPUJuNlzpxUbf50uHvBIehxckfvvFSQLN1pv7DEn5+jKg9/3oh2Ub0H8owggX/RDViKCe+AHzyzbXqLZ6ZlhLq6oTXzKbnEYEvqwrzVOeTFQokNPMdaj2EqpIxPtfHJ7FpKdHNe9+YhCy4CIzTl4CUDqYtOiM6pRhzrDS5WZKxGSe1Lkg+1AWlCRAgCC4fGnWfL3qx95TRpENdVPDrXoHYfuLXQ008qitLc3b/NnkL8QHaKUi/OKM+fEU7TxU3mnF+zIf8aPdtwHNVG23gi9qLHqphsS9kxtGfZSUEMogUE6sbfwCNujpvhQT2cSpH+xs4pOch4hS9XLOWQalfUVOqOcrgmQutwLPWvwNi30zRY3TmDfh06RDpw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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This patch also adds alternative remoteproc node to represent remoteproc cluster in split mode. By default lockstep mode is enabled and users should disable it before using split mode dts. Both device-tree nodes can't be used simultaneously one of them must be disabled. For zcu102-1.0 and zcu102-1.1 board remoteproc split mode dts node is enabled and lockstep mode dts is disabled. Signed-off-by: Tanmay Shah --- .../boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 8 +++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 60 +++++++++++++++++-- 2 files changed, 63 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts index c8f71a1aec89..495ca94b45db 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts @@ -14,6 +14,14 @@ / { compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; +&rproc_split { + status = "okay"; +}; + +&rproc_lockstep { + status = "disabled"; +}; + &eeprom { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index b61fc99cd911..602e6aba7ac5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -247,19 +247,69 @@ fpga_full: fpga-full { ranges; }; - remoteproc { + rproc_lockstep: remoteproc@ffe00000 { compatible = "xlnx,zynqmp-r5fss"; xlnx,cluster-mode = <1>; - r5f-0 { + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x20000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x20000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x20000>, <0x0 0x20000 0x0 0x20000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>; + }; + }; + + rproc_split: remoteproc-split@ffe00000 { + status = "disabled"; + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_0>; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; memory-region = <&rproc_0_fw_image>; }; - r5f-1 { + r5f@1 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_1>; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm", "btcm"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_1_fw_image>; }; }; From patchwork Fri Nov 17 17:42:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 744749 Authentication-Results: smtp.subspace.kernel.org; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 17:42:48.6332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bf99c33-5518-4d45-28be-08dbe7949d87 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4561 Use TCM pm domains extracted from device-tree to power on/off TCM using general pm domain framework. Signed-off-by: Tanmay Shah --- Changes in v7: - %s/pm_dev1/pm_dev_core0/r - %s/pm_dev_link1/pm_dev_core0_link/r - %s/pm_dev2/pm_dev_core1/r - %s/pm_dev_link2/pm_dev_core1_link/r - remove pm_domain_id check to move next patch - add comment about how 1st entry in pm domain list is used - fix loop when jump to fail_add_pm_domains loop drivers/remoteproc/xlnx_r5_remoteproc.c | 215 +++++++++++++++++++++++- 1 file changed, 212 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 4395edea9a64..22bccc5075a0 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "remoteproc_internal.h" @@ -102,6 +103,12 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { * @rproc: rproc handle * @pm_domain_id: RPU CPU power domain id * @ipi: pointer to mailbox information + * @num_pm_dev: number of tcm pm domain devices for this core + * @pm_dev_core0: pm domain virtual devices for power domain framework + * @pm_dev_core0_link: pm domain device links after registration + * @pm_dev_core1: used only in lockstep mode. second core's pm domain virtual devices + * @pm_dev_core1_link: used only in lockstep mode. second core's pm device links after + * registration */ struct zynqmp_r5_core { struct device *dev; @@ -111,6 +118,11 @@ struct zynqmp_r5_core { struct rproc *rproc; u32 pm_domain_id; struct mbox_info *ipi; + int num_pm_dev; + struct device **pm_dev_core0; + struct device_link **pm_dev_core0_link; + struct device **pm_dev_core1; + struct device_link **pm_dev_core1_link; }; /** @@ -651,7 +663,8 @@ static int add_tcm_carveout_lockstep_mode(struct rproc *rproc) ZYNQMP_PM_CAPABILITY_ACCESS, 0, ZYNQMP_PM_REQUEST_ACK_BLOCKING); if (ret < 0) { - dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id); + dev_err(dev, "failed to turn on TCM 0x%x", + pm_domain_id); goto release_tcm_lockstep; } @@ -758,6 +771,189 @@ static int zynqmp_r5_parse_fw(struct rproc *rproc, const struct firmware *fw) return ret; } +static void zynqmp_r5_remove_pm_domains(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + struct device *dev = r5_core->dev; + struct zynqmp_r5_cluster *cluster; + int i; + + cluster = platform_get_drvdata(to_platform_device(dev->parent)); + + for (i = 1; i < r5_core->num_pm_dev; i++) { + device_link_del(r5_core->pm_dev_core0_link[i]); + dev_pm_domain_detach(r5_core->pm_dev_core0[i], false); + } + + kfree(r5_core->pm_dev_core0); + r5_core->pm_dev_core0 = NULL; + kfree(r5_core->pm_dev_core0_link); + r5_core->pm_dev_core0_link = NULL; + + if (cluster->mode == SPLIT_MODE) { + r5_core->num_pm_dev = 0; + return; + } + + for (i = 1; i < r5_core->num_pm_dev; i++) { + device_link_del(r5_core->pm_dev_core1_link[i]); + dev_pm_domain_detach(r5_core->pm_dev_core1[i], false); + } + + kfree(r5_core->pm_dev_core1); + r5_core->pm_dev_core1 = NULL; + kfree(r5_core->pm_dev_core1_link); + r5_core->pm_dev_core1_link = NULL; + r5_core->num_pm_dev = 0; +} + +static int zynqmp_r5_add_pm_domains(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + struct device *dev = r5_core->dev, *dev2; + struct zynqmp_r5_cluster *cluster; + struct platform_device *pdev; + struct device_node *np; + int i, j, num_pm_dev, ret; + + cluster = dev_get_drvdata(dev->parent); + + /* get number of power-domains */ + num_pm_dev = of_count_phandle_with_args(r5_core->np, "power-domains", + "#power-domain-cells"); + + if (num_pm_dev <= 0) + return -EINVAL; + + r5_core->pm_dev_core0 = kcalloc(num_pm_dev, + sizeof(struct device *), + GFP_KERNEL); + if (!r5_core->pm_dev_core0) + ret = -ENOMEM; + + r5_core->pm_dev_core0_link = kcalloc(num_pm_dev, + sizeof(struct device_link *), + GFP_KERNEL); + if (!r5_core->pm_dev_core0_link) { + kfree(r5_core->pm_dev_core0); + r5_core->pm_dev_core0 = NULL; + return -ENOMEM; + } + + r5_core->num_pm_dev = num_pm_dev; + + /* + * start from 2nd entry in power-domains property list as + * for zynqmp we only add TCM power domains and not core's power domain. + * 1st entry is used to configure r5 operation mode. + */ + for (i = 1; i < r5_core->num_pm_dev; i++) { + r5_core->pm_dev_core0[i] = dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR_OR_NULL(r5_core->pm_dev_core0[i])) { + dev_dbg(dev, "failed to attach pm domain %d, ret=%ld\n", i, + PTR_ERR(r5_core->pm_dev_core0[i])); + ret = -EINVAL; + goto fail_add_pm_domains; + } + r5_core->pm_dev_core0_link[i] = device_link_add(dev, + r5_core->pm_dev_core0[i], + DL_FLAG_STATELESS | + DL_FLAG_RPM_ACTIVE | + DL_FLAG_PM_RUNTIME); + if (!r5_core->pm_dev_core0_link[i]) { + dev_pm_domain_detach(r5_core->pm_dev_core0[i], true); + r5_core->pm_dev_core0[i] = NULL; + ret = -EINVAL; + goto fail_add_pm_domains; + } + } + + if (cluster->mode == SPLIT_MODE) + return 0; + + r5_core->pm_dev_core1 = kcalloc(num_pm_dev, + sizeof(struct device *), + GFP_KERNEL); + if (!r5_core->pm_dev_core1) { + ret = -ENOMEM; + goto fail_add_pm_domains; + } + + r5_core->pm_dev_core1_link = kcalloc(num_pm_dev, + sizeof(struct device_link *), + GFP_KERNEL); + if (!r5_core->pm_dev_core1_link) { + kfree(r5_core->pm_dev_core1); + r5_core->pm_dev_core1 = NULL; + ret = -ENOMEM; + goto fail_add_pm_domains; + } + + /* get second core's device to detach its power-domains */ + np = of_get_next_child(cluster->dev->of_node, of_node_get(dev->of_node)); + + pdev = of_find_device_by_node(np); + if (!pdev) { + dev_err(cluster->dev, "core1 platform device not available\n"); + kfree(r5_core->pm_dev_core1); + kfree(r5_core->pm_dev_core1_link); + r5_core->pm_dev_core1 = NULL; + r5_core->pm_dev_core1_link = NULL; + ret = -EINVAL; + goto fail_add_pm_domains; + } + + dev2 = &pdev->dev; + + /* for zynqmp we only add TCM power domains and not core's power domain */ + for (j = 1; j < r5_core->num_pm_dev; j++) { + r5_core->pm_dev_core1[j] = dev_pm_domain_attach_by_id(dev2, j); + if (!r5_core->pm_dev_core1[j]) { + dev_dbg(dev, "can't attach to pm domain %d\n", j); + ret = -EINVAL; + goto fail_add_pm_domains_lockstep; + } else if (IS_ERR(r5_core->pm_dev_core1[j])) { + dev_dbg(dev, "can't attach to pm domain %d\n", j); + ret = PTR_ERR(r5_core->pm_dev_core1[j]); + goto fail_add_pm_domains_lockstep; + } + + r5_core->pm_dev_core1_link[j] = device_link_add(dev, + r5_core->pm_dev_core1[j], + DL_FLAG_STATELESS | + DL_FLAG_RPM_ACTIVE | + DL_FLAG_PM_RUNTIME); + if (!r5_core->pm_dev_core1_link[j]) { + dev_pm_domain_detach(r5_core->pm_dev_core1[j], true); + r5_core->pm_dev_core1[j] = NULL; + ret = -ENODEV; + goto fail_add_pm_domains_lockstep; + } + } + +fail_add_pm_domains_lockstep: + while (--j >= 0) { + device_link_del(r5_core->pm_dev_core1_link[j]); + dev_pm_domain_detach(r5_core->pm_dev_core1[j], true); + } + kfree(r5_core->pm_dev_core1); + r5_core->pm_dev_core1 = NULL; + kfree(r5_core->pm_dev_core1_link); + r5_core->pm_dev_core1_link = NULL; + +fail_add_pm_domains: + while (--i >= 0) { + device_link_del(r5_core->pm_dev_core0_link[i]); + dev_pm_domain_detach(r5_core->pm_dev_core0[i], true); + } + kfree(r5_core->pm_dev_core0); + r5_core->pm_dev_core0 = NULL; + kfree(r5_core->pm_dev_core0_link); + r5_core->pm_dev_core0_link = NULL; + + return ret; +} + /** * zynqmp_r5_rproc_prepare() * adds carveouts for TCM bank and reserved memory regions @@ -770,19 +966,30 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) { int ret; + ret = zynqmp_r5_add_pm_domains(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to add pm domains\n"); + return ret; + } + ret = add_tcm_banks(rproc); if (ret) { dev_err(&rproc->dev, "failed to get TCM banks, err %d\n", ret); - return ret; + goto fail_prepare; } ret = add_mem_regions_carveout(rproc); if (ret) { dev_err(&rproc->dev, "failed to get reserve mem regions %d\n", ret); - return ret; + goto fail_prepare; } return 0; + +fail_prepare: + zynqmp_r5_remove_pm_domains(rproc); + + return ret; } /** @@ -801,6 +1008,8 @@ static int zynqmp_r5_rproc_unprepare(struct rproc *rproc) r5_core = rproc->priv; + zynqmp_r5_remove_pm_domains(rproc); + for (i = 0; i < r5_core->tcm_bank_count; i++) { pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; if (zynqmp_pm_release_node(pm_domain_id)) From patchwork Fri Nov 17 17:42:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 744978 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="P3/c6h9X" Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2052.outbound.protection.outlook.com [40.107.96.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9373D7E; Fri, 17 Nov 2023 09:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; 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Fri, 17 Nov 2023 09:42:49 -0800 Received: from xsjtanmays50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Fri, 17 Nov 2023 11:42:48 -0600 From: Tanmay Shah To: , , , , , , , CC: , , , Subject: [PATCH v7 4/4] remoteproc: zynqmp: parse TCM from device tree Date: Fri, 17 Nov 2023 09:42:38 -0800 Message-ID: <20231117174238.1876655-5-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231117174238.1876655-1-tanmay.shah@amd.com> References: <20231117174238.1876655-1-tanmay.shah@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|DS0PR12MB8814:EE_ X-MS-Office365-Filtering-Correlation-Id: 1da520fa-eca7-4939-e146-08dbe7949e6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 17:42:50.0787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1da520fa-eca7-4939-e146-08dbe7949e6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8814 ZynqMP TCM information is fixed in driver. Now ZynqMP TCM information is available in device-tree. Parse TCM information in driver as per new bindings. Signed-off-by: Tanmay Shah --- Changes in v7: - move checking of pm_domain_id from previous patch - fix mem_bank_data memory allocation drivers/remoteproc/xlnx_r5_remoteproc.c | 152 ++++++++++++++++++++---- 1 file changed, 128 insertions(+), 24 deletions(-) diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 22bccc5075a0..270af73344ef 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -75,8 +75,8 @@ struct mbox_info { }; /* - * Hardcoded TCM bank values. This will be removed once TCM bindings are - * accepted for system-dt specifications and upstreamed in linux kernel + * Hardcoded TCM bank values. This will stay in driver to maintain backward + * compatibility with device-tree that does not have TCM information. */ static const struct mem_bank_data zynqmp_tcm_banks_split[] = { {0xffe00000UL, 0x0, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */ @@ -587,12 +587,21 @@ static int add_tcm_carveout_split_mode(struct rproc *rproc) bank_size = r5_core->tcm_banks[i]->size; pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; - ret = zynqmp_pm_request_node(pm_domain_id, - ZYNQMP_PM_CAPABILITY_ACCESS, 0, - ZYNQMP_PM_REQUEST_ACK_BLOCKING); - if (ret < 0) { - dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id); - goto release_tcm_split; + /* + * If TCM information is available in device-tree then + * in that case, pm domain framework will power on/off TCM. + * In that case pm_domain_id is set to 0. If hardcode + * bindings from driver is used, then only this driver will + * use pm_domain_id. + */ + if (pm_domain_id) { + ret = zynqmp_pm_request_node(pm_domain_id, + ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret < 0) { + dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id); + goto release_tcm_split; + } } dev_dbg(dev, "TCM carveout split mode %s addr=%llx, da=0x%x, size=0x%lx", @@ -604,7 +613,8 @@ static int add_tcm_carveout_split_mode(struct rproc *rproc) bank_name); if (!rproc_mem) { ret = -ENOMEM; - zynqmp_pm_release_node(pm_domain_id); + if (pm_domain_id) + zynqmp_pm_release_node(pm_domain_id); goto release_tcm_split; } @@ -617,7 +627,8 @@ static int add_tcm_carveout_split_mode(struct rproc *rproc) /* If failed, Turn off all TCM banks turned on before */ for (i--; i >= 0; i--) { pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; - zynqmp_pm_release_node(pm_domain_id); + if (pm_domain_id) + zynqmp_pm_release_node(pm_domain_id); } return ret; } @@ -659,13 +670,16 @@ static int add_tcm_carveout_lockstep_mode(struct rproc *rproc) pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; /* Turn on each TCM bank individually */ - ret = zynqmp_pm_request_node(pm_domain_id, - ZYNQMP_PM_CAPABILITY_ACCESS, 0, - ZYNQMP_PM_REQUEST_ACK_BLOCKING); - if (ret < 0) { - dev_err(dev, "failed to turn on TCM 0x%x", - pm_domain_id); - goto release_tcm_lockstep; + + if (pm_domain_id) { + ret = zynqmp_pm_request_node(pm_domain_id, + ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret < 0) { + dev_err(dev, "failed to turn on TCM 0x%x", + pm_domain_id); + goto release_tcm_lockstep; + } } bank_size = r5_core->tcm_banks[i]->size; @@ -683,7 +697,8 @@ static int add_tcm_carveout_lockstep_mode(struct rproc *rproc) bank_name); if (!rproc_mem) { ret = -ENOMEM; - zynqmp_pm_release_node(pm_domain_id); + if (pm_domain_id) + zynqmp_pm_release_node(pm_domain_id); goto release_tcm_lockstep; } @@ -700,7 +715,8 @@ static int add_tcm_carveout_lockstep_mode(struct rproc *rproc) /* If failed, Turn off all TCM banks turned on before */ for (i--; i >= 0; i--) { pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; - zynqmp_pm_release_node(pm_domain_id); + if (pm_domain_id) + zynqmp_pm_release_node(pm_domain_id); } return ret; } @@ -931,6 +947,8 @@ static int zynqmp_r5_add_pm_domains(struct rproc *rproc) } } + return 0; + fail_add_pm_domains_lockstep: while (--j >= 0) { device_link_del(r5_core->pm_dev_core1_link[j]); @@ -1012,7 +1030,7 @@ static int zynqmp_r5_rproc_unprepare(struct rproc *rproc) for (i = 0; i < r5_core->tcm_bank_count; i++) { pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; - if (zynqmp_pm_release_node(pm_domain_id)) + if (pm_domain_id && zynqmp_pm_release_node(pm_domain_id)) dev_warn(r5_core->dev, "can't turn off TCM bank 0x%x", pm_domain_id); } @@ -1087,6 +1105,83 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev) return ERR_PTR(ret); } +static int zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster *cluster) +{ + struct zynqmp_r5_core *r5_core; + int i, j, tcm_bank_count, ret; + struct platform_device *cpdev; + struct mem_bank_data *tcm; + struct device_node *np; + struct resource *res; + u64 abs_addr, size; + struct device *dev; + + for (i = 0; i < cluster->core_count; i++) { + r5_core = cluster->r5_cores[i]; + dev = r5_core->dev; + np = dev_of_node(dev); + + /* we have address cell 2 and size cell as 2 */ + ret = of_property_count_elems_of_size(np, "reg", + 4 * sizeof(u32)); + if (ret <= 0) { + dev_err(dev, "can't get reg property err %d\n", ret); + return -EINVAL; + } + + tcm_bank_count = ret; + + r5_core->tcm_banks = devm_kcalloc(dev, tcm_bank_count, + sizeof(struct mem_bank_data *), + GFP_KERNEL); + if (!r5_core->tcm_banks) + ret = -ENOMEM; + + r5_core->tcm_bank_count = tcm_bank_count; + for (j = 0; j < tcm_bank_count; j++) { + tcm = devm_kzalloc(dev, sizeof(struct mem_bank_data), + GFP_KERNEL); + if (!tcm) + return -ENOMEM; + + r5_core->tcm_banks[j] = tcm; + + /* get tcm address without translation */ + ret = of_property_read_reg(np, j, &abs_addr, &size); + if (ret) { + dev_err(dev, "failed to get reg property\n"); + return ret; + } + + /* + * remote processor can address only 32 bits + * so convert 64-bits into 32-bits. This will discard + * any unwanted upper 32-bits. + */ + tcm->da = (u32)abs_addr; + tcm->size = (u32)size; + + cpdev = to_platform_device(dev); + res = platform_get_resource(cpdev, IORESOURCE_MEM, j); + if (!res) { + dev_err(dev, "failed to get tcm resource\n"); + return -EINVAL; + } + + tcm->addr = (u32)res->start; + tcm->bank_name = (char *)res->name; + res = devm_request_mem_region(dev, tcm->addr, tcm->size, + tcm->bank_name); + if (!res) { + dev_err(dev, "failed to request tcm resource\n"); + return -EINVAL; + } + } + } + + return 0; +} + /** * zynqmp_r5_get_tcm_node() * Ideally this function should parse tcm node and store information @@ -1165,10 +1260,19 @@ static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster, struct zynqmp_r5_core *r5_core; int ret, i; - ret = zynqmp_r5_get_tcm_node(cluster); - if (ret < 0) { - dev_err(dev, "can't get tcm node, err %d\n", ret); - return ret; + r5_core = cluster->r5_cores[0]; + if (of_find_property(r5_core->np, "reg", NULL)) { + ret = zynqmp_r5_get_tcm_node_from_dt(cluster); + if (ret) { + dev_err(dev, "can't get tcm node from dt, err %d\n", ret); + return ret; + } + } else { + ret = zynqmp_r5_get_tcm_node(cluster); + if (ret < 0) { + dev_err(dev, "can't get tcm node, err %d\n", ret); + return ret; + } } for (i = 0; i < cluster->core_count; i++) {