From patchwork Wed Nov 15 19:01:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 744397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59C1EC2BB3F for ; Wed, 15 Nov 2023 19:02:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229906AbjKOTCF (ORCPT ); Wed, 15 Nov 2023 14:02:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229661AbjKOTCE (ORCPT ); Wed, 15 Nov 2023 14:02:04 -0500 Received: from mail.bugwerft.de (mail.bugwerft.de [46.23.86.59]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 42E60DC; Wed, 15 Nov 2023 11:02:00 -0800 (PST) Received: from hq-00595.fritz.box (pd95ef485.dip0.t-ipconnect.de [217.94.244.133]) by mail.bugwerft.de (Postfix) with ESMTPSA id 9641B2800D8; Wed, 15 Nov 2023 19:01:58 +0000 (UTC) From: Daniel Mack To: gregkh@linuxfoundation.org, jirislaby@kernel.org, lech.perczak@camlingroup.com, u.kleine-koenig@pengutronix.de Cc: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Mack , Maxim Popov , stable@vger.kernel.org Subject: [PATCH v3] serial: sc16is7xx: address RX timeout interrupt errata Date: Wed, 15 Nov 2023 20:01:44 +0100 Message-ID: <20231115190144.740291-1-daniel@zonque.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org This device has a silicon bug that makes it report a timeout interrupt but no data in the FIFO. The datasheet states the following in the errata section 18.1.4: "If the host reads the receive FIFO at the same time as a time-out interrupt condition happens, the host might read 0xCC (time-out) in the Interrupt Indication Register (IIR), but bit 0 of the Line Status Register (LSR) is not set (means there is no data in the receive FIFO)." The errata doesn't explicitly mention that, but tests have shown that the RXLVL register is equally affected. This bug has hit us on production units and when it does, sc16is7xx_irq() would spin forever because sc16is7xx_port_irq() keeps seeing an interrupt in the IIR register that is not cleared because the driver does not call into sc16is7xx_handle_rx() unless the RXLVL register reports at least one byte in the FIFO. Fix this by always reading one byte when this condition is detected in order to clear the interrupt. Signed-off-by: Daniel Mack Co-Developed-by: Maxim Popov Cc: stable@vger.kernel.org --- v3: re-added the additional Co-Developed-by and stable@ tags v2: reworded the commit log a bit for more context. drivers/tty/serial/sc16is7xx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 289ca7d4e566..76f76e510ed1 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -765,6 +765,18 @@ static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) case SC16IS7XX_IIR_RTOI_SRC: case SC16IS7XX_IIR_XOFFI_SRC: rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); + + /* + * There is a silicon bug that makes the chip report a + * time-out interrupt but no data in the FIFO. This is + * described in errata section 18.1.4. + * + * When this happens, read one byte from the FIFO to + * clear the interrupt. + */ + if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) + rxlen = 1; + if (rxlen) sc16is7xx_handle_rx(port, rxlen, iir); break;