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Wed, 15 Nov 2023 18:58:53 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20231115095853epcas2p3e808e27c4a5c611e7e1965f4c968cbcc~Xw36x_PKA0132301323epcas2p3S; Wed, 15 Nov 2023 09:58:53 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20231115095853epsmtrp2c7196be844e6e8ffebdc09b9161c05e1~Xw36w8hL32585825858epsmtrp2o; Wed, 15 Nov 2023 09:58:53 +0000 (GMT) X-AuditID: b6c32a45-9e590a8000002716-f7-6554965d5774 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 02.F6.08755.D5694556; Wed, 15 Nov 2023 18:58:53 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095852epsmtip2ce7770628a2aa20bbf5fe5f2b8186299~Xw36RnLWe2715627156epsmtip2N; Wed, 15 Nov 2023 09:58:52 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 01/12] dt-bindings: soc: samsung: exynos-sysreg: add exynosautov920 sysreg Date: Wed, 15 Nov 2023 18:55:57 +0900 Message-ID: <20231115095609.39883-2-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPJsWRmVeSWpSXmKPExsWy7bCmhW7stJBUg3VTNCwezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xrr5GQWn2CsONu1mamBsYOti5OCQEDCR6Nga2sXI xSEksINR4vLdz0wQzidGifbmhSxdjJxAzjdGiX+LkkFskIYluz6xQBTtZZRYdXUTI4TzkVHi yc7dzCBVbALaEt/XL2YFsUUE7jNLvG6rBiliFmhnkpj37SXYWGGBeImlk+6zg9gsAqoSV068 ZgS5iVfAVqJpjwLENnmJPYu+M4GEOQXsJFrPa4GEeQUEJU7OfAI2hRmopHnrbGaQ8RICVzgk jk9+xQ7xmovEnnMJEGOEJV4d38IOYUtJfH63lw3CzpZon/6HFcKukLi4YTZU3Fhi1rN2sGuY BTQl1u/Sh5ioLHHkFtRWPomOw3+hFvFKdLQJQTSqSdyfeg5qiIzEpCMrmSBsD4l/q6dBg3Yi o8SKDatZJjAqzELyzCwkz8xCWLyAkXkVo1hqQXFuemqxUYEhPHKT83M3MYJTtpbrDsbJbz/o HWJk4mA8xCjBwawkwmsuF5IqxJuSWFmVWpQfX1Sak1p8iNEUGNATmaVEk/OBWSOvJN7QxNLA xMzM0NzI1MBcSZz3XuvcFCGB9MSS1OzU1ILUIpg+Jg5OqQamRY/EJBaxLdx485/27YuS6oL6 364ysdt8U7fdOqO7NUPd/O3/xmkb1wb/Yl7oceXSpMrgq+rBfq5rPmg/XPOk7E358yKhj3sY HnJVmT27erf83sJYy/icZouj/1s+r7js/lVGWlSqRETHsHjG17geiyivPQcvHAupXVeQu0ff +jbvl7V3jV+vSOYuOdJU/6h/s8HmgOJdGzp71WKTP0jJHHfT+ynSL5f18hqDjswJqV0Bup09 HMtKp8dH/P27vFTY0/32+5K2VuMZN/n+ei17vU085QDfhvpVbakM70WO7tkx+fLmmWv1jp26 Ej3xApPv/89BztP9ZP76xu24L3LxQOUPvet3ryfxdOwU0hD4pMRSnJFoqMVcVJwIAM9VbOti BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42LZdlhJXjd2WkiqwdyZrBYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJWxbn5GwSn2ioNNu5kaGBvY uhg5OSQETCSW7PrE0sXIxSEksJtR4sLRJiaIhIzE8md9UEXCEvdbjrBCFL1nlJjfuRMswSag LfF9/WKwhIjAc2aJs38eMYMkmAX6mSSub0oAsYUFYiWWnmtlBLFZBFQlrpx4DWRzcPAK2Eo0 7VGAWCAvsWfRdyaQMKeAnUTreS2QsBBQRevuH2ATeQUEJU7OfMICMV1eonnrbOYJjAKzkKRm IUktYGRaxSiZWlCcm55bbFhgmJdarlecmFtcmpeul5yfu4kRHGNamjsYt6/6oHeIkYmD8RCj BAezkgivuVxIqhBvSmJlVWpRfnxRaU5q8SFGaQ4WJXFe8Re9KUIC6YklqdmpqQWpRTBZJg5O qQamrLMS318qHHly7LeUg3rxmw6jE//02FanW6f83Lvb4yrDAo47k6NDEnVzE3X8/y66IB/o 43dk8Zzfb5XdHmdePjFnz/Hn+Z/iK/d/7oyPKU3amX9/y78D8Wqm60pFlr49YnHhXfia1gUl wcKnn7T5H3/X+kXnjd2zaf+k/WU2lnBG97NEb5gxg3PH7LtB156Fvr4bdjY9+cNEI6Xdl80e CKfEnC5ttb2it7Xx62XznvXdXBe/Kuj1qIduviYnMb2o+97/Vr+wKWL7N8iYNvL/k4vicHkm 0l56d36jwVEHAd3uPfZFpTaC28+82f75ov6LD4/XLWOcMmvm4XW83Zfn7FzJ9LrhKP/qiyuf zJm2IVaJpTgj0VCLuag4EQANvdx5IAMAAA== X-CMS-MailID: 20231115095853epcas2p3e808e27c4a5c611e7e1965f4c968cbcc X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095853epcas2p3e808e27c4a5c611e7e1965f4c968cbcc References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add compatible for ExynosAutov920 sysreg controllers. Signed-off-by: Jaewon Kim --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 163e912e9cad..2de4301a467d 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -50,6 +50,11 @@ properties: - samsung,exynosautov9-peric1-sysreg - const: samsung,exynosautov9-sysreg - const: syscon + - items: + - enum: + - samsung,exynosautov920-peric0-sysreg + - samsung,exynosautov920-peric1-sysreg + - const: syscon reg: maxItems: 1 From patchwork Wed Nov 15 09:55:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744282 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A61ACC2FD for ; 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Wed, 15 Nov 2023 18:58:53 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095853epsmtip2522ff670d63eb152b9ff8433536c4976~Xw36km-312498624986epsmtip2e; Wed, 15 Nov 2023 09:58:53 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 02/12] dt-bindings: soc: samsung: exynos-pmu: add exynosautov920 compatible Date: Wed, 15 Nov 2023 18:55:58 +0900 Message-ID: <20231115095609.39883-3-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLJsWRmVeSWpSXmKPExsWy7bCmmW7stJBUg60PbCwezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xp6X0xgLrrFVNHZ7NTCuYe1i5OSQEDCRuPOiB8wW EtjBKLHlQngXIxeQ/YlRYvqiB4wQCSDn7Fk2mIYLu/eyQBTtZJRoXNTOBlH0kVHix052EJtN QFvi+/rFYFNFBO4zS7xuqwZpYBZoZ5KY9+0lC0hCWCBB4sq+/UxdjBwcLAKqEuv+JYKEeQVs JXa+WA61TF5iz6LvYCWcAnYSree1IEoEJU7OfAI2hRmopHnrbGaQ8RICZzgk1j49ygjR6yIx 899LZghbWOLV8S3sELaUxOd3e6HmZ0u0T/8DDYkKiYsbZkPFjSVmPWtnBNnLLKApsX6XPogp IaAsceQW1Fo+iY7Df9khwrwSHW1CEI1qEvennoMaIiMx6chKJogSD4npc/wh4TSRUaLhe+EE RoVZSH6ZheSXWQhrFzAyr2IUSy0ozk1PLTYqMIFHbXJ+7iZGcLrW8tjBOPvtB71DjEwcjIcY JTiYlUR4zeVCUoV4UxIrq1KL8uOLSnNSiw8xmgLDeSKzlGhyPjBj5JXEG5pYGpiYmRmaG5ka mCuJ895rnZsiJJCeWJKanZpakFoE08fEwSnVwBQ79fVh69UFDaU/Xz6zfHzjwQyB9Bs89d8r 5VjdGSpVxUx8mFovan+UKq3U+K0xV5iJu+CgbC7/lZnhYvuutJ13vOAh/ddta26S2KuHlZN3 vLXnFA1u53m3eE1nkNkUU8YHmx+fbU0LSpkkdeH3+jVBYeZFt10/PbHX/ru94kRZweydEzfZ lc0Utcpfo+13f73fsYVMhw62RX+62sykXPpn5+mZdxbu+2r9bPKjlAlLDm8/VvNWL/fNw7hX 7Dyq7YtFFgnevcd91r6+6X3o7Ge3pu5fIZv6cU/ZvgPf5md/3nG2yG/Xl54GwR8Ne23/OvNl bSlmX8bO+tHclfnY+fNS5nETbfvyVns8EEjy/e2nxFKckWioxVxUnAgAOuctDmAEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkkeLIzCtJLcpLzFFi42LZdlhJXjd2Wkiqweur4hYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJWx5+U0xoJrbBWN3V4NjGtY uxg5OSQETCQu7N7L0sXIxSEksJ1R4vuxjcwQCRmJ5c/62CBsYYn7LUdYIYreM0psef+CCSTB JqAt8X39YrCEiMBzZomzfx6BdTML9DNJXN+UAGILC8RJNFyZwt7FyMHBIqAqse5fIkiYV8BW YueL5VAL5CX2LPrOBFLCKWAn0XpeCyQsBFTSuvsHM0S5oMTJmU9YIKbLSzRvnc08gVFgFpLU LCSpBYxMqxhFUwuKc9NzkwsM9YoTc4tL89L1kvNzNzGCY0sraAfjsvV/9Q4xMnEwHmKU4GBW EuE1lwtJFeJNSaysSi3Kjy8qzUktPsQozcGiJM6rnNOZIiSQnliSmp2aWpBaBJNl4uCUamBS jLpZbbjkl6aX/Ium+enBH2z/3Dn/wlun5u+EuTPn97PdP71TTnXeLv21/jWHJRWv5N3yvdy4 UTLzl2RfQYDzrv23Cl081rMcOvb0Qk7IC+9H/kn5D5q7jlU8eHt75fXDH0zY5jm0C/IoV1mG xC3aPNNGvf30qUOLrULLrSZLaMpdmcC5Wa/ZcPlEtqm3py45co2twEIwQcpJSYzza2zeuUXP 30QWnKo84n3aO37LzO92G15t4CnbnqJ4/W/VV+OV6yNe6Uma/DJc86Hj1hlN5dR8ft7ESYrZ CT4XL3YdzLKLkOK5FPWgzLbu7K2N1VPPTFujk6Zz19nsSzObRbIn4ynzdZynuEUL3We8SnJQ YinOSDTUYi4qTgQAaZ8qVhwDAAA= X-CMS-MailID: 20231115095853epcas2p45e2c5fe8ac771555a25b434cf86895fd X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095853epcas2p45e2c5fe8ac771555a25b434cf86895fd References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add samsung,exynosautov920-pmu compatible for representing pmu of ExynosAutov920 SoC. Signed-off-by: Jaewon Kim --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 6492e92586d9..28e2cb50d85e 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -52,6 +52,7 @@ properties: - enum: - samsung,exynos7885-pmu - samsung,exynosautov9-pmu + - samsung,exynosautov920-pmu - const: samsung,exynos7-pmu - const: syscon - items: From patchwork Wed Nov 15 09:55:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744515 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B0DCD51E for ; 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Wed, 15 Nov 2023 18:58:53 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095853epsmtip289e0b6023a1c306598b74502f86d8e78~Xw3629IuF2749427494epsmtip2d; Wed, 15 Nov 2023 09:58:53 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 03/12] dt-bindings: soc: samsung: usi: add exynosautov920-usi compatible Date: Wed, 15 Nov 2023 18:55:59 +0900 Message-ID: <20231115095609.39883-4-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBJsWRmVeSWpSXmKPExsWy7bCmuW78tJBUg7VPGS0ezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2Rs/uC2wF69krNj6aw9TA+Jm1i5GTQ0LARGL55C1A NheHkMAeRomb73dAOZ8YJZbuPMUG4XxjlFg57RkbTMvOOc8ZIRJ7GSVuHd8LVfWRUWL2gdeM IFVsAtoS39cvBlsiInCfWeJ1WzVIEbNAO5PEvG8vWUASwgKxEjc6e8GKWARUJR5d28UOYvMK 2Ep86nrBCLFOXmLPou9MXYwcHJwCdhKt57UgSgQlTs58AjaGGaikeetsZpD5EgJXOCT2Nbxk guh1kTiw+hgzhC0s8er4FnYIW0riZX8blJ0t0T79DzQ0KiQubpgN9aaxxKxn7Ywge5kFNCXW 79IHMSUElCWO3IJayyfRcfgvO0SYV6KjTQiiUU3i/tRzUENkJCYdWQl1jIfE13mroOE2kVFi 3a8t7BMYFWYh+WYWkm9mISxewMi8ilEqtaA4Nz012ajAUDcvtRwey8n5uZsYwUlcy3cH4+v1 f/UOMTJxMB5ilOBgVhLhNZcLSRXiTUmsrEotyo8vKs1JLT7EaAoM7onMUqLJ+cA8klcSb2hi aWBiZmZobmRqYK4kznuvdW6KkEB6YklqdmpqQWoRTB8TB6dUA5Nv5rpb3/+9KjSyZHvQIrhv K8v2gH5/numvrNYu1Pp0WvJEzPbdZ4XkF33eYfC+32AZ5701/bZb+4oWRcw9f7kvbvWTJLGJ UseEPUXCvnEmtrfM6jSv6p0y9YfwXbEXT/647//Wvd5UYUqjabRP4s+kia/fJX07yb36+4lG FnbWE/fvm2ya0PRm7+fXlrKOhz7pMEe8/eZ9LmafBEeJP4N63cv01Z869hzzdVnLu+ZvF8dJ 9lzeN++uhbnLTfx+YMucL+nKMu/X3LcQf1k0farRF43es7c/aG7esvp70VYdYwfRnvCTKxfd KmQ7fvHd36CfcV7X3D/uslozWaaAIejmA46F9fqRSW8+7w3RZjhuqMRSnJFoqMVcVJwIADXA 2dlrBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42LZdlhJXjd2Wkiqwa9ebYsH87axWazZe47J Yv6Rc6wWzYvXs1nsaDjCavFurozF3tdb2S2m/FnOZLHp8TVWi83z/zBaXN41h83i7t1VjBYz zu9jsjizuJfdonXvEXaLw2/aWS1+7prHYrFqF1Dd7YmTGR2EPXbOusvusWlVJ5vHnWt72Dz2 z13D7rF5Sb1H/18Dj74tqxg9Pm+SC+CI4rJJSc3JLEst0rdL4Mro2X2BrWA9e8XGR3OYGhg/ s3YxcnJICJhI7JzznLGLkYtDSGA3o8S1mRvYIRIyEsuf9bFB2MIS91uOsEIUvWeUWHLhLQtI gk1AW+L7+sVgCRGB58wSZ/88YgZJMAv0M0lc35QAYgsLREs0fF/JBGKzCKhKPLq2C2wDr4Ct xKeuF4wQG+Ql9iz6DlTDwcEpYCfRel4LJCwEVNK6+wczRLmgxMmZT1ggxstLNG+dzTyBUWAW ktQsJKkFjEyrGCVTC4pz03OTDQsM81LL9YoTc4tL89L1kvNzNzGC40xLYwfjvfn/9A4xMnEw HmKU4GBWEuE1lwtJFeJNSaysSi3Kjy8qzUktPsQozcGiJM5rOGN2ipBAemJJanZqakFqEUyW iYNTqoEpadH3S7+4X6k3WnLdmMpYuPGS6Sa1p/cXvzy3J77hcCyLxNvbBSwLJh/8nPMmr3vN wocGHw1qGj6x/jzfu6Jxwcrfe8OizVLO/Hll9+CkWZz55kiPGZL2elP6th2Kmmcd3cTvrXzs xszCTLmGoxxrfwRM0y95pHLpq+a0kmYdOS4WNm6P/Ye1RC9du5EqJ7v32yHnwAuLMoMXdl35 dFBY/mhnsnHfYs4stw9CpVkTAlgWpq76vTtwRfurdd46Nh8TjQ71brf89mLH58MvP39RLp58 eH//PxO1BTkV35OubPFoz/lvlvL/kEW2VEal8sfyi61t5yf12/1+eMyK54nyxTd6BvO95GdI NkVfkHZ3V2Ipzkg01GIuKk4EAGo9A80iAwAA X-CMS-MailID: 20231115095853epcas2p38f9fbdd7bbbb940afa2042cd5ee9d237 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095853epcas2p38f9fbdd7bbbb940afa2042cd5ee9d237 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add samsung,exynosautov920-usi dedicated compatible for representing USI of ExynosAutoV920 SoC. Signed-off-by: Jaewon Kim --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 5b7ab69546c4..61be1f2ddbe7 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -24,7 +24,9 @@ properties: compatible: oneOf: - items: - - const: samsung,exynosautov9-usi + - enum: + - samsung,exynosautov9-usi + - samsung,exynosautov920-usi - const: samsung,exynos850-usi - enum: - samsung,exynos850-usi From patchwork Wed Nov 15 09:56:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744283 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F11C9479 for ; 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Wed, 15 Nov 2023 18:58:53 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095853epsmtip27aef11efdb45437ea5d29a117030e297~Xw37KDj412498224982epsmtip2Q; Wed, 15 Nov 2023 09:58:53 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 04/12] dt-bindings: serial: samsung: add exynosautov920-uart compatible Date: Wed, 15 Nov 2023 18:56:00 +0900 Message-ID: <20231115095609.39883-5-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEJsWRmVeSWpSXmKPExsWy7bCmqW7ctJBUgz0P5SwezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xu6rvxkLtrFXXH37i7mB8StrFyMnh4SAicTeJ3NZ uhi5OIQEdjBKPDn3mRXC+cQo8bXxGBuE841R4tb6SYwwLa0HjjFCJPYySrzcPYcJJCEk8JFR Yt/aFBCbTUBb4vv6xWA7RATuM0u8bqsGaWAWaGeSmPftJQtIQlggRqJ/7zMgm4ODRUBV4sPO BJAwr4CtxKLGBUwQy+Ql9iz6zgRSwilgJ9F6XguiRFDi5MwnYFOYgUqat85mBhkvIXCBQ6L5 SR8LRK+LxMGja6D+FJZ4dXwLO4QtJfGyvw3KzpZon/4HqqZC4uKG2WwQtrHErGftjCB7mQU0 Jdbv0gcxJQSUJY7cglrLJ9Fx+C87RJhXoqNNCKJRTeL+1HNQQ2QkJh1ZCfWIh0Tz/B/MkFCb yCjR/PI98wRGhVlIvpmF5JtZCIsXMDKvYhRLLSjOTU8tNiowhMdvcn7uJkZw4tZy3cE4+e0H vUOMTByMhxglOJiVRHjN5UJShXhTEiurUovy44tKc1KLDzGaAkN6IrOUaHI+MHfklcQbmlga mJiZGZobmRqYK4nz3mudmyIkkJ5YkpqdmlqQWgTTx8TBKdXAJNjFWPfn/9S552smGU5jNLQ7 3rU0WdbcWUIxPO/as21sifKTvsb+3h8/63Rb62oF6Uqh2b9r6sq6+HUOZDEp+Ox9o6S+6Jzj SvtTksXusUlf9i2NVJkh8NX28FO3C3Wm8nomZ5rkg+I3aKwUOTyjW7LS0pk7QH1/xlVr5vUl nkL/5yolR908FPqmP3fPy+T6z5vyBG6X+Tp2RfFFuP04pdN85+4RpX3rky9kBRbVrTL44Cnc fMnzspD1u09Wp8QnrZ1y/MuR6Uss18+wYf7gFc5z0n7i3LPP3KKunPaKf77SctW1WXGV4f0K igLzbwUcUi8zzzl3oErEvt7ZPUP5B8uP3cV94b/kHt8XtNukxFKckWioxVxUnAgA/q6pdmUE AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42LZdlhJXjduWkiqwb9MiwfztrFZrNl7jsli /pFzrBbNi9ezWexoOMJq8W6ujMXe11vZLab8Wc5ksenxNVaLzfP/MFpc3jWHzeLu3VWMFjPO 72OyOLO4l92ide8RdovDb9pZLX7umsdisWoXUN3tiZMZHYQ9ds66y+6xaVUnm8eda3vYPPbP XcPusXlJvUf/XwOPvi2rGD0+b5IL4IjisklJzcksSy3St0vgyth99TdjwTb2iqtvfzE3MH5l 7WLk5JAQMJFoPXCMEcQWEtjNKNExzxkiLiOx/FkfG4QtLHG/5QhQPRdQzXtGiXnfdrGAJNgE tCW+r18MlhAReM4scfbPI2aQBLNAP5PE9U0JILawQJTE79uLmLoYOThYBFQlPuwEC/MK2Eos alzABLFAXmLPou9gJZwCdhKt57Ug7rGVaN39gxmiXFDi5MwnLBDT5SWat85mnsAoMAtJahaS 1AJGplWMkqkFxbnpucWGBYZ5qeV6xYm5xaV56XrJ+bmbGMERpqW5g3H7qg96hxiZOBgPMUpw MCuJ8JrLhaQK8aYkVlalFuXHF5XmpBYfYpTmYFES5xV/0ZsiJJCeWJKanZpakFoEk2Xi4JRq YJo9SyOAzeMgt7/9pcnTOK9s3j3pNr+/7a9PuQvdZr7yMFQ+c1cvYHuiw6aD17Zv2Mih4PXB VXKJ8eR2ufWaHouvqVnMfbri9ib2ZBuJL/OeukUdUd+xnSX6XdyOX8eeCH1Rr/sr8/Ktybrg IqNfUg9mJD3iYo08dHa3zjOVO9u2sQbPVpwz4/LktTq7jIsaz8YIbjWomsQ9y5Zd5xLLT+EM ry2iehLzLu6cZ6vTXrrR14Djp37MVQmBKV8FjYoNttoph7y2CJi52oM5j2OiUJPLq5eH7si5 zxU8/4FFX3jhmVA5vc3JW/rP6kwxVTPI0C+KMry11aThnNSxnWFX41e6+3j89nisJK5W5v9D OlqJpTgj0VCLuag4EQA2vKKZHwMAAA== X-CMS-MailID: 20231115095854epcas2p2e48229f664c1de554f3ecf7075171b93 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095854epcas2p2e48229f664c1de554f3ecf7075171b93 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add samsung,exynosautov9-uart dedicated compatible for representing uart of ExynosAutov920 SoC. Signed-off-by: Jaewon Kim --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 0d0215b23ab7..e32c1b462836 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -35,7 +35,9 @@ properties: - samsung,exynos7885-uart - const: samsung,exynos5433-uart - items: - - const: samsung,exynosautov9-uart + - enum: + - samsung,exynosautov9-uart + - samsung,exynosautov920-uart - const: samsung,exynos850-uart reg: From patchwork Wed Nov 15 09:56:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744281 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEC4AD29D for ; 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Wed, 15 Nov 2023 18:58:54 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095853epsmtip201b8da7c5249b86482d5b6bd2379b063~Xw37cXBab2713927139epsmtip2f; Wed, 15 Nov 2023 09:58:53 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 05/12] dt-bindings: pwm: samsung: add exynosautov920 compatible Date: Wed, 15 Nov 2023 18:56:01 +0900 Message-ID: <20231115095609.39883-6-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMJsWRmVeSWpSXmKPExsWy7bCmmW78tJBUg4cPRSwezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xqT+sywFV9gqNi59wdbAuJW1i5GTQ0LARGLS3WtA NheHkMAORokXbydCOZ8YJR7d2Q/lfGOU2PiiiR2m5f/02SwQib2MEkv/TGKHcD4ySqxvW8cC UsUmoC3xff1isCUiAveZJV63VYMUMQu0M0nM+/YSrEhYIETi1+NpYGNZBFQlPi1ZBhTn4OAV sJVo++sOsU1eYs+i70wgYU4BO4nW81ogYV4BQYmTM5+ATWEGKmneOpsZZLyEwBMOidsrWlgg el0kXm2aCmULS7w6vgXqAymJl/1tUHa2RPv0P9DAqJC4uGE2G4RtLDHrWTsjyF5mAU2J9bv0 QUwJAWWJI7eg1vJJdBz+yw4R5pXoaBOCaFSTuD/1HNQQGYlJR1YyQdgeEo0P1jFDQmoio8TE /jUsExgVZiH5ZhaSb2YhLF7AyLyKUSy1oDg3PbXYqMAYHsHJ+bmbGMGpW8t9B+OMtx/0DjEy cTAeYpTgYFYS4TWXC0kV4k1JrKxKLcqPLyrNSS0+xGgKDOmJzFKiyfnA7JFXEm9oYmlgYmZm aG5kamCuJM57r3VuipBAemJJanZqakFqEUwfEwenVAOTjsCKb97vczfeFpcQe81fo2FY8Haa X2fL1Mv7JoeJLGENmPTkNcOd7kVL3BcHPlt4fV9FU9k8L8cFfYsPyGa9ecvRql+Vz3s8Z1WE IcfhZzqODM1Tfu24fTNBO47/zqfCzo+ulR857jw7fPHGl3aWS69WRCQ/tm1V/3dwKTfDZK59 gWv19D5tzvSZ95Xt+OMMU7cQhYrlJqt2rbRfz7j9yPPPJRapKu1S9VLNRRO2661oW+rhGbn/ 9EeRtSLms+8tPPX247ltz/e0aPCvqe6vVKtaynz3xs9H9bfyf6xUyAqNWmnPMoXD7PU1PYuY sLCvTZFCbd0v39TfPdnKHZpb/eCb0VrZj4cSrH7LPVnFqsRSnJFoqMVcVJwIAOtCSMhmBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCIsWRmVeSWpSXmKPExsWy7bCSvG7ctJBUgwWXhC0ezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjissmJTUnsyy1SN8ugStjUv9ZloIrbBUbl75ga2Dc ytrFyMkhIWAi8X/6bJYuRi4OIYHdjBInJ55jg0jISCx/1gdlC0vcbznCClH0nlHifuM/JpAE m4C2xPf1i8ESIgLPmSXO/nnEDJJgFuhnkri+KQHEFhYIkvj4Yxk7iM0ioCrxackyoHUcHLwC thJtf90hFshL7Fn0nQkkzClgJ9F6XgskLARU0br7B9hEXgFBiZMzn4B1MguoS6yfJwSxSF6i eets5gmMgrOQVM1CqJqFpGoBI/MqRsnUguLc9NxiwwKjvNRyveLE3OLSvHS95PzcTYzgiNTS 2sG4Z9UHvUOMTByMhxglOJiVRHjN5UJShXhTEiurUovy44tKc1KLDzFKc7AoifN+e92bIiSQ nliSmp2aWpBaBJNl4uCUamAyMt6devMpT0rknKviWZn3xLZfui41tdsiw/s+u3llxu3TkQcC Npvoy+kVs8WHLrZ0f9/2tCC93N+6jHf6da5LebmKL6a1idcJ7fl5+NkVybudG2/vNF4c+XWV xcYKbvkMjhuTZ7XMKJq64UiB+AKNrv9/319wklodofvuefFK/blGS+5/10zhP1hx4HHw+taP G07WzZ5Tt7fnTaHXzovhJrUWnmcset1zb3oF/axkEQ6VTd+bKBcZOrWLhaFK6ci0yzwt08// 0LSs/9yw46B+8Flx/cgdHKofHeomCTR2333uaXWzsemlkbf9BnuWtHzf8rNCqVuXXD9XHlt0 +LWe6xq+tMyjnCEiHOtbDiixFGckGmoxFxUnAgBngwBsNwMAAA== X-CMS-MailID: 20231115095854epcas2p42af0a20bcc4fb98aee818c7b44d77c31 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095854epcas2p42af0a20bcc4fb98aee818c7b44d77c31 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add samsung,exynosautov920-pwm compatible string to binding document. Signed-off-by: Jaewon Kim Acked-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/pwm-samsung.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index 89a3875cb50a..16de6434693b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -32,6 +32,7 @@ properties: - samsung,exynos5433-pwm - samsung,exynos7-pwm - samsung,exynosautov9-pwm + - samsung,exynosautov920-pwm - const: samsung,exynos4210-pwm reg: From patchwork Wed Nov 15 09:56:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744517 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3CEAD516 for ; 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Wed, 15 Nov 2023 18:58:54 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095854epsmtip2a7108cf51124bbcca52237ddf8587f3e~Xw37uoCkA2332523325epsmtip2i; Wed, 15 Nov 2023 09:58:54 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 06/12] dt-bindings: pinctrl: samsung: add exynosautov920 binding Date: Wed, 15 Nov 2023 18:56:02 +0900 Message-ID: <20231115095609.39883-7-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEJsWRmVeSWpSXmKPExsWy7bCmqW78tJBUgw8trBYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARlW2TkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhr aGlhrqSQl5ibaqvk4hOg65aZA/SOkkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKbUgJafA vECvODG3uDQvXS8vtcTK0MDAyBSoMCE7492RdvaCOXwVEz9fYm5g3M/dxcjJISFgIrF+8X+2 LkYuDiGBHYwSXxbdYodwPjFKLDv9mBnOWfzsLCtMS8/q+0wgtpDATqCWA2EQRR8ZJW5cf8QC kmAT0Jb4vn4xWIOIwH1middt1SBFzALtTBLzvr0EKuLgEBYIlej9Uw1SwyKgKtGx+gAbiM0r YCvROmMRO8QyeYk9i74zgZRzCthJtJ7XgigRlDg58wnYKmagkuats8EOlRC4wCHxYutZJohe F4nbP45A2cISr45vgZopJfGyvw3KzpZon/4H6rEKiYsbZrNB2MYSs561M4LsZRbQlFi/Sx/E lBBQljhyC2otn0TH4b/sEGFeiY42IYhGNYn7U89BDZGRmHRkJdQBHhIrzu5mgoTUREaJvdse M05gVJiF5JtZSL6ZhbB4ASPzKkax1ILi3PTUYqMCE3j8JufnbmIEJ24tjx2Ms99+0DvEyMTB eIhRgoNZSYTXXC4kVYg3JbGyKrUoP76oNCe1+BCjKTCoJzJLiSbnA3NHXkm8oYmlgYmZmaG5 kamBuZI4773WuSlCAumJJanZqakFqUUwfUwcnFINTNoes6XzjwdViy5ZUNi15PvfeJGI/pNu jBXeG8R+9m3aeS2Eq9K9yYCzyPWZdczdp/vtco+9XLhkcop7+yedZ1vfXZMItjm89VPbDHND XkW/l7kZPWyGC0+EVnCGGhvb7K6qvbPZoSz5XOT1u/M+brivx/Dz3swqp9Drqd2TY7T5qu77 KT6a+aZc/mab889qy1af23aRJq82Tvllta6i+dT0ntVvvP+8XzTDPl1Q4Ky+2NHZJr5HLu9+ FuuyvEc7Y9vk9V8UHH9Hq5hOuWXk/3LtglO5yr/ymhfHLOX5+vBL259T5WFZIitnyU3dc/dc m/oPid8l3sqPni4y4N5+J2TiM666GMl7Eg2BhtKNt5RYijMSDbWYi4oTAQsX7TVlBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42LZdlhJXjduWkiqQXODqsWDedvYLNbsPcdk Mf/IOVaL5sXr2Sx2NBxhtXg3V8Zi7+ut7BZT/ixnstj0+Bqrxeb5fxgtLu+aw2Zx9+4qRosZ 5/cxWZxZ3Mtu0br3CLvF4TftrBY/d81jsVi1C6ju9sTJjA7CHjtn3WX32LSqk83jzrU9bB77 565h99i8pN6j/6+BR9+WVYwenzfJBXBEcdmkpOZklqUW6dslcGW8O9LOXjCHr2Li50vMDYz7 ubsYOTkkBEwkelbfZ+pi5OIQEtjOKNH74gcrREJGYvmzPjYIW1jifssRVoii94wSC+7eZAdJ sAloS3xfvxgsISLwnFni7J9HzCAJZoF+JonrmxJAbGGBYImn06aCTWURUJXoWH0AbCqvgK1E 64xF7BAb5CX2LPoOdAYHB6eAnUTreS2QsBBIye4fzBDlghInZz5hgRgvL9G8dTbzBEaBWUhS s5CkFjAyrWIUTS0ozk3PTS4w1CtOzC0uzUvXS87P3cQIji+toB2My9b/1TvEyMTBeIhRgoNZ SYTXXC4kVYg3JbGyKrUoP76oNCe1+BCjNAeLkjivck5nipBAemJJanZqakFqEUyWiYNTqoGp /YJRyL+3C+8eV/V0/il54oXg8aUufCfzp98r+8Tbs0mh+Pnvryeb9/Bmy4W9zj41aX/QnL23 Q6puPt8ZzXBAXvAd+5HAO9OCziy1fPt0zaP/nzfLHK8UPW+7Q1BiT6F++JM71vubOj77rjl9 b9r7i5+iPy8JXfXmhkPKUcl8seXTkpQ8xUW5T0+7xfvDINlSp/Fyxo/Jaza2nP9S6v/gjqNy 6f4TX/bO4Rb49J/Z+MQ/fi73fTW8ZTbP99hpT3PaGME2O+2w0M13V4/0a/hfWy62MfKeVkCm 3qL98e+fLr+afGheW/itr7Vet8RdRV6ce/nS0uhmw0bb+89OBdUaZEgul10rdWDilJOqHnee +T1UYinOSDTUYi4qTgQAc7lY6R4DAAA= X-CMS-MailID: 20231115095854epcas2p457e0eedcd0b4a001eba8fba012f73920 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095854epcas2p457e0eedcd0b4a001eba8fba012f73920 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add compatible string for exynosautov920 pin controller. Signed-off-by: Jaewon Kim --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 2 ++ Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 1c07af24d6cf..1b75abebb953 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -38,6 +38,7 @@ properties: - samsung,exynos7-wakeup-eint - samsung,exynos850-wakeup-eint - samsung,exynosautov9-wakeup-eint + - samsung,exynosautov920-wakeup-eint - items: - enum: - samsung,exynos5433-wakeup-eint @@ -105,6 +106,7 @@ allOf: enum: - samsung,exynos850-wakeup-eint - samsung,exynosautov9-wakeup-eint + - samsung,exynosautov920-wakeup-eint then: properties: interrupts: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 7509dc36af93..9f04a0c76403 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -53,6 +53,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynosautov9-pinctrl + - samsung,exynosautov920-pinctrl - tesla,fsd-pinctrl interrupts: From patchwork Wed Nov 15 09:56:03 2023 Content-Type: text/plain; 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Wed, 15 Nov 2023 09:58:55 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20231115095855epsmtrp1318f70161c222803c4f679b79950d8e6~Xw38ZTOz-2856328563epsmtrp1N; Wed, 15 Nov 2023 09:58:55 +0000 (GMT) X-AuditID: b6c32a4d-9f7ff70000004a32-a5-6554965f2ef3 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 2C.B2.07368.E5694556; Wed, 15 Nov 2023 18:58:54 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095854epsmtip2ae1ea63cad25751c01692d17dd63ba66~Xw37-7N3p2749427494epsmtip2e; Wed, 15 Nov 2023 09:58:54 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 07/12] dt-bindings: arm: samsung: Document exynosautov920 SADK board binding Date: Wed, 15 Nov 2023 18:56:03 +0900 Message-ID: <20231115095609.39883-8-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKJsWRmVeSWpSXmKPExsWy7bCmhW78tJBUg6NXRS0ezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xq6GM4wFH9krTnyaxtzAuJyti5GTQ0LAROLy0x1A NheHkMAeRon5F38yQzifGCW2Pe1ihXC+MUpM/vSeqYuRA6xlxn9ukG4hgb2MEovvO0LUfGSU OHNqCytIgk1AW+L7+sVgtojAfWaJ123VIEXMAu1MEvO+vWQBGSQskChxaLUSSA2LgKrElLbl LCA2r4CtRM/+CewQ58lL7Fn0HWwvp4CdROt5LYgSQYmTM5+AlTMDlTRvnQ12tITADQ6JNW09 LBC9LhKXr+9nhrCFJV4d3wI1U0riZX8blJ0t0T79DyuEXSFxccNsaLAYS8x61s4IspdZQFNi /S59iNeVJY7cglrLJ9Fx+C87RJhXoqNNCKJRTeL+1HNQQ2QkJh1ZyQRhe0i8e/8dGs4TGSVO LJ7BOIFRYRaSb2Yh+WYWwuIFjMyrGKVSC4pz01OTjQoMdfNSy+FRnJyfu4kRnL61fHcwvl7/ V+8QIxMH4yFGCQ5mJRFec7mQVCHelMTKqtSi/Pii0pzU4kOMpsDgnsgsJZqcD8wgeSXxhiaW BiZmZobmRqYG5krivPda56YICaQnlqRmp6YWpBbB9DFxcEo1MEUcenS/3uty2Uef5AiNr3/2 S/LnVdhanf3778F3PZv2z7KL1dk1efdvZ2t27ZY3uny8jOHfC7PHNQt7eZmSEmc+X/n656/t 3x8/n5T7/HG+W2j0s4yTzKbib/77iR3Za7LIJ0q2drPEV92GySeu/t+jtn5OuG4E342diz2n fnDMbpS4vvaU8qrcZWtuKU24KOET/7/HcRp3fl2d5haNf9ZX3U6vLo4Oq+YP3ZhyuGmvErdY vfejdWI2PQXTXIpNt9zpYj/8+dBe06R2z4YXb07nPPj3chdv96LMA2m3IgJkzViCZnPlbDB4 F5/9O0XT6mVc+O3zyRJLS2cb31Ir3/3yg8a+2btintZM/2mwbr4SS3FGoqEWc1FxIgBfEWx4 aAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42LZdlhJXjduWkiqwc6DFhYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJWxq+EMY8FH9ooTn6YxNzAu Z+ti5OCQEDCRmPGfu4uRi0NIYDejxJuLHUxdjJxAcRmJ5c/62CBsYYn7LUdYQWwhgfeMEgv+ GYPYbALaEt/XL2YFaRYReM4scfbPI2aQBLNAP5PE9U0JILawQLzEvzsXweIsAqoSU9qWs4DY vAK2Ej37J7BDLJCX2LPoOxPIQZwCdhKt57UgdtlKtO7+wQxRLihxcuYTFojx8hLNW2czT2AU mIUkNQtJagEj0ypGydSC4tz03GTDAsO81HK94sTc4tK8dL3k/NxNjOAY09LYwXhv/j+9Q4xM HIyHGCU4mJVEeM3lQlKFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8xrOmJ0iJJCeWJKanZpakFoE k2Xi4JRqYIpqmmvSYW//+My09af+/pL8cfPrXpFL0VfEe7UCL/MtKXXXZznx9eiu6WsS/B4W hYZoGip3P43QPTRL+05HesBi9uo1q7nWnPy2++bqiXtU1YO2L9/5f7PE/lS3BaXRew6/vrr2 6QalY9GmHEuYD3GmRGy5vWji7qX3q1/PPLFBaMuKde/FJDVeWmv482bMfrRxzw+zTK1N3mah cp/PqTf08C9YeSL4ddSysA0hrMnVarJ1kXyxtxUST936bsjnULVhp1T/r5C9pw9s0F/NukGb k4Nnit/pJv9NzzvUGWX/hF4S5WOVyt0SsXCy/k3jnQ+duT/Y+rRU7Xfbua7caKLeHc7JCzNs ZIuP/45/NDtTiaU4I9FQi7moOBEAztoSiCADAAA= X-CMS-MailID: 20231115095855epcas2p41cfb2254bb7f5908612267ab254bb985 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095855epcas2p41cfb2254bb7f5908612267ab254bb985 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add binding for the ExynosAutov920 SADK(Samsung Automotive Development Kit) board. Signed-off-by: Jaewon Kim --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index e3ffd8159ab6..01dcbd8aa703 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -230,6 +230,12 @@ properties: - samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK - const: samsung,exynosautov9 + - description: Exynos Auto v920 based boards + items: + - enum: + - samsung,exynosautov920-sadk # Samsung Exynos Auto v920 SADK + - const: samsung,exynosautov920 + required: - compatible From patchwork Wed Nov 15 09:56:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744518 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5231D2E7 for ; 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Wed, 15 Nov 2023 18:58:55 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095854epsmtip2761568fbbc0d8e5081e00a53702f595e~Xw38Sv_sJ2498624986epsmtip2f; Wed, 15 Nov 2023 09:58:54 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 08/12] dt-bindings: hwinfo: samsung,exynos-chipid: add exynosautov920 compatible Date: Wed, 15 Nov 2023 18:56:04 +0900 Message-ID: <20231115095609.39883-9-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEJsWRmVeSWpSXmKPExsWy7bCmqW78tJBUg1PnzSwezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xrR3jWwFl9gq+tbOYmpg3MraxcjJISFgItH9dzGQ zcUhJLCDUWL/rR5mCOcTo8TOlitsEM43Rolzf28DlXGAtdyfGgUR38soseFZE1THR0aJO7M/ s4DMZRPQlvi+fjHYDhGB+8wSr9uqQYqYBdqZJOZ9ewlWJCyQKrG48z4ziM0ioCpx9dJpJpAN vAK2Ev/PaUDcJy+xZ9F3sDCngJ1E63ktkDCvgKDEyZlPwKYwA5U0b50NdoOEwBUOiZafO6F+ c5GY1/6YBcIWlnh1fAs7hC0l8fndXjYIO1uiffofqPoKiYsbZkPFjSVmPWtnBNnLLKApsX6X PsTvyhJHbkGt5ZPoOPyXHSLMK9HRJgTRqAYMnXNQQ2QkJh1ZyQRhe0j8vfCWHRJSExkl3n18 xD6BUWEWkm9mIflmFsLiBYzMqxjFUguKc9NTi40KTODxm5yfu4kRnLi1PHYwzn77Qe8QIxMH 4yFGCQ5mJRFec7mQVCHelMTKqtSi/Pii0pzU4kOMpsCQnsgsJZqcD8wdeSXxhiaWBiZmZobm RqYG5krivPda56YICaQnlqRmp6YWpBbB9DFxcEo1ME1dtGyS3N1Jz3lP/fbXEtKQUkr44vRV 9BETi0Hv9J0Tl4TJ/6/60/PBXazxW2tOW+iDllurMrnP1B1fa6QouqbB5kD/4YkmW7l9NI+1 l0j6T02TtvlwQ0870GGjtxyzztZgT94uCb8feSFtFcw7Gx9fC9JKPlZ/lmlN46nFpl0b35V+ Dokpee8Wmc4TusCW++53+yBnzp3+nE2XNty2WLtkTkipoVdC5oPvcxlkdl87fkp1bevWK28z Lp77vW/H2hlTH++eqbv/4ZGc1SVvP10Jr3zS3Wbuc/HzKhG3LWbxLJ9uyTy2/ql4OuJmhG+n 20PN2Vsntr5wZc6ZyjW9bV1H5HZFVZFrhyofzvhyarYSS3FGoqEWc1FxIgD1wIELZQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42LZdlhJXjd+WkiqwdQJ/BYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJUx7V0jW8Eltoq+tbOYGhi3 snYxcnBICJhI3J8a1cXIxSEksJtR4sKFD4xdjJxAcRmJ5c/62CBsYYn7LUdYQWwhgfeMEuvO lYHYbALaEt/XL2YFaRYReM4scfbPI2aQBLNAP5PE9U0JILawQLJE296FYENZBFQlrl46zQSy mFfAVuL/OQ2I+fISexZ9BwtzCthJtJ7XglhlK9G6+wfYRF4BQYmTM5+wQEyXl2jeOpt5AqPA LCSpWUhSCxiZVjFKphYU56bnJhsWGOallusVJ+YWl+al6yXn525iBEeYlsYOxnvz/+kdYmTi YDzEKMHBrCTCay4XkirEm5JYWZValB9fVJqTWnyIUZqDRUmc13DG7BQhgfTEktTs1NSC1CKY LBMHp1QDU873BcdmfNuu/VZhX71zVmlCblf8yn27p+7yfF2+47Da6+uWpZPLGMVMWFjScyd5 Nf48dii6q9RScuepe4tMzpb94VUTv7/2cbjA7OjapT6vbB5OSur/brfnd4fdv1P1Eyvu8kqF KoUw9zjorFn75c8SofkZ/tzr5/7jOHvSVa5Dkj3L1P+92+nWBs88xt1CEXr/9Wfyb3Zx1nmS wRl4dg+jsK1/RFINvy8X36qt/WXcHzierzbobdE21srXmRPWteogo8zbgo1BZus1M1Y9NWhq eTJvdYF8ik9mlO3Ji248uUunfQ1a82TVtC027PIVD0/9D61/NmfDH+/gUqeaVybsBW0Tc/Wi 1Q+ttK1QYinOSDTUYi4qTgQAETc4UR8DAAA= X-CMS-MailID: 20231115095855epcas2p3fb87cfdf820587174cc6b4d97e7f1b45 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095855epcas2p3fb87cfdf820587174cc6b4d97e7f1b45 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add "samsung,exynosautov920-chipid" compatible string to binding document. Signed-off-by: Jaewon Kim --- .../devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml index 45f3d468db7c..780ccb5ee9b4 100644 --- a/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/Documentation/devicetree/bindings/hwinfo/samsung,exynos-chipid.yaml @@ -24,6 +24,7 @@ properties: - enum: - samsung,exynos7885-chipid - samsung,exynosautov9-chipid + - samsung,exynosautov920-chipid - const: samsung,exynos850-chipid reg: From patchwork Wed Nov 15 09:56:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744516 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B13BC129 for ; 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Wed, 15 Nov 2023 18:58:55 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095855epsmtip2d68054b42f963ffc029117aa1331aa66~Xw38l_V9N2498224982epsmtip2R; Wed, 15 Nov 2023 09:58:55 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 09/12] soc: samsung: exynos-chipid: add exynosautov920 SoC support Date: Wed, 15 Nov 2023 18:56:05 +0900 Message-ID: <20231115095609.39883-10-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Tf0xTVxTOfa99fUXLnuD0piPSPN0S2YC2K+VJqBlMXBOZIWBmZrJAbd8o FNqmPxarf8jCCkjYGDAVyk+tAa0kkOKPDqg6aGQwhnGyLo7VQpgICA6mKxMhW+mrm/9959zv nO98596Lo1HjGB8v0Jpog1ZRRGIRrGuDu6n4vDOHaOH1GZyabLmGUZ3uMYRq9YyxqVJ7F0a5 Sjxs6klzDOV+fJVDfbPWgVDOaS+b6mldA9S93iaM8vkcgKq/cwOhRu1fciir28OhBhfK2dTz 3hYW5egN8iZq6sB70fJvbT6O3Ok4hcl/8/Zj8pvNnRx5z4WT8up1ofyrKw4gf+rckYUf0aSq aYWKNghorVKnKtDmy8gDObnv5yZJhaJ40R4qmRRoFcW0jNyXmRW/v6AoaIcUfKYoMgdTWQqj kUzcm2rQmU20QK0zmmQkrVcV6ZP1CUZFsdGszU/Q0qYUkVAoTgoS8zRq99kRTO9lHwtUnUNL wCNWJeDikJDAPy71IZUgAo8iXACOfNcdDv4EsG2ql8MEAQBnv7+MvSzx/HweZQ7cADrbJzAm WAZwsmc+xMKIt+FKl529gbcSfhQ+LjuxQUKJcgS2BOZC6tHEYeh9OAw2MIt4E3Y/awwV84i9 8PbiQ5SRi4X951eCQ+E4N5i33oljKFvgcMPvoTZokFJ6tTE0ESTGcThq9YXd7YPrf9s4DI6G 80NXwpgPnz5xh+1oYPnZNTaDj8G73Y3h/LvQNlMONnRRYjfs6k3cgJDYCT2/hmUjYcXgOodJ 82BFWRRT+Bb0nx4LN4mBtZ5LCIPlcG75BYtZVQ2Az13L6NdAYHvFje0VN7b/hdsA6gDbaL2x OJ82ivWi/25YqSt2gtDzjstwgbrFpYQBgOBgAEAcJbfyknccoqN4KoXlOG3Q5RrMRbRxACQF V12D8l9X6oL/Q2vKFUn2CCVSqShZnCRMJrfzHlibVVFEvsJEa2haTxte1iE4l1+CaP6aN4uX EjOaq259OHkxtra2VSI92mNt/2XpQuWjTT/96IkBvHNI3InqizsfcLsix0/H6pXDNUPt5Wmv TaXsyh5RjgSEZsHhVllhwFed5cAPVlt4qZ+vH5HdHj6+f8vymfT0+mj0pqW0QeUMDC3Ezqqq YjJt//yQWTd5/6OyD5oPxvs5hXc/HYVa6Vzax/4vxNzt3ffTM26sODqyV3dxGvodKS9wV8di vqyp752cNv7JacvlVS+pTLXXFx/YFjnRWVL9Rvb1mTTJ9MJiZATRZPF4Cx2rt+am7M/61AOz McTRT8r6N/tbqu4NJlS1WzaP5lUqCX8OemrVl1PhqR3ZRLKMaoUoDjUYFf8CHoXpDGcEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42LZdlhJXjd+WkiqQedMZYsH87axWazZe47J Yv6Rc6wWzYvXs1nsaDjCavFurozF3tdb2S2m/FnOZLHp8TVWi83z/zBaXN41h83i7t1VjBYz zu9jsjizuJfdonXvEXaLw2/aWS1+7prHYrFqF1Dd7YmTGR2EPXbOusvusWlVJ5vHnWt72Dz2 z13D7rF5Sb1H/18Dj74tqxg9Pm+SC+CI4rJJSc3JLEst0rdL4MrYO/0UW8E11opvPQuZGxif s3QxcnJICJhIHLm6iLmLkYtDSGA3o8SvngWsEAkZieXP+tggbGGJ+y1HWCGK3jNKdBx9BpZg E9CW+L5+MVhCROA5s8TZP4+YQRLMAv1MEtc3JYDYwgKhEp3/VjKC2CwCqhIbvswGa+YVsJM4 9vYpM8QGeYk9i74zdTFycHACxVvPa4GEhQRsJVp3/2CGKBeUODnzCQvEeHmJ5q2zmScwCsxC kpqFJLWAkWkVo2RqQXFuem6xYYFRXmq5XnFibnFpXrpecn7uJkZwnGlp7WDcs+qD3iFGJg7G Q4wSHMxKIrzmciGpQrwpiZVVqUX58UWlOanFhxilOViUxHm/ve5NERJITyxJzU5NLUgtgsky cXBKNTDF7m/2+LFo9skdGQxcV1ed1TjyeLrCDK1VovnaEcUh4pkLjENem/o7TWwt1Hrnk3Jy 6/9tFQnZfD3PK7iCX4Zlxice0Fv/8c+fRSWx66Nrg3aEVR2YGeMcu2UC76v9vFOKdU+Zbkz/ FD/n2v03HlVBVy7cW16gwTCd6folA94avoJ8lu/+j6Iq9zdMuT5N4v3Oypbqe3UnfkfPZIva xK1b7inkMkOSbfalh99naru/WnGcSWzrtoYOBtf5p7tbL27NvJuy96pc9K0tVYYLAj7OvxNa NZv7/IfYev7oGdNeO16UfS29oGqFzNKO+UHB19/9qiw3PbhWoq9R9aH3GtkVW07tfR9ptO6Q aeKRvpJ7SizFGYmGWsxFxYkARA2+DSIDAAA= X-CMS-MailID: 20231115095855epcas2p3fe5776db0e15e0427cbe2bd2382644c2 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095855epcas2p3fe5776db0e15e0427cbe2bd2382644c2 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Add EXYNOSAUTOV920 information to soc_ids tables. This SoC product id is "0x0A920000". Signed-off-by: Jaewon Kim --- drivers/soc/samsung/exynos-chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 3fd0f2b84dd3..b1118d37779e 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -59,6 +59,7 @@ static const struct exynos_soc_id { { "EXYNOS7885", 0xE7885000 }, { "EXYNOS850", 0xE3830000 }, { "EXYNOSAUTOV9", 0xAAA80000 }, + { "EXYNOSAUTOV920", 0x0A920000 }, }; static const char *product_id_to_soc_id(unsigned int product_id) From patchwork Wed Nov 15 09:56:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744278 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78359F9F2 for ; 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Wed, 15 Nov 2023 18:58:55 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095855epsmtip2e39232ae7c56787c7afe8b88fcaa15ae~Xw385tfXx2749427494epsmtip2f; Wed, 15 Nov 2023 09:58:55 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 10/12] pinctrl: samsung: add exynosautov920 pinctrl Date: Wed, 15 Nov 2023 18:56:06 +0900 Message-ID: <20231115095609.39883-11-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGJsWRmVeSWpSXmKPExsWy7bCmuW7CtJBUgxOzjCwezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xurnz9gLFsxlrPjzfi1TA+ONZsYuRk4OCQETiVnL njN1MXJxCAnsYJR4NnEtG4TziVHi+eTLrBDON0aJ069PsMC0rGmaANWyl1FiZdNRqJaPjBLz z25iBaliE9CW+L5+MZgtInCfWeJ1WzVIEbNAO5PEvG8vwUYJC7hJ3Jj6ig3EZhFQlVh9eztY A6+AncSns0uYINbJS+xZ9B3I5uDgBIq3nteCKBGUODnzCdgYZqCS5q2zmUHmSwjc4JC4vfgK 1HcuEnMPz4SaIyzx6vgWdghbSuJlfxuUnS3RPv0PK4RdIXFxw2w2CNtYYtazdkaQvcwCmhLr d+mDmBICyhJHbkGt5ZPoOPyXHSLMK9HRJgTRqCZxf+o5qCEyEpOOrIQ6wEOiefJ0aFBNBIbu vU0sExgVZiH5ZhaSb2YhLF7AyLyKUSy1oDg3PbXYqMAIHsfJ+bmbGMEJXMttB+OUtx/0DjEy cTAeYpTgYFYS4TWXC0kV4k1JrKxKLcqPLyrNSS0+xGgKDOqJzFKiyfnAHJJXEm9oYmlgYmZm aG5kamCuJM57r3VuipBAemJJanZqakFqEUwfEwenVANTasbzXQ88czQn25Z9nWN2N6XliMau 5KV3G0wmP1K0dxV7OVuDt/9nl/2U5dYLe2un2E9errNKZ6YVp8HNS3PmZrblzLNO4NrC8tGJ /eUtmTXzF22YLn8s7kjmmYl2+Z7K+rN03VXZ7i3flpz88tzdteHvTlfbSa64s/ovz54a75p3 GU8z1+18lm9ccHjGjPCCR4VWRYVp25NEPyu/SZm5rPSEtH7BrJtrOze0NHJqn6+OmKMaoCmu P0n/6/9fxwSfpUd0uf9c2HW96YpkxNmMr3+iA40SnfccTFxvOL1VeP/Jj2aRkkkH4+7O2Hig u29d4rPr+yNvGG28oN59V53hhKf1dM+duzQXWE4wcAw3VWIpzkg01GIuKk4EAH2T+E5pBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsWy7bCSvG78tJBUg95zphYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJWx+vkz9oIFcxkr/rxfy9TA eKOZsYuRk0NCwERiTdMEpi5GLg4hgd2MEh1vW9khEjISy5/1sUHYwhL3W46wQhS9Z5Q43zOZ FSTBJqAt8X39YrCEiMBzZomzfx4xgySYBfqZJK5vSgCxhQXcJG5MfQU2iUVAVWL17e1gzbwC dhKfzi5hgtggL7Fn0Xcgm4ODEyjeel4LJCwkYCvRuvsHM0S5oMTJmU9YIMbLSzRvnc08gVFg FpLULCSpBYxMqxglUwuKc9Nziw0LDPNSy/WKE3OLS/PS9ZLzczcxgmNNS3MH4/ZVH/QOMTJx MB5ilOBgVhLhNZcLSRXiTUmsrEotyo8vKs1JLT7EKM3BoiTOK/6iN0VIID2xJDU7NbUgtQgm y8TBKdXAlD4rwLN908rEkxtf3sxx3P1dLvr9rk+MOcefOuXNUS0qXqv1y+Lqm9iGH8wzV522 /TCzXz9X1n/te5sDd6a94RBWXHWu9F6dgs2WZ7YLdVczfuPbVX/bZIVWyCcxgRmPOjVu508I rXm0Q0hCK6jSMyjGuWTmouUPlIvP3JvRri89p9dmwq9p20q0hSqefUhn5HaYb7LsSue1MHZu W+Z5mQ+b9Zb9muq5bEKI26Ikw3Nbbpr/X/encenczVFXdJmFv/X0Xlyl4nn93XLZvT6lVxY4 n5++I+h65ER7RrayOXdC/TdUapdOY2PNjTbK/WG7QeKj1+9d/re6yjdmLd3Gs2jxgfyM85f+ vokOtlqsvUOJpTgj0VCLuag4EQB+a0dqJAMAAA== X-CMS-MailID: 20231115095856epcas2p1c3ee85750828bec2ee4ab0adeaeaff28 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095856epcas2p1c3ee85750828bec2ee4ab0adeaeaff28 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> ExynosAutov920 GPIO has a different register structure. In the existing Exynos series, EINT control register enumerated after a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET). However, in ExynosAutov920 SoC, the register that controls EINT belongs to each GPIO group, and each GPIO group has 0x1000 align. This is a structure to protect the GPIO group with S2MPU in VM environment, and will only be applied in ExynosAuto series SoCs. Example) ------------------------------------------------- | original | ExynosAutov920 | |-----------------------------------------------| | 0x0 GPIO_CON | 0x0 GPIO_CON | | 0x4 GPIO_DAT | 0x4 GPIO_DAT | | 0x8 GPIO_PUD | 0x8 GPIO_PUD | | 0xc GPIO_DRV | 0xc GPIO_DRV | | 0x700 EINT_CON | 0x18 EINT_CON | | 0x800 EINT_FLTCON | 0x1c EINT_FLTCON0 | | 0x900 EINT_MASK | 0x20 EINT_FLTCON1 | | 0xa00 EINT_PEND | 0x24 EINT_MASK | | | 0x28 EINT_PEND | ------------------------------------------------- Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by: Jaewon Kim --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.c | 102 ++++++++++++- drivers/pinctrl/samsung/pinctrl-exynos.h | 27 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 5 + drivers/pinctrl/samsung/pinctrl-samsung.h | 13 ++ 5 files changed, 280 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index cb965cf93705..cf86722a70a3 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { .ctrl = fsd_pin_ctrl, .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), }; + +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { + EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), + EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), +}; + +/* pin banks of exynosautov920 pin-controller 1 (AUD) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks1[] = { + EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 2 (HSI0) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks2[] = { + EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24), +}; + +/* pin banks of exynosautov920 pin-controller 3 (HSI1) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks3[] = { + EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 4 (HSI2) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks4[] = { + EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks5[] = { + EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24), +}; + +/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks6[] = { + EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */ +static struct samsung_pin_bank_data exynosautov920_pin_banks7[] = { + EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), +}; + +static const struct samsung_retention_data exynosautov920_retention_data __initconst = { + .regs = NULL, + .nr_regs = 0, + .value = 0, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynosautov920_pin_banks0, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynosautov920_retention_data, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynosautov920_pin_banks1, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1), + }, { + /* pin-controller instance 2 HSI0 data */ + .pin_banks = exynosautov920_pin_banks2, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 HSI1 data */ + .pin_banks = exynosautov920_pin_banks3, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 HSI2 data */ + .pin_banks = exynosautov920_pin_banks4, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 HSI2UFS data */ + .pin_banks = exynosautov920_pin_banks5, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 PERIC0 data */ + .pin_banks = exynosautov920_pin_banks6, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 PERIC1 data */ + .pin_banks = exynosautov920_pin_banks7, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = { + .ctrl = exynosautov920_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 6b58ec84e34b..b1bf44ee09db 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -56,6 +56,9 @@ static void exynos_irq_mask(struct irq_data *irqd) unsigned int mask; unsigned long flags; + if (bank->combine) + reg_mask = bank->mask_offset; + raw_spin_lock_irqsave(&bank->slock, flags); mask = readl(bank->eint_base + reg_mask); @@ -72,6 +75,9 @@ static void exynos_irq_ack(struct irq_data *irqd) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; + if (bank->combine) + reg_pend = bank->pend_offset; + writel(1 << irqd->hwirq, bank->eint_base + reg_pend); } @@ -95,6 +101,9 @@ static void exynos_irq_unmask(struct irq_data *irqd) if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) exynos_irq_ack(irqd); + if (bank->combine) + reg_mask = bank->mask_offset; + raw_spin_lock_irqsave(&bank->slock, flags); mask = readl(bank->eint_base + reg_mask); @@ -221,6 +230,22 @@ static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = { /* eint_wake_mask_value not used */ }; +static const struct exynos_irq_chip exynosautov920_gpio_irq_chip __initconst = { + .chip = { + .name = "exynosautov920_gpio_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_con = 0, + .eint_mask = 0, + .eint_pend = 0, + /* eint_wake_mask_value not used */ +}; + static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { @@ -247,7 +272,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) unsigned int svc, group, pin; int ret; - svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); + if (bank->combine) + svc = readl(bank->eint_base + EXYNOSAUTOV920_SVC_OFFSET); + else + svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); group = EXYNOS_SVC_GROUP(svc); pin = svc & EXYNOS_SVC_NUM_MASK; @@ -297,8 +325,12 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) if (bank->eint_type != EINT_TYPE_GPIO) continue; - bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, - sizeof(*bank->irq_chip), GFP_KERNEL); + if (bank->combine) + bank->irq_chip = devm_kmemdup(dev, &exynosautov920_gpio_irq_chip, + sizeof(*bank->irq_chip), GFP_KERNEL); + else + bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, + sizeof(*bank->irq_chip), GFP_KERNEL); if (!bank->irq_chip) { ret = -ENOMEM; goto err_domains; @@ -456,6 +488,22 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; +static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = { + .chip = { + .name = "exynosautov920_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_wake_mask_value = &eint_wake_mask_value, + .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, +}; + /* list of external wakeup controllers supported */ static const struct of_device_id exynos_wkup_irq_ids[] = { { .compatible = "samsung,s5pv210-wakeup-eint", @@ -468,6 +516,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { .data = &exynos7_wkup_irq_chip }, { .compatible = "samsung,exynosautov9-wakeup-eint", .data = &exynos7_wkup_irq_chip }, + { .compatible = "samsung,exynosautov920-wakeup-eint", + .data = &exynosautov920_wkup_irq_chip }, { } }; @@ -655,6 +705,20 @@ static void exynos_pinctrl_suspend_bank( pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } +static void exynosautov920_pinctrl_suspend_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + + save->eint_con = readl(regs + bank->eint_offset); + save->eint_mask = readl(regs + bank->mask_offset); + + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); +} + void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) { struct samsung_pin_bank *bank = drvdata->pin_banks; @@ -662,8 +726,12 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) int i; for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { - if (bank->eint_type == EINT_TYPE_GPIO) - exynos_pinctrl_suspend_bank(drvdata, bank); + if (bank->eint_type == EINT_TYPE_GPIO) { + if (bank->combine) + exynosautov920_pinctrl_suspend_bank(drvdata, bank); + else + exynos_pinctrl_suspend_bank(drvdata, bank); + } else if (bank->eint_type == EINT_TYPE_WKUP) { if (!irq_chip) { irq_chip = bank->irq_chip; @@ -704,14 +772,34 @@ static void exynos_pinctrl_resume_bank( + bank->eint_offset); } +static void exynosautov920_pinctrl_resume_bank( + struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + bank->eint_offset), save->eint_con); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->mask_offset), save->eint_mask); + + writel(save->eint_con, regs + bank->eint_offset); + writel(save->eint_mask, regs + bank->mask_offset); +} + void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) { struct samsung_pin_bank *bank = drvdata->pin_banks; int i; for (i = 0; i < drvdata->nr_banks; ++i, ++bank) - if (bank->eint_type == EINT_TYPE_GPIO) - exynos_pinctrl_resume_bank(drvdata, bank); + if (bank->eint_type == EINT_TYPE_GPIO) { + if (bank->combine) + exynosautov920_pinctrl_resume_bank(drvdata, bank); + else + exynos_pinctrl_resume_bank(drvdata, bank); + } } static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 3ac52c2cf998..210952c7a5aa 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -31,6 +31,7 @@ #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 #define EXYNOS_SVC_OFFSET 0xB08 +#define EXYNOSAUTOV920_SVC_OFFSET 0xF008 /* helpers to access interrupt service register */ #define EXYNOS_SVC_GROUP_SHIFT 3 @@ -140,6 +141,32 @@ .name = id \ } +#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, offs, mask_offs, pend_offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = (reg + offs), \ + .mask_offset = (reg + mask_offs), \ + .pend_offset = (reg + pend_offs), \ + .combine = true, \ + .name = id \ + } + +#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, offs, mask_offs, pend_offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = (reg + offs), \ + .mask_offset = (reg + mask_offs), \ + .pend_offset = (reg + pend_offs), \ + .combine = true, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 79babbb39ced..adf2d0cff438 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1106,6 +1106,9 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, bank->eint_type = bdata->eint_type; bank->eint_mask = bdata->eint_mask; bank->eint_offset = bdata->eint_offset; + bank->mask_offset = bdata->mask_offset; + bank->pend_offset = bdata->pend_offset; + bank->combine = bdata->combine; bank->name = bdata->name; raw_spin_lock_init(&bank->slock); @@ -1321,6 +1324,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynosautov9_of_data }, { .compatible = "tesla,fsd-pinctrl", .data = &fsd_of_data }, + { .compatible = "samsung,exynosautov920-pinctrl", + .data = &exynosautov920_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 9b3db50adef3..cbb78178651b 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -122,6 +122,9 @@ struct samsung_pin_bank_type { * @eint_type: type of the external interrupt supported by the bank. * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @mask_offset: SoC-specific EINT mask register offset of bank. + * @pend_offset: SoC-specific EINT pend register offset of bank. + * @combine: EINT register is adjacent to the GPIO control register. * @name: name to be prefixed for each pin in this pin bank. */ struct samsung_pin_bank_data { @@ -133,6 +136,9 @@ struct samsung_pin_bank_data { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + u32 mask_offset; + u32 pend_offset; + bool combine; const char *name; }; @@ -147,6 +153,9 @@ struct samsung_pin_bank_data { * @eint_type: type of the external interrupt supported by the bank. * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @mask_offset: SoC-specific EINT mask register offset of bank. + * @pend_offset: SoC-specific EINT pend register offset of bank. + * @combine: EINT register is adjacent to the GPIO control register. * @name: name to be prefixed for each pin in this pin bank. * @id: id of the bank, propagated to the pin range. * @pin_base: starting pin number of the bank. @@ -170,6 +179,9 @@ struct samsung_pin_bank { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + u32 mask_offset; + u32 pend_offset; + bool combine; const char *name; u32 id; @@ -350,6 +362,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; +extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; From patchwork Wed Nov 15 09:56:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744514 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B04F0FBE9 for ; Wed, 15 Nov 2023 09:59:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="XR3Txd6R" Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64DDF1AE for ; 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Wed, 15 Nov 2023 18:58:56 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095855epsmtip2742f802db1a8f5e58c9f567f90cb097d~Xw39LS2iC2332523325epsmtip2k; Wed, 15 Nov 2023 09:58:55 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 11/12] arm64: dts: exynos: add initial support for exynosautov920 SoC Date: Wed, 15 Nov 2023 18:56:07 +0900 Message-ID: <20231115095609.39883-12-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Te0xbVRjP6W1vL9vKroDZCSI0l4cBgbVI6cUAWbKpXUTH5qJucWE39A4Y 9OG9hQ2dipnQSTZLYVMoL4VtsAYHFugAy9jaRh7BlkUF2XjMTecmSgJGHgqLbW+d++/3fef3 yPedczAkaBINxfLVOppRU4UEuolvdcSmJBz+dD8tqRojyduNVpRsH3DxyCanS0CebOlAyd5S p4BcaAgjB+Z7hOTZ9VYeabk7ISC7mtYB+V1/PUrOzJgBWeO+yiPHWs4IybIBp5B0/K4XkGv9 jXzS3O/h3TJWgx3Bij7TjFBhMX+MKqYnbKhisKFdqOg6/4HCsCFRfNJtBoo/LeFZ2MGCtDya UtKMmFbnaJT56tx04uXXsndmy1Ik0gRpKiknxGpKRacTuzKzEl7ML/SMQ4iLqcIiTyuLYlli e0YaoynS0eI8DatLJ2itslAr1yaylIotUucmqmnd81KJJEnmIR4uyBvrGQZa/Sjv+C/9T5WC qQpeBQjAIJ4Muw0OvhcH4TYA7w8FVoBNHrwE4F9XaoVcsQxgu3XhkeKfiWHAHQwAOGgbRrli EUDT2ijwslD8WbjS0SLw4hB8DoHz5e96SQiu58HG5Qe+wGD8IOz7atEn4OPR0Lhk8WERngHP mq4KubgIaGte8URjWICnX+aO4yhPwJHan302iIdysqcO8fpDfByDC5dGgJcP8V3QNlfC2QTD 34a6/Zah8IGh3I8LoP6zdQGHj8MbnXUoh5+Dpnt6nw2Cx8KO/u2cYyR03vSnBsJTjg0h1xbB U+VBnDAGzp1z+U3CYJXzkn9tCugYtfn3aQRw8W41qARi02PDmB4bxvR/8OcAMYNQWsuqcumc JK00QU0fe3TJORqVBfheeNwrvWC+YyPRDngYsAOIIUSISB6+nw4SKamSd2hGk80UFdKsHcg8 2zYioU/maDxfRK3LlianSpJTUqTyJJlETmwTzZY1KIPwXEpHF9C0lmb+0/GwgNBSXsi2yvpK 3e7qbOaOtcbYMMXG2932Nute+eR1GL6Ej8TbKbPq3IdvXyE/Mlx+uIbNSHJjzMHvpyvFyWkH mn9M4G8Wj3XczIyNaDVNX7tz0eK8cKF48thP954JrFn/46XND/vaVunF0+8dret2fQtcTdLr R6JnQ5Dw17//muKfiTQe6Gxj3Uune/Ov3SeO4l0RxfXxbciXW4O/Gbeu6B23L0ej42O3In4d KFfte1o5tOAwuF5wMY0Xrck7B5mFqL9NYS7ZoS2y4gI06kbkvgxm5I3zJbXVP2hijmS69+yu 2XtCxN+6Jyww9a2oHdNVba++uXziiy2rIVOdM4dk9mF38+xqK8Fn8yhpHMKw1L+w+12kagQA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42LZdlhJXjdhWkiqwfHJ3BYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJVxZusJxoL2U0wVT3dJNzDe 7GLqYuTkkBAwkfh97QQjiC0ksJtR4t3xQoi4jMTyZ31sELawxP2WI6xdjFxANe8ZJb48/wTW zCagLfF9/WKwhIjAc2aJs38eMYMkmAX6mSSub0oAsYUFIiQWfekD28AioCox8dMmMJtXwE5i yqx97BAb5CX2LPoONJSDgxMo3npeC+IgW4nW3T+YIcoFJU7OfMICMV5eonnrbOYJjAKzkKRm IUktYGRaxSiZWlCcm55bbFhgmJdarlecmFtcmpeul5yfu4kRHGdamjsYt6/6oHeIkYmD8RCj BAezkgivuVxIqhBvSmJlVWpRfnxRaU5q8SFGaQ4WJXFe8Re9KUIC6YklqdmpqQWpRTBZJg5O qQamuV8dT9+ecelW568laY5/dGN89i4Juaf05Oz5T3/5d+8T5L/c/nOK/HIPq+z/U5nrJqWr LK/9vDaD3e+hTZlZxsRNglLdR8/at6zj4Dy3WsDc8gfjLN+AScfWz93Ku7tMXf9TXFZKhKaI CWeyeXXH0zlG63wuLFL4HfaveWt6sc/7f76L0z+e7f3+8UdLppfKQd93n57/lZc82PNz+V8u 9rkHn+/bu1xGa8apLZFJcd/mKS5J/cxV5FackqRbkx3ifGLWC2F54xuh/E7XznxeNWHpqoCL tvGMKtbpe4IOGVxcdewY91PBFcr2HMrKX+cdDq1WjHjstO7p/5PNvWVeEn+qYh2SJkkyrTl4 eoPvFyWW4oxEQy3mouJEAEu9RUsiAwAA X-CMS-MailID: 20231115095856epcas2p473602f53ec35b5f3c57503b21b7ef406 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095856epcas2p473602f53ec35b5f3c57503b21b7ef406 References: <20231115095609.39883-1-jaewon02.kim@samsung.com> Samsung ExynosAutov920 is ARMv8-based automotive-oriented SoC. It has AE(Automotive Enhanced) IPs for safety. * Cortex-A78AE 10-cores * GIC-600AE This is minimal support for ExynosAutov920 SoC. * Enumerate all pinctrl nodes * Enable Chip-Id * Serial0 for console * PWM Since the clock driver is not yet implemented, it is supported as fixed-clock. Signed-off-by: Jaewon Kim --- .../dts/exynos/exynosautov920-pinctrl.dtsi | 1266 +++++++++++++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 312 ++++ 2 files changed, 1578 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi new file mode 100644 index 000000000000..63b958b96c48 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi @@ -0,0 +1,1266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2023 Samsung Electronics Co., Ltd. + * + * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as + * device tree nodes in this file. + */ + +#include + +#include "exynos-pinctrl.h" + +&pinctrl_alive { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + ; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_aud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb6: gpb6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_hsi0 { + gph0: gph0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_hsi1 { + gph8: gph8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_hsi2 { + gph3: gph3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph4: gph4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph5: gph5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph6: gph6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_hsi2ufs { + gph2: gph2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ufs_rst_n: ufs-rst-n-pins { + samsung,pins = "gph2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + }; + + ufs_refclk_out: ufs-refclk-out-pins { + samsung,pins = "gph2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + }; + + ufs_rst_n_1: ufs-rst-n-1-pins { + samsung,pins = "gph2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + }; + + ufs_refclk_out_1: ufs-refclk-out-1-pins { + samsung,pins = "gph2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + }; +}; + +&pinctrl_peric0 { + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg4: gpg4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg5: gpg5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* UART PERIC0_USI00 */ + uart0_bus: uart0-bus-pins { + samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart0_bus_dual: uart0-bus-dual-pins { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI01 */ + uart1_bus: uart1-bus-pins { + samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart1_bus_dual: uart1-bus-dual-pins { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI02 */ + uart2_bus: uart2-bus-pins { + samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart2_bus_dual: uart2-bus-dual-pins { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI03 */ + uart3_bus: uart3-bus-pins { + samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart3_bus_dual: uart3-bus-dual-pins { + samsung,pins = "gpp1-4", "gpp1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI04 */ + uart4_bus: uart4-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart4_bus_dual: uart4-bus-dual-pins { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI05 */ + uart5_bus: uart5-bus-pins { + samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart5_bus_dual: uart5-bus-dual-pins { + samsung,pins = "gpp2-4", "gpp2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI06 */ + uart6_bus: uart6-bus-pins { + samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart6_bus_dual: uart6-bus-dual-pins { + samsung,pins = "gpp3-0", "gpp3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI07 */ + uart7_bus: uart7-bus-pins { + samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6", "gpp3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart7_bus_dual: uart7-bus-dual-pins { + samsung,pins = "gpp3-4", "gpp3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC0_USI08 */ + uart8_bus: uart8-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart8_bus_dual: uart8-bus-dual-pins { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI00 */ + hsi2c0_bus: hsi2c0-bus-pins { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI00_I2C */ + hsi2c1_bus: hsi2c1-bus-pins { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI01 */ + hsi2c2_bus: hsi2c2-bus-pins { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI01_I2C */ + hsi2c3_bus: hsi2c3-bus-pins { + samsung,pins = "gpp0-6", "gpp0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI02 */ + hsi2c4_bus: hsi2c4-bus-pins { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI02_I2C */ + hsi2c5_bus: hsi2c5-bus-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI03 */ + hsi2c6_bus: hsi2c6-bus-pins { + samsung,pins = "gpp1-4", "gpp1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI03_I2C */ + hsi2c7_bus: hsi2c7-bus-pins { + samsung,pins = "gpp1-6", "gpp1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI04 */ + hsi2c8_bus: hsi2c8-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI04_I2C */ + hsi2c9_bus: hsi2c9-bus-pins { + samsung,pins = "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI05 */ + hsi2c10_bus: hsi2c10-bus-pins { + samsung,pins = "gpp2-4", "gpp2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI05_I2C */ + hsi2c11_bus: hsi2c11-bus-pins { + samsung,pins = "gpp2-6", "gpp2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI06 */ + hsi2c12_bus: hsi2c12-bus-pins { + samsung,pins = "gpp3-0", "gpp3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI06_I2C */ + hsi2c13_bus: hsi2c13-bus-pins { + samsung,pins = "gpp3-2", "gpp3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI07 */ + hsi2c14_bus: hsi2c14-bus-pins { + samsung,pins = "gpp3-4", "gpp3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI07_I2C */ + hsi2c15_bus: hsi2c15-bus-pins { + samsung,pins = "gpp3-6", "gpp3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI08 */ + hsi2c16_bus: hsi2c16-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC0 USI08_I2C */ + hsi2c17_bus: hsi2c17-bus-pins { + samsung,pins = "gpp4-2", "gpp4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI00 */ + spi0_bus: spi0-bus-pins { + samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi0_cs: spi0-cs-pins { + samsung,pins = "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi0_cs_func: spi0-cs-func-pins { + samsung,pins = "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI01 */ + spi1_bus: spi1-bus-pins { + samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi1_cs: spi1-cs-pins { + samsung,pins = "gpp0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi1_cs_func: spi1-cs-func-pins { + samsung,pins = "gpp0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI02 */ + spi2_bus: spi2-bus-pins { + samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi2_cs: spi2-cs-pins { + samsung,pins = "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi2_cs_func: spi2-cs-func-pins { + samsung,pins = "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI03 */ + spi3_bus: spi3-bus-pins { + samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi3_cs: spi3-cs-pins { + samsung,pins = "gpp1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi3_cs_func: spi3-cs-func-pins { + samsung,pins = "gpp1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI04 */ + spi4_bus: spi4-bus-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi4_cs: spi4-cs-pins { + samsung,pins = "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi4_cs_func: spi4-cs-func-pins { + samsung,pins = "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI05 */ + spi5_bus: spi5-bus-pins { + samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi5_cs: spi5-cs-pins { + samsung,pins = "gpp2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi5_cs_func: spi5-cs-func-pins { + samsung,pins = "gpp2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI06 */ + spi6_bus: spi6-bus-pins { + samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi6_cs: spi6-cs-pins { + samsung,pins = "gpp3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi6_cs_func: spi6-cs-func-pins { + samsung,pins = "gpp3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI07 */ + spi7_bus: spi7-bus-pins { + samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi7_cs: spi7-cs-pins { + samsung,pins = "gpp3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi7_cs_func: spi7-cs-func-pins { + samsung,pins = "gpp3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC0 USI08 */ + spi8_bus: spi8-bus-pins { + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi8_cs: spi8-cs-pins { + samsung,pins = "gpp4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi8_cs_func: spi8-cs-func-pins { + samsung,pins = "gpp4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I3C PERIC0 */ + i3c0_bus: i3c0-bus-pins { + samsung,pins = "gpp2-6", "gpp2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i3c1_bus: i3c1-bus-pins { + samsung,pins = "gpp3-2", "gpp3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i3c2_bus: i3c2-bus-pins { + samsung,pins = "gpp3-6", "gpp3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i3c3_bus: i3c3-bus-pins { + samsung,pins = "gpp4-2", "gpp4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* PWM PERIC0 */ + pwm_tout0: pwm-tout0-pins { + samsung,pins = "gpg0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pwm_tout1: pwm-tout1-pins { + samsung,pins = "gpg0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pwm_tout2: pwm-tout2-pins { + samsung,pins = "gpg0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + pwm_tout3: pwm-tout3-pins { + samsung,pins = "gpg0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_peric1 { + gpp5: gpp5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp6: gpp6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp7: gpp7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp8: gpp8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp9: gpp9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp10: gpp10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp11: gpp11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp12: gpp12-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* UART PERIC1 USI09 */ + uart9_bus: uart9-bus-pins { + samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2", "gpp5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart9_bus_dual: uart9-bus-dual-pins { + samsung,pins = "gpp5-0", "gpp5-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1 USI10 */ + uart10_bus: uart10-bus-pins { + samsung,pins = "gpp5-4", "gpp5-5", "gpp5-6", "gpp5-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart10_bus_dual: uart10-bus-dual-pins { + samsung,pins = "gpp5-4", "gpp5-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1 USI11 */ + uart11_bus: uart11-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2", "gpp10-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart11_bus_dual: uart11-bus-dual-pins { + samsung,pins = "gpp10-0", "gpp10-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1_USI12 */ + uart12_bus: uart12-bus-pins { + samsung,pins = "gpp7-0", "gpp7-1", "gpp7-2", "gpp7-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart12_bus_dual: uart12-bus-dual-pins { + samsung,pins = "gpp7-0", "gpp7-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1_USI13 */ + uart13_bus: uart13-bus-pins { + samsung,pins = "gpp7-4", "gpp7-5", "gpp7-6", "gpp7-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart13_bus_dual: uart13-bus-dual-pins { + samsung,pins = "gpp7-4", "gpp7-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1 USI14 */ + uart14_bus: uart14-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2", "gpp8-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart14_bus_dual: uart14-bus-dual-pins { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1 USI15 */ + uart15_bus: uart15-bus-pins { + samsung,pins = "gpp11-0", "gpp11-1", "gpp11-2", "gpp11-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart15_bus_dual: uart15-bus-dual-pins { + samsung,pins = "gpp11-0", "gpp11-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1 USI16 */ + uart16_bus: uart16-bus-pins { + samsung,pins = "gpp9-0", "gpp9-1", "gpp9-2", "gpp9-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart16_bus_dual: uart16-bus-dual-pins { + samsung,pins = "gpp9-0", "gpp9-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* UART PERIC1 USI17 */ + uart17_bus: uart17-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2", "gpp12-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart17_bus_dual: uart17-bus-dual-pins { + samsung,pins = "gpp12-0", "gpp12-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI09 */ + hsi2c18_bus: hsi2c18-bus-pins { + samsung,pins = "gpp5-0", "gpp5-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI09_I2C */ + hsi2c19_bus: hsi2c19-bus-pins { + samsung,pins = "gpp5-2", "gpp5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI10 */ + hsi2c20_bus: hsi2c20-bus-pins { + samsung,pins = "gpp5-4", "gpp5-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI10_I2C */ + hsi2c21_bus: hsi2c21-bus-pins { + samsung,pins = "gpp5-6", "gpp5-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI11 */ + hsi2c22_bus: hsi2c22-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI11_I2C */ + hsi2c23_bus: hsi2c23-bus-pins { + samsung,pins = "gpp10-2", "gpp10-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI12 */ + hsi2c24_bus: hsi2c24-bus-pins { + samsung,pins = "gpp7-0", "gpp7-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI12_I2C */ + hsi2c25_bus: hsi2c25-bus-pins { + samsung,pins = "gpp7-2", "gpp7-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI13 */ + hsi2c26_bus: hsi2c26-bus-pins { + samsung,pins = "gpp7-4", "gpp7-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI13_I2C */ + hsi2c27_bus: hsi2c27-bus-pins { + samsung,pins = "gpp7-6", "gpp7-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI14 */ + hsi2c28_bus: hsi2c28-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI14_I2C */ + hsi2c29_bus: hsi2c29-bus-pins { + samsung,pins = "gpp8-2", "gpp8-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI15 */ + hsi2c30_bus: hsi2c30-bus-pins { + samsung,pins = "gpp11-0", "gpp11-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI15_I2C */ + hsi2c31_bus: hsi2c31-bus-pins { + samsung,pins = "gpp11-2", "gpp11-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI16 */ + hsi2c32_bus: hsi2c32-bus-pins { + samsung,pins = "gpp9-0", "gpp9-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI16_I2C */ + hsi2c33_bus: hsi2c33-bus-pins { + samsung,pins = "gpp9-2", "gpp9-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI17 */ + hsi2c34_bus: hsi2c34-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I2C PERIC1 USI17_I2C */ + hsi2c35_bus: hsi2c35-bus-pins { + samsung,pins = "gpp12-2", "gpp12-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI09 */ + spi9_bus: spi9-bus-pins { + samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi9_cs: spi9-cs-pins { + samsung,pins = "gpp5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi9_cs_func: spi9-cs-func-pins { + samsung,pins = "gpp5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI10 */ + spi10_bus: spi10-bus-pins { + samsung,pins = "gpp5-4", "gpp5-5", "gpp5-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi10_cs: spi10-cs-pins { + samsung,pins = "gpp5-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi10_cs_func: spi10-cs-func-pins { + samsung,pins = "gpp5-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI11 */ + spi11_bus: spi11-bus-pins { + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi11_cs: spi11-cs-pins { + samsung,pins = "gpp10-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi11_cs_func: spi11-cs-func-pins { + samsung,pins = "gpp10-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI12 */ + spi12_bus: spi12-bus-pins { + samsung,pins = "gpp7-0", "gpp7-1", "gpp7-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi12_cs: spi12-cs-pins { + samsung,pins = "gpp7-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi12_cs_func: spi12-cs-func-pins { + samsung,pins = "gpp7-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI13 */ + spi13_bus: spi13-bus-pins { + samsung,pins = "gpp7-4", "gpp7-5", "gpp7-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi13_cs: spi13-cs-pins { + samsung,pins = "gpp7-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi13_cs_func: spi13-cs-func-pins { + samsung,pins = "gpp7-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI14 */ + spi14_bus: spi14-bus-pins { + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi14_cs: spi14-cs-pins { + samsung,pins = "gpp8-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi14_cs_func: spi14-cs-func-pins { + samsung,pins = "gpp8-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI15 */ + spi15_bus: spi15-bus-pins { + samsung,pins = "gpp11-0", "gpp11-1", "gpp11-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi15_cs: spi15-cs-pins { + samsung,pins = "gpp11-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi15_cs_func: spi15-cs-func-pins { + samsung,pins = "gpp11-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI16 */ + spi16_bus: spi16-bus-pins { + samsung,pins = "gpp9-0", "gpp9-1", "gpp9-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi16_cs: spi16-cs-pins { + samsung,pins = "gpp9-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi16_cs_func: spi16-cs-func-pins { + samsung,pins = "gpp9-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* SPI PERIC1 USI17 */ + spi17_bus: spi17-bus-pins { + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi17_cs: spi17-cs-pins { + samsung,pins = "gpp12-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + spi17_cs_func: spi17-cs-func-pins { + samsung,pins = "gpp12-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* I3C PERIC1 */ + i3c4_bus: i3c4-bus-pins { + samsung,pins = "gpp7-2", "gpp7-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i3c5_bus: i3c5-bus-pins { + samsung,pins = "gpp7-6", "gpp7-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i3c6_bus: i3c6-bus-pins { + samsung,pins = "gpp8-2", "gpp8-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i3c7_bus: i3c7-bus-pins { + samsung,pins = "gpp11-2", "gpp11-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi new file mode 100644 index 000000000000..4de76e29164f --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAutov920 SoC device tree source + * + * Copyright (c) 2023 Samsung Electronics Co., Ltd. + * + */ + +#include +#include + +/ { + compatible = "samsung,exynosautov920"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_aud; + pinctrl2 = &pinctrl_hsi0; + pinctrl3 = &pinctrl_hsi1; + pinctrl4 = &pinctrl_hsi2; + pinctrl5 = &pinctrl_hsi2ufs; + pinctrl6 = &pinctrl_peric0; + pinctrl7 = &pinctrl_peric1; + }; + + arm-pmu { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + xtcxo: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "oscclk"; + }; + + /* + * FIXME: Keep the stub clock for serial driver, until proper clock + * driver is implemented. + */ + clock_usi: clock-usi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "usi"; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; + + cpu4: cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x10000>; + enable-method = "psci"; + }; + + cpu5: cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x10100>; + enable-method = "psci"; + }; + + cpu6: cpu@10200 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x10200>; + enable-method = "psci"; + }; + + cpu7: cpu@10300 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x10300>; + enable-method = "psci"; + }; + + cpu8: cpu@20000 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x20000>; + enable-method = "psci"; + }; + + cpu9: cpu@20100 { + device_type = "cpu"; + compatible = "arm,cortex-a78ae"; + reg = <0x0 0x20100>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynosautov920-chipid", + "samsung,exynos850-chipid"; + reg = <0x10000000 0x24>; + }; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x10400000 0x10000>, + <0x10460000 0x140000>; + interrupts = ; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x11850000 0x10000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynosautov920-wakeup-eint"; + }; + }; + + pinctrl_aud: pinctrl@1a460000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x1a460000 0x10000>; + }; + + pinctrl_hsi0: pinctrl@16040000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x16040000 0x10000>; + interrupts = ; + }; + + pinctrl_hsi1: pinctrl@16450000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x16450000 0x10000>; + interrupts = ; + }; + + pinctrl_hsi2: pinctrl@16c10000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x16c10000 0x10000>; + interrupts = ; + }; + + pinctrl_hsi2ufs: pinctrl@16d20000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x16d20000 0x10000>; + interrupts = ; + }; + + pinctrl_peric0: pinctrl@10830000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x10830000 0x10000>; + interrupts = ; + }; + + pinctrl_peric1: pinctrl@10c30000 { + compatible = "samsung,exynosautov920-pinctrl"; + reg = <0x10c30000 0x10000>; + interrupts = ; + }; + + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynosautov920-pmu", + "samsung,exynos7-pmu","syscon"; + reg = <0x11860000 0x10000>; + }; + + pwm: pwm@109b0000 { + compatible = "samsung,exynosautov920-pwm", + "samsung,exynos4210-pwm"; + reg = <0x109b0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&xtcxo>; + clock-names = "timers"; + status = "disabled"; + }; + + syscon_peric0: syscon@102820000 { + compatible = "samsung,exynosautov920-peric0-sysreg", + "syscon"; + reg = <0x10820000 0x2000>; + }; + + syscon_peric1: syscon@10c21000 { + compatible = "samsung,exynosautov920-peric1-sysreg", + "syscon"; + reg = <0x10c21000 0x2000>; + }; + + usi_0: usi@108800c0 { + compatible = "samsung,exynosautov920-usi", + "samsung,exynos850-usi"; + reg = <0x108800c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&clock_usi>, <&clock_usi>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@10880000 { + compatible = "samsung,exynosautov920-uart", + "samsung,exynos850-uart"; + reg = <0x10880000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&clock_usi>, <&clock_usi>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +}; + +#include "exynosautov920-pinctrl.dtsi" From patchwork Wed Nov 15 09:56:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaewon Kim X-Patchwork-Id: 744280 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7AF3C154 for ; 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Wed, 15 Nov 2023 18:58:56 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.55]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231115095856epsmtip232c3ccc608c345f749a2f8215284d513~Xw39cuzZe2498624986epsmtip2g; Wed, 15 Nov 2023 09:58:56 +0000 (GMT) From: Jaewon Kim To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , Thierry Reding , Uwe Kleine-K?nig , Greg Kroah-Hartman , Jiri Slaby Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, Jaewon Kim Subject: [PATCH v2 12/12] arm64: dts: exynos: add minimal support for exynosautov920 sadk board Date: Wed, 15 Nov 2023 18:56:08 +0900 Message-ID: <20231115095609.39883-13-jaewon02.kim@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115095609.39883-1-jaewon02.kim@samsung.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAJsWRmVeSWpSXmKPExsWy7bCmmW7CtJBUg2vXrS0ezNvGZrFm7zkm i/lHzrFaNC9ez2axo+EIq8W7uTIWe19vZbeY8mc5k8Wmx9dYLTbP/8NocXnXHDaLu3dXMVrM OL+PyeLM4l52i9a9R9gtDr9pZ7X4uWsei8WqXUB1tydOZnQQ9tg56y67x6ZVnWwed67tYfPY P3cNu8fmJfUe/X8NPPq2rGL0+LxJLoAjKtsmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX 0NLCXEkhLzE31VbJxSdA1y0zB+gdJYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUmpBSk6B eYFecWJucWleul5eaomVoYGBkSlQYUJ2xpv3zYwFN8UrXnY8ZWtgnC/cxcjJISFgInF98yGm LkYuDiGBHYwSTy+fZoRwPjFK7Hh8Fsr5xiixoL8VqIwDrKXpmTtIt5DAXkaJ3c1eEDUfGSU2 /bjMApJgE9CW+L5+MSuILSJwn1nidVs1SBGzQDuTxLxvL1lABgkLJEq0nQ4AqWERUJXYcf8a E4jNK2An8enfGxaI8+Ql9iz6DraXEyjeel4LokRQ4uTMJ2AlzEAlzVtnM0OU3+CQuDXJDMJ2 kWjZsYYdwhaWeHV8C5QtJfH53V42CDtbon36H1YIu0Li4obZUHFjiVnP2hlB1jILaEqs36UP 8bmyxJFbUFv5JDoO/2WHCPNKdLQJQTSqSdyfeg5qiIzEpCMrmSBsD4mJe3dDA3Mio8TGtb3M ExgVZiF5ZhaSZ2YhLF7AyLyKUSy1oDg3PbXYqMAIHrvJ+bmbGMFJW8ttB+OUtx/0DjEycTAe YpTgYFYS4TWXC0kV4k1JrKxKLcqPLyrNSS0+xGgKDOmJzFKiyfnAvJFXEm9oYmlgYmZmaG5k amCuJM57r3VuipBAemJJanZqakFqEUwfEwenVAOTkrsNa14x229BK5Xc3P/2PPdZGab5c629 f1IjOaTwYPKjOw+nX1Tr6hWWEp3Oks7yqFbp2YvE6uj/6wyLTvRtzmEMOZIgcZtlWXyIXKPr M5XH31NXFi00fXFX7pb7IS2vygM7GX/df9kt2rXw6odPBq+51+5IjWG7usKMuYlzu+O6Ldx7 ZIWYc7Q2BDawWdja39x5/02TxUre6dvn3c86+cHiS8uumrU83bpdWgmnrl7pWJKv/eDnqTcR ktra+zoze/Zcakrcy3V0c0O4hYZ1183PjgLnHjG1azBJTzu+4t5Wv9n7n9z9/C3zn3H8D/2z c/zvsmrVOn8VmbRV+Zoyv5Fx54UlF4wMyy3V9+kqsRRnJBpqMRcVJwIAngHRvGMEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42LZdlhJXjdhWkiqwZHTUhYP5m1js1iz9xyT xfwj51gtmhevZ7PY0XCE1eLdXBmLva+3sltM+bOcyWLT42usFpvn/2G0uLxrDpvF3burGC1m nN/HZHFmcS+7ReveI+wWh9+0s1r83DWPxWLVLqC62xMnMzoIe+ycdZfdY9OqTjaPO9f2sHns n7uG3WPzknqP/r8GHn1bVjF6fN4kF8ARxWWTkpqTWZZapG+XwJXx5n0zY8FN8YqXHU/ZGhjn C3cxcnBICJhIND1z72Lk4hAS2M0oseDNP9YuRk6guIzE8md9bBC2sMT9liOsEEXvGSXOv93M DJJgE9CW+L5+MVhCROA5s8TZP4/AEswC/UwS1zclgGwQFoiXeHdREiTMIqAqseP+NSYQm1fA TuLTvzcsEAvkJfYs+s4EUs4JFG89rwUSFhKwlWjd/YMZolxQ4uTMJywQ0+UlmrfOZp7AKDAL SWoWktQCRqZVjJKpBcW56bnFhgWGeanlesWJucWleel6yfm5mxjBMaaluYNx+6oPeocYmTgY DzFKcDArifCay4WkCvGmJFZWpRblxxeV5qQWH2KU5mBREucVf9GbIiSQnliSmp2aWpBaBJNl 4uCUamCq3eBy5bJfmnhma/SDOUdY+jjOTpWyWs13U2/VxONr7b4zbZkv33dBqNXqfb2w4c01 nX//bl1z9u1K8/szKz88WJ2RGScWNnOPZlPZ4x3c2RM+VC7+//sDA7PO3xqWvc4sARv26p0o FmJtYNl6O+zPad7Xteor728v/jFrdUu7yJe7bTc/1XzW27amRFnr5QTmx+8v8ogkdlntftLv xHJo0fs2mfX1inXyQdcmLc27pOgfO61d8ZnZzXeNq+LEGJKvlW7ODHu5cePfZYYL/9axJa4K 1krPP3Q4ePX35R35v1Q27p5m8+uYr4SX84GrsuYLeZeUdJd9O3JwZqrYnuRde5fN3bRgroTR 27VLj7CIXlZiKc5INNRiLipOBADm9AgPIAMAAA== X-CMS-MailID: 20231115095856epcas2p189ef50d3e97656a92df6fef64414690c X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231115095856epcas2p189ef50d3e97656a92df6fef64414690c References: <20231115095609.39883-1-jaewon02.kim@samsung.com> ExynosAutov920 SADK is ExynosAutov920 SoC based SADK(Samsung Automotive Development Kit) board. It has 16GB(8GB + 8GB) LPDDR5 RAM and 256GB (128GB + 128GB) UFS. This is minimal support board device-tree. * Serial console * GPIO Key * PWM FAN Signed-off-by: Jaewon Kim --- arch/arm64/boot/dts/exynos/Makefile | 3 +- .../boot/dts/exynos/exynosautov920-sadk.dts | 88 +++++++++++++++++++ 2 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index 6e4ba69268e5..da06e1a9456c 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -5,4 +5,5 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ exynos7-espresso.dtb \ exynos7885-jackpotlte.dtb \ exynos850-e850-96.dtb \ - exynosautov9-sadk.dtb + exynosautov9-sadk.dtb \ + exynosautov920-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts new file mode 100644 index 000000000000..e250b5594b58 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAutov920 SADK board device tree source + * + * Copyright (c) 2023 Samsung Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "exynosautov920.dtsi" +#include "exynos-pinctrl.h" +#include +#include + +/ { + model = "Samsung ExynosAutov920 SADK board"; + compatible = "samsung,exynosautov920-sadk", "samsung,exynosautov920"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x70000000>, + <0x8 0x80000000 0x1 0xfba00000>, + <0xa 0x00000000 0x2 0x00000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_wakeup &key_back>; + + key-wakeup { + label = "KEY_WAKEUP"; + linux,code = ; + gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + key-back { + label = "KEY_BACK"; + linux,code = ; + gpios = <&gpp6 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl_alive { + key_wakeup: key-wakeup-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + }; +}; + +&pinctrl_peric1 { + key_back: key-back-pins { + samsung,pins = "gpp6-3"; + samsung,pin-function = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_tout0>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&usi_0 { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&xtcxo { + clock-frequency = <38400000>; +};