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This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/stm32f405_soc.h | 4 ---- hw/arm/netduinoplus2.c | 7 ++++++- hw/arm/olimex-stm32-h405.c | 8 ++++++-- hw/arm/stm32f405_soc.c | 8 +------- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index c968ce3ab2..d15c03c4b5 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define CCM_SIZE (64 * 1024) struct STM32F405State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; ARMv7MState armv7m; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c081605..e411806dd7 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -55,7 +54,13 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; + mc->valid_cpu_types = machine_valid_cpu_types; mc->init = netduinoplus2_init; } diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b7..694b1dd6ed 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) static void olimex_stm32_h405_machine_init(MachineClass *mc) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc = "Olimex STM32-H405 (Cortex-M4)"; mc->init = olimex_stm32_h405_init; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types = machine_valid_cpu_types; /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size = 0; diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cef23d7ee4..a65bbe298d 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("RNG", 0x50060800, 0x400); } -static Property stm32f405_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f405_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f405_soc_realize; - device_class_set_props(dc, stm32f405_soc_properties); /* No vmstate or reset required: device has no internal state */ } From patchwork Wed Nov 15 23:21:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 744003 Delivered-To: patch@linaro.org Received: by 2002:a5d:5388:0:b0:32d:baff:b0ca with SMTP id d8csp22696wrv; Wed, 15 Nov 2023 15:24:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IGsl0l1cnC9pRVki95X2ciYVfaFt9l8n8CjgZFjWaEpToB1HYhrQ4WX+Ob9SQRP1viHOptm X-Received: by 2002:ac8:1001:0:b0:41e:9ef9:38f8 with SMTP id z1-20020ac81001000000b0041e9ef938f8mr1589qti.17.1700090641709; Wed, 15 Nov 2023 15:24:01 -0800 (PST) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id f22-20020a05622a105600b00417b8f534a5si10101518qte.365.2023.11.15.15.24.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Nov 2023 15:24:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MHeh91/n"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3PDN-0007bV-Pv; Wed, 15 Nov 2023 18:22:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3PDK-0007ap-Ui for qemu-devel@nongnu.org; Wed, 15 Nov 2023 18:22:30 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r3PD2-0003MI-Bl for qemu-devel@nongnu.org; Wed, 15 Nov 2023 18:22:30 -0500 Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-543c3756521so306875a12.2 for ; Wed, 15 Nov 2023 15:22:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700090531; x=1700695331; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z2Aez4pIK4BJ1WwRvt8loGDJ5oavAC3olsgV9rlMnB0=; b=MHeh91/nrgkxfcXxOepPhhIyAPcIaBmG3xCVynwggyKytPPJUaKpQH2AjUptiQdup2 xQWg8MWFnzLwFkVUZ0Ob44G/nPW7WuWyiiPjW+wJ+qMli0c5d1iZd/rYdXXZOPnuzrZr bmFDBMRDUc1ouE7o3dQivK3692qpplsBmEba5qBABR0xEoLuSQqPjLXs/K5AgWldCvv6 pximfUh77jtf4jKti0n0/YvfphsSBfc0F8uifLmeni0XrFCycou71UO0f17i8H4UGf9E mhHtbzUKU13/r7+CR6TsK+GPTwIiImRf0tgJTYtNyR2aJxqsUFEi7iYz3QIJ8+FWLfj/ u0Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700090531; x=1700695331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z2Aez4pIK4BJ1WwRvt8loGDJ5oavAC3olsgV9rlMnB0=; b=WbfD+oOpOk5HIWrLOJKHB7QbniouL4gH0KofK1qANL6FSiGuicQnfMI2hZDRvgs54z VrA8IQtm1fGYV9/EFAa5jxs2frql4mabyXVJjFGnwvUu3Zx6mrsb9yEKTmP2rxkBwhGk LvmMr3O7UyZDzWMMQJYxtdlzLXTcJUYbr8ZvyGnsvjtcZc/BFKXbdD+AJCFjGBcF61fB biZKdLKHxhj5UJdwUFARBgMgfTgjPLSRO65OCCOO1sz8jTEjfyVyD/JXGnarYpeK4qax vTiXePgNJXzD6fjxfra41nOS2e94Dqt49eGbIisKMcC2PEw4wU/Ei7n/RSilFtKgUq8g cbfw== X-Gm-Message-State: AOJu0Ywn5YZv6eJ09/p3+bRBbBJeFI1urQJmj0808oi7lXyaW19Odz4T Hq/097Em93FoiOm5dAgK1H2xzPodnPKHuFDq2ys= X-Received: by 2002:a05:6402:5193:b0:543:5789:4d6c with SMTP id q19-20020a056402519300b0054357894d6cmr733971edd.2.1700090530804; Wed, 15 Nov 2023 15:22:10 -0800 (PST) Received: from m1x-phil.lan ([176.176.130.62]) by smtp.gmail.com with ESMTPSA id v22-20020a50d096000000b0053e0f63ce33sm7104725edd.95.2023.11.15.15.22.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 15 Nov 2023 15:22:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , =?utf-8?q?In=C3=A8s_Varhol?= , Tyrone Ting , Subbaraya Sundeep , Hao Wu , Felipe Balbi , Gavin Shan , Igor Mammedov , Subbaraya Sundeep , Peter Maydell , Eduardo Habkost , Alistair Francis , Alexandre Iooss , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-8.2? 2/6] hw/arm/stm32f205: Report error when incorrect CPU is used Date: Thu, 16 Nov 2023 00:21:49 +0100 Message-ID: <20231115232154.4515-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231115232154.4515-1-philmd@linaro.org> References: <20231115232154.4515-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 'netduino2' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-arm -M netduino2 -cpu cortex-a9 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-arm -M netduino2 -cpu cortex-a9 qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/stm32f205_soc.h | 4 ---- hw/arm/netduino2.c | 7 ++++++- hw/arm/stm32f205_soc.c | 9 ++------- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 5a4f776264..4f4c8bbebc 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC) #define SRAM_SIZE (128 * 1024) struct STM32F205State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; ARMv7MState armv7m; diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 83753d53a3..94b6b379d6 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F205_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine) static void netduino2_machine_init(MachineClass *mc) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc = "Netduino 2 Machine (Cortex-M3)"; mc->init = netduino2_init; + mc->valid_cpu_types = machine_valid_cpu_types; mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index c6b75a381d..1a548646f6 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) } } -static Property stm32f205_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f205_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f205_soc_realize; - device_class_set_props(dc, stm32f205_soc_properties); + /* No vmstate or reset required: device has no internal state */ } static const TypeInfo stm32f205_soc_info = { From patchwork Wed Nov 15 23:21:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 744001 Delivered-To: patch@linaro.org Received: by 2002:a5d:5388:0:b0:32d:baff:b0ca with SMTP id d8csp22477wrv; Wed, 15 Nov 2023 15:23:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IHiXWJPzD5T0kE88CNH9zF8hIA0iQD6GGUCVzXaP+1ok7GU4wJcMh2cHixppYEJUbX+gM70 X-Received: by 2002:a05:620a:2481:b0:775:9bb1:9ac4 with SMTP id i1-20020a05620a248100b007759bb19ac4mr8056812qkn.61.1700090601976; Wed, 15 Nov 2023 15:23:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700090601; cv=none; d=google.com; s=arc-20160816; b=CJp0WA+zxC5kn2mN1dXy5yLikpsI0AoR7KbHPre91z/ckX+l+sIl8vz/ZC1sOca0rd IeAy16xzcTkM2hk87N+KuD0vmFs6/4UWiphmWW3NV8sU4aTjFy2r2hkxvM9wEDCw0DCU xExnFvcAP12IwGTp1qy2zK9eESXa2MJCo9Mn99EKUPln4w05i+BdN5pcSBmUEOMDGcU5 gp1g0Fzu9poiE/fi1GB+QTsvxEBUj843QHavUhwfi4pC6CLUOl7O3qC8h0EDOkaPUOK4 nJ10DnsH5MigRkRNsba4FcgP+POC2Ldnhf5MaA3f8UnOEnLgqFYSgEKzi9jVUxWylWFm 1TxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=no978ZTm2/H5gCS/ezA/0hjk4jjwIQ7oHQcjYSAByag=; fh=uMNkG2qG0zUfNX9Dd8yIHy0nhEp+iUPJbdGoU1GKRvc=; b=rZvsWr9Fx5rIhQB+B7BmDaLP/4yybHc+4RfJIc29R64hEJqrfveFt83bo1UHEBp3jj kNN+aCE+4WM9iedjYXHizRpbPmb3SZsee1Bn/nGcL+eA4SlLJfS+FTzgM9HmGibH5Wnw W1Y2YPxXsVSjNozYEmYXybEu7FYCMeaOK3uVVI65mTKaOrSf4evBvrg4sIAUAS75B584 VNyCfP+2K6W6jipEWcuJfWtx9ippfQx94kiUhQtxyvcwrUsnYOViT6UazqInbSFKTyjj QEHLKd7BKJ4NADHz/kTEumjP11YVn773YyZh87qVF1MytSFYDAiudiAGOaSHCKWXN3VV Pwig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nOu528ys; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/stm32f100_soc.h | 4 ---- hw/arm/stm32f100_soc.c | 9 ++------- hw/arm/stm32vldiscovery.c | 7 ++++++- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 40cd415b28..a74d7b369c 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) #define SRAM_SIZE (8 * 1024) struct STM32F100State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - char *cpu_type; - ARMv7MState armv7m; STM32F2XXUsartState usart[STM_NUM_USARTS]; diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index f7b344ba9f..b90d440d7a 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) /* Init ARMv7m */ armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("CRC", 0x40023000, 0x400); } -static Property stm32f100_soc_properties[] = { - DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f100_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = stm32f100_soc_realize; - device_class_set_props(dc, stm32f100_soc_properties); + /* No vmstate or reset required: device has no internal state */ } static const TypeInfo stm32f100_soc_info = { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952f..6300dca722 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); dev = qdev_new(TYPE_STM32F100_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine) static void stm32vldiscovery_machine_init(MachineClass *mc) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; mc->init = stm32vldiscovery_init; + mc->valid_cpu_types = machine_valid_cpu_types; } DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) From patchwork Wed Nov 15 23:21:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 744005 Delivered-To: patch@linaro.org Received: by 2002:a5d:5388:0:b0:32d:baff:b0ca with SMTP id d8csp22770wrv; Wed, 15 Nov 2023 15:24:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IGdrXk+rqL4RlaICc77Db6TfIVjwIASEm6YyoLUTjqmulQ9AhybAi5V+/Qq8PMePLFyBf2P X-Received: by 2002:a05:620a:385b:b0:77a:663:aaf with SMTP id po27-20020a05620a385b00b0077a06630aafmr6847071qkn.45.1700090654788; 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[209.51.188.17]) by mx.google.com with ESMTPS id m7-20020a05620a290700b0077a3bdd7079si10107473qkp.688.2023.11.15.15.24.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Nov 2023 15:24:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VjtwpG9n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3PDL-0007ax-7n; Wed, 15 Nov 2023 18:22:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3PDI-0007ZF-Pm for qemu-devel@nongnu.org; Wed, 15 Nov 2023 18:22:28 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r3PDG-0003Ri-1E for qemu-devel@nongnu.org; Wed, 15 Nov 2023 18:22:28 -0500 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-543923af573so339247a12.0 for ; Wed, 15 Nov 2023 15:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700090543; x=1700695343; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SyOSV1bHLb/8jtxLoF5k1Jl+S3gYGF1w2lu5Kj6Bo84=; b=VjtwpG9n89RgJcXUQrRQgGX3I840mcjcXzcJ8Ce1D8oglzQrU2HI9L04Q0zip8x/Nd 8r2pwkqkRFemG3ye5+xw187DKEUpqsXq+El2s8jUR3Iu4mMYfU60Zffr/RVmlUM3JR7l HiGoss38b+NgDq7r814G3KcuZ9MUoHPm0CF75f+9WAPzy0ps/shwNMOYa2RNZa6xSy5w ovyJT5cq3suIOO4mjDAI3NmrKkjifQr2x+u08RN8R5s8AkeBP7ct/AAhN87g8stD2/j3 RjBCL/GcDa8TLpmu4eACpDt5dAotuwPNv8fq2A9z1FI4GPTYCo1hIwypmTD5TiuAZAdg JWOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700090543; x=1700695343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SyOSV1bHLb/8jtxLoF5k1Jl+S3gYGF1w2lu5Kj6Bo84=; b=Vu+zGu9yimv+UnaTiIik8mXezsZNDQ3+OrqI+D+StAp81pheyw7TdTox7xqR0xY801 AzQQo0dwDeB5dygYYb9cGlipaf2VGxx6crsgMscgAKwnFXaBEyrRh1r2dQ4t6EoirRZL Nldeq8w4ymI3aNen2A4Ph4AroaSpzZuKR4z9qR4BQ7SIzCEy/kZOJ7ACamIjGtbG9f0B lGnBfB0QJIqWAGnNzzN/+KTY78kQ3z7yhQ9wkkYJGMLWb7sKhzYkiI9fw1UsEY5kqCxp wxHfCEqmiaMar4r83Ud+0PHRplNGKqFYDebK4UxdrAVvbb5f4U++qoQAFdX+IPiVr2H8 bMEQ== X-Gm-Message-State: AOJu0YxZAmYjuinX8M3TXERhBgMuth2KVggORUPxTCax82P+tGUqkLhj SqHgpAK5FoA2qj8jcvcMLGLphDbEO6Z/N6k8qlU= X-Received: by 2002:a17:907:9688:b0:9e8:48e6:8e0a with SMTP id hd8-20020a170907968800b009e848e68e0amr11040286ejc.61.1700090543047; Wed, 15 Nov 2023 15:22:23 -0800 (PST) Received: from m1x-phil.lan ([176.176.130.62]) by smtp.gmail.com with ESMTPSA id kg4-20020a17090776e400b009e5e4ff01d4sm7563210ejc.129.2023.11.15.15.22.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 15 Nov 2023 15:22:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , =?utf-8?q?In=C3=A8s_Varhol?= , Tyrone Ting , Subbaraya Sundeep , Hao Wu , Felipe Balbi , Gavin Shan , Igor Mammedov , Subbaraya Sundeep , Peter Maydell , Eduardo Habkost , Alistair Francis , Alexandre Iooss , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.0 4/6] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] Date: Thu, 16 Nov 2023 00:21:51 +0100 Message-ID: <20231115232154.4515-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231115232154.4515-1-philmd@linaro.org> References: <20231115232154.4515-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The M2Sxxx SoC family can only be used with Cortex-M3. Propagating the CPU type from the board level is pointless. Hard-code the CPU type at the SoC level. Remove the now ignored MachineClass::default_cpu_type field. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/msf2-soc.h | 3 --- hw/arm/msf2-soc.c | 3 +-- hw/arm/msf2-som.c | 16 ++++++---------- 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index ce417a6266..9300664e8e 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -47,13 +47,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC) #define MSF2_NUM_TIMERS 2 struct MSF2State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ ARMv7MState armv7m; - char *cpu_type; char *part_name; uint64_t envm_size; uint64_t esram_size; diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index b5fe9f364d..d6eb9ec9ac 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -134,7 +134,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 81); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -231,7 +231,6 @@ static Property m2sxxx_soc_properties[] = { * part name specifies the type of SmartFusion2 device variant(this * property is for information purpose only. */ - DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type), DEFINE_PROP_STRING("part-name", MSF2State, part_name), DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE), DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 7b3106c790..ed399223b8 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -47,7 +47,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) DeviceState *dev; DeviceState *spi_flash; MSF2State *soc; - MachineClass *mc = MACHINE_GET_CLASS(machine); DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); qemu_irq cs_line; BusState *spi_bus; @@ -55,20 +54,12 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) MemoryRegion *ddr = g_new(MemoryRegion, 1); Clock *m3clk; - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, &error_fatal); memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); dev = qdev_new(TYPE_MSF2_SOC); qdev_prop_set_string(dev, "part-name", "M2S010"); - qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type); - qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); @@ -106,9 +97,14 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) static void emcraft_sf2_machine_init(MachineClass *mc) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)"; mc->init = emcraft_sf2_s2s010_init; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types = machine_valid_cpu_types; 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Wed, 15 Nov 2023 15:22:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , =?utf-8?q?In=C3=A8s_Varhol?= , Tyrone Ting , Subbaraya Sundeep , Hao Wu , Felipe Balbi , Gavin Shan , Igor Mammedov , Subbaraya Sundeep , Peter Maydell , Eduardo Habkost , Alistair Francis , Alexandre Iooss , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.0 5/6] hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] Date: Thu, 16 Nov 2023 00:21:52 +0100 Message-ID: <20231115232154.4515-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231115232154.4515-1-philmd@linaro.org> References: <20231115232154.4515-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philmd@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The npcm7xx Soc is created with a Cortex-A9 core, see in hw/arm/npcm7xx.c: static void npcm7xx_init(Object *obj) { NPCM7xxState *s = NPCM7XX(obj); for (int i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { object_initialize_child(obj, "cpu[*]", &s->cpu[i], ARM_CPU_TYPE_NAME("cortex-a9")); } The MachineClass::default_cpu_type field is ignored: delete it. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/npcm7xx_boards.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 2aef579aac..98f9af27e7 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -121,15 +121,8 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, uint32_t hw_straps) { NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); - MachineClass *mc = MACHINE_CLASS(nmc); Object *obj; - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with %s", - mc->default_cpu_type); - exit(1); - } - obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", &error_abort, NULL); object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); @@ -462,13 +455,17 @@ static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type) static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; mc->default_ram_id = "ram"; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types = machine_valid_cpu_types; } /* From patchwork Wed Nov 15 23:21:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 744004 Delivered-To: patch@linaro.org Received: by 2002:a5d:5388:0:b0:32d:baff:b0ca with SMTP id d8csp22717wrv; Wed, 15 Nov 2023 15:24:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IFccGr/K2mrO4q0MI3TsV+b43yiO41BpIBcsejhP13YQ32mB31WoLL6W/j+bnUG9tsTkhC4 X-Received: by 2002:a05:6214:558f:b0:672:118e:e368 with SMTP id mi15-20020a056214558f00b00672118ee368mr6947785qvb.24.1700090644361; Wed, 15 Nov 2023 15:24:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700090644; cv=none; d=google.com; s=arc-20160816; b=newn3ZKVwlcTpiG+KIifNYokz+kglPok8xJV2pH+0QPief+T4H6vO5zEYCiR1K+PEg NQbL0fjl1nUGlk2BZkl3e4Vr8fjepJQV8ShRh0bKFe8+bO+J0YqbJ+vBO80W2eo3CPuC OwpwadPqrG+u1FAQH1xG+eCWSq/VWgrIiL3S6FW453w/9S2yIJ1yljspBiK7YhXSuwtR Xzzhdi2bL9wzBwtCqxr8pLv2oOcwPrSSmG+dXN/xRJcGM5Gll71vbQ9sc8aGWtKNbf2w +LAQQ1vvIopAhdJ4tWcL/Dx4CV9eymLQVoj4O84ScN2Sq3OThfelObrZDfJKcwpq4VGZ 7bqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XdaILDX0UTZX18ZacnU/N5Y1jh+ZT87BDkgwEDab2Z8=; fh=uMNkG2qG0zUfNX9Dd8yIHy0nhEp+iUPJbdGoU1GKRvc=; b=GGW9w3EJKpKxQyGXuFauyP/3nkabw1AhBPQti+eeYUxnor8sT5WgmOZEDWZLnzEHn1 OV2VTK7eKj1uAnas4HNxiVIZmi5cWXvfvh6ibPlSDXwaZuKfZL3r9iWcleK2mm0WLs0J PIwBcoC3Q3Ser5kHtcvuMjG/ChyqGV37rAh1ZclyCLgu3rmZuKAiFmGIpye14TZ7StQv AWuaxG5E76UkbMK3iUfmSvTJaFHvUCnWwI6cD59HYqxWvHBnMiww6M/uA+il0VlDnn8J c8BpSCwQI5ziH+LQuTnp9Hm2Fz1nWEcQYejBLZaOCRLDqqg347L1tVwZteKGoCMHTeXs SSIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZBGSnvPT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Our models only use the Cortex-M33. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Remove the now unused MachineClass::default_cpu_type field. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/musca.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 6eeee57c9d..d3658354ba 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -355,7 +355,6 @@ static void musca_init(MachineState *machine) { MuscaMachineState *mms = MUSCA_MACHINE(machine); MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms); - MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *system_memory = get_system_memory(); DeviceState *ssedev; DeviceState *dev_splitter; @@ -366,12 +365,6 @@ static void musca_init(MachineState *machine) assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX); assert(mmc->num_mpcs <= MUSCA_MPC_MAX); - if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); @@ -603,12 +596,16 @@ static void musca_init(MachineState *machine) static void musca_class_init(ObjectClass *oc, void *data) { + static const char *machine_valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); mc->default_cpus = 2; mc->min_cpus = mc->default_cpus; mc->max_cpus = mc->default_cpus; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types = machine_valid_cpu_types; mc->init = musca_init; }