From patchwork Tue Nov 14 14:34:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744320 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8733A41238; Tue, 14 Nov 2023 14:35:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VkbwHHbz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8470EC433C9; Tue, 14 Nov 2023 14:35:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972525; bh=7RNGzDmYQmscIH9JLPqJXNwGek+pQVepVhKqfj7iORk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VkbwHHbz7fjQzXsJP3lTckh1hJCu42SQn+TuyZElCfRdbuIP7gY4OkdM4xXk7XvYh WRE66yFWyBjs3wMwvbD7xK+M7zHB7FnoxOGLBYe2CubLrR68t2RoRr+6cLUhniHIp5 FYEZ0vatiJMXitWnGL6GZ9CWnkJZaNMZbFCDlJmKuj9DIGO50ip6kScIpFlxHIFKG1 VODa7B83QIHM9uLignEw6UmpXTXh0NC1v97EMpqaVt7JD1c+/TBe/QjkHrmDtE8GdC z3pg2I6lUWVtpGaB+AYVnojqobu2BOuie6mE3DYhfa+j3q+aewiJcKes75l0MTkAL5 49Iqlsoce6UoA== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:46 +0000 Subject: [PATCH v2 01/21] arm64/sysreg: Add definition for ID_AA64PFR2_EL1 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-1-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=956; i=broonie@kernel.org; h=from:subject:message-id; bh=7RNGzDmYQmscIH9JLPqJXNwGek+pQVepVhKqfj7iORk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WVg2Ikw3iWITXOqCE07VmNrK4zNx+v3EVj0mup tNa37EyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFlQAKCRAk1otyXVSH0JT9B/ 4o5Zmux0ogG+GcaDp1D5toS82oPts87/6QehL4Q1kQsA5Y9ZLV49ZupmUYCsNcdxzLf578qMJqxTuS UVjC+ZLKBZzWxfw7CpLfwDY4GXrnROS4ViJZgD+4pN9AaJqo9VkCMZ/WjeaAKDMsu0b07jlsQi3e4q f6+qgc/zf9gcNfyRrHnWZOEplu3KiKPGIqEBadPkFqYiB4pDMm2QCWK+fwO4ezIwiPMQMXbXYsyb/N vBo5ro1KZw64ZWUflrcNLeBo+iCcQDtQoqjEP/Xo9dnZVr1D2j2KSCnE7G4NSS0KEDUcW70zYrQKg9 x5vPoFQJ9sPyi42NL66fEryehoPWx/ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 defines a new system register ID_AA64PFR2_EL1 which enumerates FPMR and some new MTE features. Add a definition of this register. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 96cbeeab4eec..f22ade8f1fa7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1002,6 +1002,27 @@ UnsignedEnum 3:0 BT EndEnum EndSysreg +Sysreg ID_AA64PFR2_EL1 3 0 0 4 2 +Res0 63:36 +UnsignedEnum 35:32 FPMR + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 31:12 +UnsignedEnum 11:8 MTEFAR + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 7:4 MTESTOREONLY + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 3:0 MTEPERM + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 Res0 63:60 UnsignedEnum 59:56 F64MM From patchwork Tue Nov 14 14:34:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743908 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DB9741232; Tue, 14 Nov 2023 14:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nyo4/1Oj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AADBDC433CA; Tue, 14 Nov 2023 14:35:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972529; bh=yGEIdovBwYeKe84KQvqQuF6UfRvXTIIewONLZW3lJjY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Nyo4/1Oj6myZfkVLxGcOgXOPbAoI7MtHCdrprtGGcg9eSTOSEdWEkOqZolN8GkkPz DqqjYZdrDCLWf+OpGqqmBVIisSxFS5ZrGhQf3iY1oEVHhEyMhShf3MilpnRvvu8cxC viytEumqXX0oIa66PqMQ6NKZk8q1LrRQFtP3YEmUAOZfzAFeONpWwqqvvWnECB5tSU zloa04j0bloxne7oXpfvuwoeeUYyY5UAVclSKOyy6V9tpJMET2G3csP0dgB8dnV9Q1 498GyuOXpgEcwxonzDzW2MtRWIobYGRy5DasU12BCBkqrjXbSWRF++TgVhUN2vwKNn qJkYuJ6y1ZxzA== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:47 +0000 Subject: [PATCH v2 02/21] arm64/sysreg: Update ID_AA64ISAR2_EL1 defintion for DDI0601 2023-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-2-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1340; i=broonie@kernel.org; h=from:subject:message-id; bh=yGEIdovBwYeKe84KQvqQuF6UfRvXTIIewONLZW3lJjY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WWJyAT1EajJpXBXpEaS53OUF2hv6b0h7gWKmIO 8kBVEz+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFlgAKCRAk1otyXVSH0KsLB/ wNkHc/y+KAanpOQXfWvRli4Zn0MC/CzlXWZAvxItFPIaXxZJ5ryll61hoVQuZG94LJuKMgUY1cG4Lb vpafHI7zqmVuiW5okwEzEVpZVIyFHqqQBYLqJqjpYBkd1/PW1c3nGdpFqqLaoLdSBLiQmLIV+f+le4 NyuV3biiM6OC8cNxteh8skwVQdHBURItpQiAW7jmvctFJVuUPXXGYQai+Bdizx/kbCcfpJ4z0Qkzd3 r6qGtPmfGc0KhCWSsUEpEZ82Y6d3B3iBKVXiG47WepTEYqkY/6yuYaGK9JcufvnBVN87ToMQn5yqCV hkL4oxC5cJmVIeru1AzdyXhC5EAKeR X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 defines some new fields in previously RES0 space in ID_AA64ISAR2_EL1, together with one new enum value. Update the system register definition to reflect this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f22ade8f1fa7..27d79644e1a0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1365,7 +1365,14 @@ EndEnum EndSysreg Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 -Res0 63:56 +UnsignedEnum 63:60 ATS1A + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 59:56 LUT + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 55:52 CSSC 0b0000 NI 0b0001 IMP @@ -1374,7 +1381,19 @@ UnsignedEnum 51:48 RPRFM 0b0000 NI 0b0001 IMP EndEnum -Res0 47:32 +Res0 47:44 +UnsignedEnum 43:40 PRFMSLC + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 39:36 SYSINSTR_128 + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 35:32 SYSREG_128 + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 31:28 CLRBHB 0b0000 NI 0b0001 IMP @@ -1398,6 +1417,7 @@ UnsignedEnum 15:12 APA3 0b0011 PAuth2 0b0100 FPAC 0b0101 FPACCOMBINE + 0b0110 PAUTH_LR EndEnum UnsignedEnum 11:8 GPA3 0b0000 NI From patchwork Tue Nov 14 14:34:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744319 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E989541231; Tue, 14 Nov 2023 14:35:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gk927/WR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9713EC4339A; Tue, 14 Nov 2023 14:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972533; bh=S3NMLYQ19RrEAdoy2+4KbBwGNVT5MhUVc+1BjCfl9/g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gk927/WR5EyKxYCh+Pc9WZW0pJpXPTAJ7h7INrAFmYKpNzXy0QaHuBCJilMqIjnQH Mn38NuP2LsD8pE/xmAvQMSmPP/n40W1kC7o+31ydbHesOG0BvKPuJCKdGiN3hDOlFk w/8r4X/DZsKSPqCPrC6ZaEEM/PVazUEs+YQ+lvaoRZU8/Ib8plBvg1BZ/XItd9oVFi urzu1sja8QR0rr5VLNfpp5GpGjOEAhMERKLWzlZsFaFL2EVki4xByb/OHL9ClpIG5W 7BzgpRIgqqnWfWVOgjwVc0kz/wWtEQA9oM6IIqf6AN+CEB3JjKbe0D1OJIWcbKHB3M GlGMqsCj9+NYQ== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:48 +0000 Subject: [PATCH v2 03/21] arm64/sysreg: Add definition for ID_AA64ISAR3_EL1 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-3-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=883; i=broonie@kernel.org; h=from:subject:message-id; bh=S3NMLYQ19RrEAdoy2+4KbBwGNVT5MhUVc+1BjCfl9/g=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WXRWQJV7DkDAe3fM6c5JrXAGS3X/FV5KJmVmk8 a11Rw7qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFlwAKCRAk1otyXVSH0H8nB/ 49tuCQSBSQtsxS5e0Rae5UXUeHeRSH/3KyXZ7fGq/3lRCdroUjdR7AG1aRnH2tJs+foAMLSM4z6Bkl bbRabcc01HyPjbI5fWZJR0I49QlvtwEb8fqySdTry88YbC3YpY15VB7S6+RWfxb+bGLiGl8yIdAQGf IO2nL9IqH0Uo8i6sq7KbukZPPjvz1vM9BJo5nonurtVtqWND4ASkbYN7Mgwcgxd6roGQrpLvhq4Uo/ eHMdExTsADgJ4+q0jDalXGEQTF4WeyjvS0GMS4UJl6SWyZecI9i+MA/GD1bXF/4dX5Ds8y4mpL2+tO T3gVstZITu1RNs6EpUzDcpsApht+oD X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 adds a new system register ID_AA64ISAR3_EL1 enumerating new floating point and TLB invalidation features. Add a defintion for it. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 27d79644e1a0..3d623a04934c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1433,6 +1433,23 @@ UnsignedEnum 3:0 WFxT EndEnum EndSysreg +Sysreg ID_AA64ISAR3_EL1 3 0 0 6 3 +Res0 63:12 +UnsignedEnum 11:8 TLBIW + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 7:4 FAMINMAX + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 3:0 CPA + 0b0000 NI + 0b0001 IMP + 0b0010 CPA2 +EndEnum +EndSysreg + Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0 UnsignedEnum 63:60 ECV 0b0000 NI From patchwork Tue Nov 14 14:34:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743907 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B883E484; Tue, 14 Nov 2023 14:35:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bFW3jGGr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DFD53C43395; Tue, 14 Nov 2023 14:35:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972536; bh=9pvl6RJ+p+9jph69b/rCGpkJ7MZ4wRu40V+N9vMPcAQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bFW3jGGrX99CyL0qi9olo9EfX11xLdNZ9fEu7dCGbEJmzqnccxQWBJEZbfo6agP0U 1I/GDBwNS4TB59trVs5rlIyYAfXqf6681CuPfrXp20aozLma9Le2XoOhaMzLVdkKct Gkc+Voik1z209A38TYuU0N/c1TZbt/4X+qHSFo81fNrVhwHT5oH+xxbvuB+BPJEnYJ 4ZROoyNgXVZj61JbkKJtFYHSKSYUDQDBKKM/zRlnp10WCiPePmKNaVR8GKriMakDI9 rv+gY2Pq2Bqj5DZ2P153940soaIGbiZX3PfamGCa/aewAngYi4hwD22tOvRC3ycnZ1 UewPB5cADvHnA== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:49 +0000 Subject: [PATCH v2 04/21] arm64/sysreg: Add definition for ID_AA64FPFR0_EL1 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-4-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1020; i=broonie@kernel.org; h=from:subject:message-id; bh=9pvl6RJ+p+9jph69b/rCGpkJ7MZ4wRu40V+N9vMPcAQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WXI0i29C4AWZW/YdvOD1Lh7Tx09sVecB9ewLYw +MdTa+WJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFlwAKCRAk1otyXVSH0AOSB/ 9bMf1Cmxor0PH3zuV67Z5stn5fPhpnE6Hbzy2PO6/Cf+idns/JP6EScwnEM1CadFTBeTA+mGZbzElI 5fnvqB0PE6JyNrmHnJgoHvOFge30QTpfQ8ZcsVBzS8mMSeuLp3jbs770uB7olgd+8FcnFfOry86/wp ZoRcFrP0mKXG/E3t1vxfTVqogS+rXEYWLH4i8AihyT+Iqt1OqrvsarSOrg8GqWBwOghwCMTtW3UPMG gaOY/mkL0FKJx+STQ+TzdGefd+nAtcRLVdCKuNdaKSE7LDJWtcYynryXPCswotihzmXQiLW4rbdYx6 jLAYSF4xsyEmAU+G2Se/Zv/JR27DZt X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 defines a new feature register ID_AA64FPFR0_EL1 which enumerates a number of FP8 related features. Add a definition for it. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 3d623a04934c..c9bb49d0ea03 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1131,6 +1131,35 @@ EndEnum Res0 31:0 EndSysreg +Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 +Res0 63:32 +UnsignedEnum 31 F8CVT + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 30 F8FMA + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 29 F8DP4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 28 F8DP2 + 0b0 NI + 0b1 IMP +EndEnum +Res0 27:2 +UnsignedEnum 1 F8E4M3 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 0 F8E5M2 + 0b0 NI + 0b1 IMP +EndEnum +EndSysreg + Sysreg ID_AA64DFR0_EL1 3 0 0 5 0 Enum 63:60 HPMN0 0b0000 UNPREDICTABLE From patchwork Tue Nov 14 14:34:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744318 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE11B3FE2C; Tue, 14 Nov 2023 14:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PnSStsPA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 187CFC433CD; Tue, 14 Nov 2023 14:35:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972539; bh=W6NILgEt2d5dF4rtCICDrMO+KDYmPRbi2cIO83aqtdM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PnSStsPA2cgYrHi5FDsSH3S/3kGThJYhLVmpsngs3QYTxoITH/VpGSrTqbT3J422j h7k9W390Tcn5dTFar3Qc7SCDSLtggHuivb9tjLyI8BD8AdeSACjKEpKyv4hak4SREA cY8JmL1/xDU8uoIY1BaozTDj87focnidxQu+yUNG2jXbAOn7l1pCBzXdsYazKCARdO 3hnun6V+sR+Zk74uCy77rhPHK2aaW0NW02wsxtg/T8kzt/FpsnVAZFDlzzZL+6Eb5Q JxVpoolHbjnx++pG9Om2QzqdUchzjLY3Y2H9nIIbub0PC0aYE+fi4XwA+Kkk+ONwfq jSPtmjbO1N3Cg== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:50 +0000 Subject: [PATCH v2 05/21] arm64/sysreg: Update ID_AA64SMFR0_EL1 definition for DDI0601 2023-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-5-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1275; i=broonie@kernel.org; h=from:subject:message-id; bh=W6NILgEt2d5dF4rtCICDrMO+KDYmPRbi2cIO83aqtdM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WY4LJ3zW0Njv0NlTJy7v8HYTzo6HIUyrg3DyeQ +CAvzPiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFmAAKCRAk1otyXVSH0FIVB/ 9BIqFDzBtxuWhtbQOuFi6+eNGWMJx4iMowyvGz63y8VgUS9cZeux0IVqrLoDcwMbrm+1DwQAdfacr6 789/QCJQanP9LK/vkGPuFI402nyKT4M2KuDn5a3uGINMNOx0RAWSzlPZClTPhF7khd5kNjEtCwLfrV TmJY7+Ws21dMvU06SO5WEThROgwMkxm5wikcV2ZftSfDGMCe81g5hfHcxPfpFPdhu02DnESnta7GpX 2kD/rvYklk/0x3fzupXEzIxqbyd+J6tlub1BZoPcRPzW1AFJRtJjuIbAhaoXT6cVm06QfmreQjqnOm lFO9XIGGDykqZhFjgkM3hRal3cBxpG X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023-09 release of DDI0601 defines a number of new feature enumeration fields in ID_AA64SMFR0_EL1. Add these fields. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c9bb49d0ea03..aee9ab4087c1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1079,7 +1079,11 @@ UnsignedEnum 63 FA64 0b0 NI 0b1 IMP EndEnum -Res0 62:60 +Res0 62:61 +UnsignedEnum 60 LUTv2 + 0b0 NI + 0b1 IMP +EndEnum UnsignedEnum 59:56 SMEver 0b0000 SME 0b0001 SME2 @@ -1107,7 +1111,14 @@ UnsignedEnum 42 F16F16 0b0 NI 0b1 IMP EndEnum -Res0 41:40 +UnsignedEnum 41 F8F16 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 40 F8F32 + 0b0 NI + 0b1 IMP +EndEnum UnsignedEnum 39:36 I8I32 0b0000 NI 0b1111 IMP @@ -1128,7 +1139,20 @@ UnsignedEnum 32 F32F32 0b0 NI 0b1 IMP EndEnum -Res0 31:0 +Res0 31 +UnsignedEnum 30 SF8FMA + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 29 SF8DP4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 28 SF8DP2 + 0b0 NI + 0b1 IMP +EndEnum +Res0 27:0 EndSysreg Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 From patchwork Tue Nov 14 14:34:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743906 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66C5841229; Tue, 14 Nov 2023 14:35:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F2qsC+hY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3F851C433CA; Tue, 14 Nov 2023 14:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972542; bh=tnXYFwh5n0qNcsRXurtqbaVARrY3vmLHqYkv+SC46VU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F2qsC+hYRzp+zkl0cu+7wANu/Kg6DJ2+Osfeb6Y+ZhcNB6ONN5g2kBsYqSheH3/dZ rBh1J3R7SgBi6FZqPVGP6hrdc7d+pp2ERrMxqAnYaTRxWJ+cqmIwTN3Ric5QDaRjWR 142cPWHrRfwVVbwl3bG6byEhgC0ZItoVBjQAdvzym/WfyieIcDENl4eGbbRq6GsY9j SJwuNdrX0Irs9KAXol/8m6x+JN0mJQd5BzYxQcuit4DK6Vo7DWJX+IVE3rGA8U6Bvl oVWGN3SJheOAfGXuvQjEDNS1dcWzsEAqI0CsbleL8PRFMUDQVi3NSPi3vkv3ZY3FUR hijiL1ASziW5g== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:51 +0000 Subject: [PATCH v2 06/21] arm64/sysreg: Update SCTLR_EL1 for DDI0601 2023-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-6-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=817; i=broonie@kernel.org; h=from:subject:message-id; bh=tnXYFwh5n0qNcsRXurtqbaVARrY3vmLHqYkv+SC46VU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WZQLjjlJnDG6sLMYbbDE8khFwcKUOr3r1xSwhg Tn3j2uGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFmQAKCRAk1otyXVSH0HacB/ 4tdRseQb8KW8QSZ53F1aeLRN6HJJXEqHZvfffd8e9793kNW1hft7Gk05vbS3TkhjaVk3cqcb9F8PzB RpAb6DOkvap2BBdh2gkIHqEBbZe+Pcr9Xrzj5N9eEO5eoDBBPDuDSaNPAISwM13AaibLrXJv8wxaFP hPBMG6G7WWvnC1jOTJnnl5Ae3WSYfzkKIsRnaRjK4vOxgNNGQajMYUqWv7p52pH9q2HESPzgkaGKBC MFhC+vLmO/zZuDCRL6tEuwE3BqvYwgpRBxV4RN1dGwUTHNEhDf51tRnbFnVZV6DUJyC9rW/LITIxQx hjUJSZY1PbZiioeGwZ/+8yC8OPxMn8 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 defines some new fields in SCTLR_EL1 controlling new MTE and floating point features. Update our sysreg definition to reflect these. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index aee9ab4087c1..eea69bb48fa7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1791,7 +1791,8 @@ Field 63 TIDCP Field 62 SPINTMASK Field 61 NMI Field 60 EnTP2 -Res0 59:58 +Field 59 TCSO +Field 58 TCSO0 Field 57 EPAN Field 56 EnALS Field 55 EnAS0 @@ -1820,7 +1821,7 @@ EndEnum Field 37 ITFSB Field 36 BT1 Field 35 BT0 -Res0 34 +Field 34 EnFPM Field 33 MSCEn Field 32 CMOW Field 31 EnIA From patchwork Tue Nov 14 14:34:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744317 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95DC241227; Tue, 14 Nov 2023 14:35:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AmlkUwAW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64E02C433B7; Tue, 14 Nov 2023 14:35:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972546; bh=BQwIlG0oOgH2zbKU3AwqILoaXU3JMfSvJqswNhTlD0w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AmlkUwAWO2XqB5Mupah1fuEkJfhJfVXANP0fSOIWheOkkVyEjYgz9j3yvniTaEqo4 Ry/qFI+imv6qgGXpOBByNfMkimEZKWOhV3FsiuTfmz5th39laHGXiEr2oVZw+e15vS EtZ26tvBObAmimNESFpf86DUkEiNBu0yN4EUnUTJ2f+ruHKJSCUH5px2P6xwl10VyY GavVQiOgexaYYyA7A4mgnR1FO8y8usaViy6rShuWdbth9CqRate8QOQjPMpp8l6fKj tXEJ3H/I2loXBwCWGEmSxjZEf1j3aKquS7WnOX7QXEfgoZRPj8NwMeYQIKRmXmvhez SwKH5B7uYA/gA== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:52 +0000 Subject: [PATCH v2 07/21] arm64/sysreg: Update HCRX_EL2 definition for DDI0601 2023-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-7-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=666; i=broonie@kernel.org; h=from:subject:message-id; bh=BQwIlG0oOgH2zbKU3AwqILoaXU3JMfSvJqswNhTlD0w=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WaHe/+M/b5X9jP1rg5p8morKdu1D8EE6Ahjim2 yAvg02yJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFmgAKCRAk1otyXVSH0J+2B/ 40ib/oULdd/d9oZVEuawOWDa+pD4lu3zatx1xVBQOmZy4xvOcIiLzhjp8vhx2C7aLHPkRYpIm9t0n0 TCcHEMnJdWHJTLn6ovctmFh9B3ERG4KJ3n9ZkB2UTnMfxe7VGSFsVu4H7i3r0kmwIXzrqAQbxuis5E acPfNP0zEi+QM7eIrsTYq5TgIel0icPITsGchgTknOC89jSdgJ5xQHwlBGgbaaxUxLSPxMONxajjDR gRTbVr+wEkvkQ0HaFv7Ef7qQP+U1KvsRmaZGQTNEYa6Vdz++KvgMUO11ClQkFvs3jUsRhUYcgTKj0m LnS+mw+o0eDK+3veaphPvBhj2vW4Lf X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 defines new fields in HCRX_EL2 controlling access to new system registers, update our definition of HCRX_EL2 to reflect this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index eea69bb48fa7..0b1a33a77074 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2412,7 +2412,9 @@ Fields ZCR_ELx EndSysreg Sysreg HCRX_EL2 3 4 1 2 2 -Res0 63:23 +Res0 63:25 +Field 24 PACMEn +Field 23 EnFPM Field 22 GCSEn Field 21 EnIDCP128 Field 20 EnSDERR From patchwork Tue Nov 14 14:34:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743905 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2DFB4121F; Tue, 14 Nov 2023 14:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u8EGpCwP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85FD6C433A9; Tue, 14 Nov 2023 14:35:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972549; bh=TRfwOBP1ct8dRqN5onbbksp9izfKksijyA3SFS57tL8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=u8EGpCwP2YDwTsdhnCuWNRR3ET4cBwlGPOMNDjDi7MyBerlIwMvfr9/Re4WP+Tu2W E3r0tuz9FDWCe5vZRDtnbDwxgtWbVlHa7lriiZOEKRO2bouvvisBzdJ9/1FSIYgS8A nKlvuw1wMHtsutJX74iVJNWv59Angpc0RmjXhL0g9Uem9qclL190adwrdcTzIsLNbS Wf2ANZgx3bCFFKHdKUiga7bbgvbxwa9ZZ7ajEfw2wMTnvxVBtmp20IiwYoo21YJNzO wAKSSEqc09xkvffhauB6TRhdv+aPi/m81q2iBRwZ4iedMGidiu423066hgGRzHapRO 71e5nUyBmf1Gw== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:53 +0000 Subject: [PATCH v2 08/21] arm64/sysreg: Add definition for FPMR Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-8-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=975; i=broonie@kernel.org; h=from:subject:message-id; bh=TRfwOBP1ct8dRqN5onbbksp9izfKksijyA3SFS57tL8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WbxAeU82L4RUHrAd9Oxy2f0PMZPzQhBtz2zavq mLdMhCOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFmwAKCRAk1otyXVSH0H1GB/ wPSxydoLDmEph6vxq4HTgSiwCFR5ow+x1m0GsC/hw4ixQz4T6U8KuOY/T5Rl6r9rBYyBegyWmsezp9 qb/bGB2w2sNU0Ixiiq9tUd9X/MaJLWzJ52D4WjQPLEIyRCU9+Mmvvd7CJm/ZKhwtTQ15ZWiyDHfmwu o9RLCcAiwDzmoFwuYD7vJjLGJOtcfJ/dY3G4quJkRPHIbgt3IubEYivPU+5q6pL3SIwUYIaNbRU0KY KFLXbNmJNNJKEx1dEDkGQwnm1osxKtzuhwg9jMtSC+UPqBSAGkLkyHrr7NhcGh/KrFqCGqNiA+F4ZX NbONDrwLeCffjD/8nRdaIrn19O5O3h X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2023-09 defines a new sysrem register FPMR (Floating Point Mode Register) which configures the new FP8 features. Add a definition of this register. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0b1a33a77074..67173576115a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2138,6 +2138,29 @@ Field 1 ZA Field 0 SM EndSysreg +Sysreg FPMR 3 3 4 4 2 +Res0 63:38 +Field 37:32 LSCALE2 +Field 31:24 NSCALE +Res0 23 +Field 22:16 LSCALE +Field 15 OSC +Field 14 OSM +Res0 13:9 +UnsignedEnum 8:6 F8D + 0b000 E5M2 + 0b001 E4M3 +EndEnum +UnsignedEnum 5:3 F8S2 + 0b000 E5M2 + 0b001 E4M3 +EndEnum +UnsignedEnum 2:0 F8S1 + 0b000 E5M2 + 0b001 E4M3 +EndEnum +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 From patchwork Tue Nov 14 14:34:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744316 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85A484121A; Tue, 14 Nov 2023 14:35:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F9qS4cNY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A663BC433B9; Tue, 14 Nov 2023 14:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972552; bh=eZaW7Q4M/zzv5URqk5Jj7aBPK/YCTtlJ1HieBEOkpao=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F9qS4cNYbmzk9CRD6I1kPZKHC55oQxPorNN4MjGLqUUzu4rd9kc34C0K9+ecjB60c 5rmZdt/jC+2Um8aR3019vjqiiXBcxJQ3sYcN07cE8yUR4Lgd21jjmlNsMM0Ccb6qVo 7UQ5UKlycZbLz5QASOR6SPVjI77leds3Q1bHy61jxt2JdIGF7rK7rrd+pA58jSyHFN ROMq4kC+uXUiI7cDdwbLGBE1LgAiK7mV2GY3s/TryAeV45iLjvIBedjO7k2t0SkzXI 7/SgJ4C2ZlmT3xljSKXHNAjI+j2yYFXjmm5S3hy3j3crbU1N4URsQxDktC8o9jBpUk GJyWDYJrx+m7A== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:54 +0000 Subject: [PATCH v2 09/21] arm64/cpufeature: Hook new identification registers up to cpufeature Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-9-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=7888; i=broonie@kernel.org; h=from:subject:message-id; bh=eZaW7Q4M/zzv5URqk5Jj7aBPK/YCTtlJ1HieBEOkpao=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4Wboob+aN212olICG31A2T4E/iZQdufTXtP+L/a 6WBz/MWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFmwAKCRAk1otyXVSH0DrKB/ 9eMgz51jPlNWTFwaHt9t5/kYA6OPCJPH9tbByrkoUFrcq2Fh1uK6lOCbtVLzULmczakiMffQmz4Gq8 kVQZiekNfDUvPUJzfMCKCwHpTFjY2X8MKkcwU0AAyrTkzcEKgxlVhlitzaFELsw3o3d7F94IsILdMo ZDwWNyId6qUBmknicwCX6mVvSNEiWl1EI1x2x9siQG6PZP8FlOF8NC8Lf1KKVN3b7K7bgEGlEqtx++ 8fZwYZ2SJlfClxSGJLcwhBDIMra/13oVCARioTogmzckk9h/lQAqG7q03aWoSJlifsbEbMvontBWVV W9CxKD5hfAzRXWBd0LD9CpJUJ+9WkQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023 architecture extensions have defined several new ID registers, hook them up to the cpufeature code so we can add feature checks and hwcaps based on their contents. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpu.h | 3 +++ arch/arm64/kernel/cpufeature.c | 28 ++++++++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 3 +++ 3 files changed, 34 insertions(+) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index f3034099fd95..b99138bc3d4a 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -53,14 +53,17 @@ struct cpuinfo_arm64 { u64 reg_id_aa64isar0; u64 reg_id_aa64isar1; u64 reg_id_aa64isar2; + u64 reg_id_aa64isar3; u64 reg_id_aa64mmfr0; u64 reg_id_aa64mmfr1; u64 reg_id_aa64mmfr2; u64 reg_id_aa64mmfr3; u64 reg_id_aa64pfr0; u64 reg_id_aa64pfr1; + u64 reg_id_aa64pfr2; u64 reg_id_aa64zfr0; u64 reg_id_aa64smfr0; + u64 reg_id_aa64fpfr0; struct cpuinfo_32bit aarch32; }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 646591c67e7a..c8d38e5ce997 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -234,6 +234,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), @@ -267,6 +271,10 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), @@ -319,6 +327,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), @@ -702,10 +714,12 @@ static const struct __ftr_reg_entry { &id_aa64pfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, &id_aa64pfr1_override), + ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, &id_aa64zfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, &id_aa64smfr0_override), + ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), /* Op1 = 0, CRn = 0, CRm = 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), @@ -717,6 +731,7 @@ static const struct __ftr_reg_entry { &id_aa64isar1_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, &id_aa64isar2_override), + ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), /* Op1 = 0, CRn = 0, CRm = 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), @@ -1043,14 +1058,17 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); + init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); + init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); + init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) init_32bit_cpu_features(&info->aarch32); @@ -1291,6 +1309,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64isar1, boot->reg_id_aa64isar1); taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, info->reg_id_aa64isar2, boot->reg_id_aa64isar2); + taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, + info->reg_id_aa64isar3, boot->reg_id_aa64isar3); /* * Differing PARange support is fine as long as all peripherals and @@ -1310,6 +1330,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); + taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, + info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); @@ -1317,6 +1339,9 @@ void update_cpu_features(int cpu, taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); + taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, + info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); + /* Probe vector lengths */ if (IS_ENABLED(CONFIG_ARM64_SVE) && id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { @@ -1429,8 +1454,10 @@ u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64PFR0_EL1); read_sysreg_case(SYS_ID_AA64PFR1_EL1); + read_sysreg_case(SYS_ID_AA64PFR2_EL1); read_sysreg_case(SYS_ID_AA64ZFR0_EL1); read_sysreg_case(SYS_ID_AA64SMFR0_EL1); + read_sysreg_case(SYS_ID_AA64FPFR0_EL1); read_sysreg_case(SYS_ID_AA64DFR0_EL1); read_sysreg_case(SYS_ID_AA64DFR1_EL1); read_sysreg_case(SYS_ID_AA64MMFR0_EL1); @@ -1440,6 +1467,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64ISAR0_EL1); read_sysreg_case(SYS_ID_AA64ISAR1_EL1); read_sysreg_case(SYS_ID_AA64ISAR2_EL1); + read_sysreg_case(SYS_ID_AA64ISAR3_EL1); read_sysreg_case(SYS_CNTFRQ_EL0); read_sysreg_case(SYS_CTR_EL0); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index a257da7b56fe..8322e968fd0d 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -448,14 +448,17 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); + info->reg_id_aa64isar3 = read_cpuid(ID_AA64ISAR3_EL1); info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1); info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); + info->reg_id_aa64pfr2 = read_cpuid(ID_AA64PFR2_EL1); info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); + info->reg_id_aa64fpfr0 = read_cpuid(ID_AA64FPFR0_EL1); if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) info->reg_gmid = read_cpuid(GMID_EL1); From patchwork Tue Nov 14 14:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743904 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A558941231; Tue, 14 Nov 2023 14:35:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SEGdzbC7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9683C43395; Tue, 14 Nov 2023 14:35:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972555; bh=+jSB6ryQw/tAoaW0f6Dn8f5r/j3Y5hYXa/dEZzeKHsY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SEGdzbC7b3wvMV/Ivzh+9pjvZ4JIMa9KlE7jQa6b4P2pa6rq17+x3do5ktJq1XLux 7T4GgVQV7XbbzuW7I2oE2Q1GisQDn5s60Zm9L3lSQruv90HXyNcPZRO98vranKE7l2 /GrQfWQYcZjvSQUQGvLmKA+UQt+ba+dAoAnpU2Up9slFFsWZJiYEBrBEIsxsQZGNrJ DxNdqxvl+v1I8aIMm2OKN44VvNMGy752EsPi39uSdacKE8uDorHkb/u9pEjBsDRrAD 8gqTuFsq5dcoH2Xpq+C6lSGdEw9sW8wZvPS4wRmKOXjCUjZGbBj64nFj7lUQKALnli AeCR4q53PRrdA== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:55 +0000 Subject: [PATCH v2 10/21] arm64/fpsimd: Enable host kernel access to FPMR Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-10-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1057; i=broonie@kernel.org; h=from:subject:message-id; bh=+jSB6ryQw/tAoaW0f6Dn8f5r/j3Y5hYXa/dEZzeKHsY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WcKwT165mW8oQVRPIaZv68B/WwcA+JzKzLOCir kQlxz5+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFnAAKCRAk1otyXVSH0GMdB/ 4+cijMYPYrqufsdKVq1iYT/G7uPwkXJ9/l3VF+dAG1JOHxhY2b2Ce8RiIKiql/X7QgixZvMO/M/zOM ZPIUX4CV0DhhyCv0dry+chuyfHmZKstJzsDz4jyryyx+szv4am5GwIGJHOHVKQ/JoSK4k/SRMyKR4q U7TJe73E+13UCeTitrIqV6D2gDqr7SqeRungofG3SkzDPWAQb4givyRUVEyAWPEukXji4V58e40LzE mgNS18Eb0F4D4Ih3su5c+Ejb3IF390ueKDQJLFs6HKKcR82E589lXZnquLKvpuP4hHV/KUWZ28+PY2 8jL/aO44ctaIzBymlrA1ZBmmRoqanD X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_FPMR provides a new generally accessible architectural register FPMR. This is only accessible to EL0 and EL1 when HCRX_EL2.EnFPM is set to 1, do this when the host is running. The guest part will be done along with context switching the new register and exposing it via guest management. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index b85f46a73e21..9f9239d86900 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -105,7 +105,7 @@ #define HCRX_GUEST_FLAGS \ (HCRX_EL2_SMPME | HCRX_EL2_TCR2En | \ (cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn | HCRX_EL2_MCE2) : 0)) -#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En) +#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) /* TCR_EL2 Registers bits */ #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) From patchwork Tue Nov 14 14:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744315 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFCDB41232; Tue, 14 Nov 2023 14:35:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="izmal1NH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EEAEEC433B8; Tue, 14 Nov 2023 14:35:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972558; bh=8aMhtvWd2U4DgD7OsoWitXafC2Gl0m4G3yGyGq+lQbA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=izmal1NHUcXM258SsY7CAzau7r6omqtbcTWKpJdC7aNgAVS3wrhLv+5d1qme3QBcP IDgnF+/e3KKUiJsrpQB+G0BQpViD9QrnWLxd1vJkxr4IF+Cc2UxrQVBBBYAdRzgekl TBhxtyvL/TAKKWDfa2JsEq0fX9HzMo37VjwFhYZfxAte56nQmMyQKXdl94pePo8jep SHAODwykmnw1G5IZvdajPAjbFZDw9NWo82ItDbjOGMaPZgzmtvGlspacxfazJG+bbc 7aifuiDNRn3XgQ9hGh6NE+Mrps1yes87cQnWH/zXD9IMD5YEWT2rHWM0r45XijTnAx EA0KdNEMD+24w== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:56 +0000 Subject: [PATCH v2 11/21] arm64/fpsimd: Support FEAT_FPMR Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-11-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=6717; i=broonie@kernel.org; h=from:subject:message-id; bh=8aMhtvWd2U4DgD7OsoWitXafC2Gl0m4G3yGyGq+lQbA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WdDpPp66HYRzBr0f+t44qJWTRJ4dFjYjTu+Ix5 R50HEVmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFnQAKCRAk1otyXVSH0G/GB/ 9c1CgTjCIp7wxd/CTP4ABHWi2Q4r+evaJgH2ZXNpQhXoEbYq1xymDugpOzV77r3qEmqu9nUmtngDbM vGpaLI1BNZWpxArTK34GBWE0qr2VlDLZ5PuM90YYgiSpOsZwdsx7klRB3eFn4LbsxecMZ91C3wWwM1 mPncgP4C6izwTvnYgnSeZN72flPrV7uOsB+JDzCgtApARTNHj/di5stJnP/D4VrOafeSzjXDMv8aZP 8iYkyibvoU6BFE7xs8EKE/TBvqSbTF+Tn1wTUhZJYXukIZcN515b1SSBh8z1Gi6VOQPdVNIhNRg61c 7XF5lNhKGZ2NOEuMjsdNGOrpzXY6bm X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_FPMR defines a new EL0 accessible register FPMR use to configure the FP8 related features added to the architecture at the same time. Detect support for this register and context switch it for EL0 when present. Due to the sharing of responsibility for saving floating point state between the host kernel and KVM FP8 support is not yet implemented in KVM and a stub similar to that used for SVCR is provided for FPMR in order to avoid bisection issues. To make it easier to share host state with the hypervisor we store FPMR immediately after the base floating point state, existing usage means that it is not practical to extend that directly. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 5 +++++ arch/arm64/include/asm/fpsimd.h | 2 ++ arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/processor.h | 2 ++ arch/arm64/kernel/cpufeature.c | 9 +++++++++ arch/arm64/kernel/fpsimd.c | 13 +++++++++++++ arch/arm64/kvm/fpsimd.c | 1 + arch/arm64/tools/cpucaps | 1 + 8 files changed, 34 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f6d416fe49b0..8e83cb1e6c7c 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -767,6 +767,11 @@ static __always_inline bool system_supports_tpidr2(void) return system_supports_sme(); } +static __always_inline bool system_supports_fpmr(void) +{ + return alternative_has_cap_unlikely(ARM64_HAS_FPMR); +} + static __always_inline bool system_supports_cnp(void) { return alternative_has_cap_unlikely(ARM64_HAS_CNP); diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 50e5f25d3024..74afca3bd312 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -89,6 +89,7 @@ struct cpu_fp_state { void *sve_state; void *sme_state; u64 *svcr; + u64 *fpmr; unsigned int sve_vl; unsigned int sme_vl; enum fp_type *fp_type; @@ -154,6 +155,7 @@ extern void cpu_enable_sve(const struct arm64_cpu_capabilities *__unused); extern void cpu_enable_sme(const struct arm64_cpu_capabilities *__unused); extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused); extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused); +extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused); extern u64 read_smcr_features(void); diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 824f29f04916..f8d98985a39c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -517,6 +517,7 @@ struct kvm_vcpu_arch { enum fp_type fp_type; unsigned int sve_max_vl; u64 svcr; + u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index e5bc54522e71..dd3a5b29f76e 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -158,6 +158,8 @@ struct thread_struct { struct user_fpsimd_state fpsimd_state; } uw; + u64 fpmr; /* Adjacent to fpsimd_state for KVM */ + enum fp_type fp_type; /* registers FPSIMD or SVE? */ unsigned int fpsimd_cpu; void *sve_state; /* SVE registers, if any */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c8d38e5ce997..ea0b680792de 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -272,6 +272,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2759,6 +2760,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) }, + { + .desc = "FPMR", + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .capability = ARM64_HAS_FPMR, + .matches = has_cpuid_feature, + .cpu_enable = cpu_enable_fpmr, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) + }, {}, }; diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 1559c706d32d..2a6abd6423f7 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -385,6 +385,9 @@ static void task_fpsimd_load(void) WARN_ON(!system_supports_fpsimd()); WARN_ON(!have_cpu_fpsimd_context()); + if (system_supports_fpmr()) + write_sysreg_s(current->thread.fpmr, SYS_FPMR); + if (system_supports_sve() || system_supports_sme()) { switch (current->thread.fp_type) { case FP_STATE_FPSIMD: @@ -472,6 +475,9 @@ static void fpsimd_save(void) if (test_thread_flag(TIF_FOREIGN_FPSTATE)) return; + if (system_supports_fpmr()) + *(last->fpmr) = read_sysreg_s(SYS_FPMR); + /* * If a task is in a syscall the ABI allows us to only * preserve the state shared with FPSIMD so don't bother @@ -714,6 +720,12 @@ static void sve_to_fpsimd(struct task_struct *task) } } +void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__always_unused p) +{ + write_sysreg_s(read_sysreg_s(SYS_SCTLR_EL1) | SCTLR_EL1_EnFPM_MASK, + SYS_SCTLR_EL1); +} + #ifdef CONFIG_ARM64_SVE /* * Call __sve_free() directly only if you know task can't be scheduled @@ -1671,6 +1683,7 @@ static void fpsimd_bind_task_to_cpu(void) last->sve_vl = task_get_sve_vl(current); last->sme_vl = task_get_sme_vl(current); last->svcr = ¤t->thread.svcr; + last->fpmr = ¤t->thread.fpmr; last->fp_type = ¤t->thread.fp_type; last->to_save = FP_STATE_CURRENT; current->thread.fpsimd_cpu = smp_processor_id(); diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 8c1d0d4853df..e3e611e30e91 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -153,6 +153,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; fp_state.svcr = &vcpu->arch.svcr; + fp_state.fpmr = &vcpu->arch.fpmr; fp_state.fp_type = &vcpu->arch.fp_type; if (vcpu_has_sve(vcpu)) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index b98c38288a9d..7a249a950bbc 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -26,6 +26,7 @@ HAS_ECV HAS_ECV_CNTPOFF HAS_EPAN HAS_EVT +HAS_FPMR HAS_FGT HAS_FPSIMD HAS_GENERIC_AUTH From patchwork Tue Nov 14 14:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743903 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFC3E41231; Tue, 14 Nov 2023 14:36:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Glzj0v12" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D3F5C433C7; Tue, 14 Nov 2023 14:35:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972561; bh=qb52W/FnN/1SulYmCofB+kYw3kMDdBBbntUr0aosnTs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Glzj0v120aflxdYnHPfQd5su3t1oeElorZGM5ygd7L7vJOE02ndlcmY7Cy6kGduK1 sdaA9Torg1JX33/HErdM00gVUc4Yqh/YMSPrxgx1yyJYjTekPWbpxdSrVpKBzOm12h +xNaiPXCX+z8QsfRWw7uTr/lNm8LBpGETZuesV83fMfGTZFpbdAEDzfUhgZPuNdJF+ 3iHql5yIDkbFKLHB8Uh+KswIvKxkQFV2BvcydwFCjFaPlcsXcwvxYrVWSJIuGtha23 4Jjenpr+FEIxqd2UaiV/rr+IQjHTR61Wwr0YYtVknPgcdELOHNHJg6VikSRA6wAsBu mzJSIXsVsu1ew== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:57 +0000 Subject: [PATCH v2 12/21] arm64/signal: Add FPMR signal handling Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-12-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=4170; i=broonie@kernel.org; h=from:subject:message-id; bh=qb52W/FnN/1SulYmCofB+kYw3kMDdBBbntUr0aosnTs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WeFMLwbe9KIbWdJ3rpZTtwz0hq1SldLKGbW2Vu EfVeOvKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFngAKCRAk1otyXVSH0AzJB/ 4uGbb9V7V0/YWxM9klilQspJUf+w7iLUUTCI7xqcc18nZ/Wz/cFF9nv6RkpZaeFY/SAwefA7DHfx4Z QMCbzIe9X5pipNbiJG9HikTVwmhlVT2yzH+594uYvZIOEZyFdXMRlMB2VXaAxYcTBJxhM1YevpTpGI BUUwXb16OWpcplqKe0tnS/hNUCA0bJinbG1SBNxIyWQp/lT6ZWoYUoz3rMbkyAuli4QZ3VCVj034oD DWPz9KsvWTkw83VNreAjayLOafHUIaPmYFyzcNxGpFopnKUQ6BDyQXV+ASga8MHsn5DC9tePVrZbp7 OmrqJxLZH65ixKJ57BEe3LjihqK3DM X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Expose FPMR in the signal context on systems where it is supported. The kernel validates the exact size of the FPSIMD registers so we can't readily add it to fpsimd_context without disruption. Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/sigcontext.h | 8 +++++ arch/arm64/kernel/signal.c | 59 ++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index f23c1dc3f002..8a45b7a411e0 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -152,6 +152,14 @@ struct tpidr2_context { __u64 tpidr2; }; +/* FPMR context */ +#define FPMR_MAGIC 0x46504d52 + +struct fpmr_context { + struct _aarch64_ctx head; + __u64 fpmr; +}; + #define ZA_MAGIC 0x54366345 struct za_context { diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 0e8beb3349ea..e8c808afcc8a 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -60,6 +60,7 @@ struct rt_sigframe_user_layout { unsigned long tpidr2_offset; unsigned long za_offset; unsigned long zt_offset; + unsigned long fpmr_offset; unsigned long extra_offset; unsigned long end_offset; }; @@ -182,6 +183,8 @@ struct user_ctxs { u32 za_size; struct zt_context __user *zt; u32 zt_size; + struct fpmr_context __user *fpmr; + u32 fpmr_size; }; static int preserve_fpsimd_context(struct fpsimd_context __user *ctx) @@ -227,6 +230,33 @@ static int restore_fpsimd_context(struct user_ctxs *user) return err ? -EFAULT : 0; } +static int preserve_fpmr_context(struct fpmr_context __user *ctx) +{ + int err = 0; + + current->thread.fpmr = read_sysreg_s(SYS_FPMR); + + __put_user_error(FPMR_MAGIC, &ctx->head.magic, err); + __put_user_error(sizeof(*ctx), &ctx->head.size, err); + __put_user_error(current->thread.fpmr, &ctx->fpmr, err); + + return err; +} + +static int restore_fpmr_context(struct user_ctxs *user) +{ + u64 fpmr; + int err = 0; + + if (user->fpmr_size != sizeof(*user->fpmr)) + return -EINVAL; + + __get_user_error(fpmr, &user->fpmr->fpmr, err); + if (!err) + write_sysreg_s(fpmr, SYS_FPMR); + + return err; +} #ifdef CONFIG_ARM64_SVE @@ -590,6 +620,7 @@ static int parse_user_sigframe(struct user_ctxs *user, user->tpidr2 = NULL; user->za = NULL; user->zt = NULL; + user->fpmr = NULL; if (!IS_ALIGNED((unsigned long)base, 16)) goto invalid; @@ -684,6 +715,17 @@ static int parse_user_sigframe(struct user_ctxs *user, user->zt_size = size; break; + case FPMR_MAGIC: + if (!system_supports_fpmr()) + goto invalid; + + if (user->fpmr) + goto invalid; + + user->fpmr = (struct fpmr_context __user *)head; + user->fpmr_size = size; + break; + case EXTRA_MAGIC: if (have_extra_context) goto invalid; @@ -806,6 +848,9 @@ static int restore_sigframe(struct pt_regs *regs, if (err == 0 && system_supports_tpidr2() && user.tpidr2) err = restore_tpidr2_context(&user); + if (err == 0 && system_supports_fpmr() && user.fpmr) + err = restore_fpmr_context(&user); + if (err == 0 && system_supports_sme() && user.za) err = restore_za_context(&user); @@ -928,6 +973,13 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, } } + if (system_supports_fpmr()) { + err = sigframe_alloc(user, &user->fpmr_offset, + sizeof(struct fpmr_context)); + if (err) + return err; + } + return sigframe_alloc_end(user); } @@ -983,6 +1035,13 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user, err |= preserve_tpidr2_context(tpidr2_ctx); } + /* FPMR if supported */ + if (system_supports_fpmr() && err == 0) { + struct fpmr_context __user *fpmr_ctx = + apply_user_offset(user, user->fpmr_offset); + err |= preserve_fpmr_context(fpmr_ctx); + } + /* ZA state if present */ if (system_supports_sme() && err == 0 && user->za_offset) { struct za_context __user *za_ctx = From patchwork Tue Nov 14 14:34:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744314 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2656C41227; Tue, 14 Nov 2023 14:36:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KEYsetiV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 42084C433D9; Tue, 14 Nov 2023 14:36:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972565; bh=2lwb/HSWzM5tgdqcRY+V9adtYXXgaHL2EUDsgIl8iAQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KEYsetiV6MaKRvSP2qTYGyOt6FTXMtZHH5rnhGvGeHym+yDLW2n7f3qK/gLamETzg G+QO8rMtRiQMm2avjkoPSJbDf/AK1cy4amP7GlfQouAoj+dBb+MFHHuKSaF2/9EEAv 45Rht04crG3HYhTOPB3vpLINSm+9Bu2R4gedci/AJs7vo2mXBrI3X9FjRUrDowcatR mfq0kN0gzMOoYDu4SyZeiyQFsJq0Y9fv0af9iF1vpSabijN2iDBK0i4wLd6B0n4pEA U00T40Xbwi7+scmTmVBHGngGGsUIvpDRHsFA8eGG4gzPO8hKQASjtS//4Oew1oFM0H XuRJ3kUyariwQ== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:58 +0000 Subject: [PATCH v2 13/21] arm64/ptrace: Expose FPMR via ptrace Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-13-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=2850; i=broonie@kernel.org; h=from:subject:message-id; bh=2lwb/HSWzM5tgdqcRY+V9adtYXXgaHL2EUDsgIl8iAQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4Wezz8fhVXghjJg399hUEAcrCZzENLJijL4NWsO Sa+6tuOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFngAKCRAk1otyXVSH0PRgB/ 9AktNcdpCKGPO+EG0Sv4Ug0mwEFOJeJj1bTis0Oqw5Y6betpj1xiH6x25BDr9vn5Fc57mgE0nOTGfi 2BEo7s8lkYhcsTCIA7sq1IXn2QgU/W4uERUmmt4Je31beCS6aVl7iODRIEo11vT/z+1HNXgLVdqtce rv0lYUk9A0HhP2Vtmr6K3MXFVqSooFd3jZ+2Rwj8mupg3Qeb6WbMHiTt0tisrmZlzu5w/vS/kaZjf9 zQKipE/3j+F5Agad97zfIL9qmqQn9GqxFRIGuDMx7XFbBo9zXUsNYmwid6nO94e97I2f6niOZHQeqr L6/GxB2tu/AFY542AhaHO/vC2w8Y5A X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add a new regset to expose FPMR via ptrace. It is not added to the FPSIMD registers since that structure is exposed elsewhere without any allowance for extension we don't add there. Signed-off-by: Mark Brown --- arch/arm64/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 43 insertions(+) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 20d7ef82de90..cfb8a4d213be 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -697,6 +697,39 @@ static int tls_set(struct task_struct *target, const struct user_regset *regset, return ret; } +static int fpmr_get(struct task_struct *target, const struct user_regset *regset, + struct membuf to) +{ + if (!system_supports_fpmr()) + return -EINVAL; + + if (target == current) + fpsimd_preserve_current_state(); + + return membuf_store(&to, target->thread.fpmr); +} + +static int fpmr_set(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + unsigned long fpmr; + + if (!system_supports_fpmr()) + return -EINVAL; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpmr, 0, count); + if (ret) + return ret; + + target->thread.fpmr = fpmr; + + fpsimd_flush_task_state(target); + + return 0; +} + static int system_call_get(struct task_struct *target, const struct user_regset *regset, struct membuf to) @@ -1417,6 +1450,7 @@ enum aarch64_regset { REGSET_HW_BREAK, REGSET_HW_WATCH, #endif + REGSET_FPMR, REGSET_SYSTEM_CALL, #ifdef CONFIG_ARM64_SVE REGSET_SVE, @@ -1495,6 +1529,14 @@ static const struct user_regset aarch64_regsets[] = { .regset_get = system_call_get, .set = system_call_set, }, + [REGSET_FPMR] = { + .core_note_type = NT_ARM_FPMR, + .n = 1, + .size = sizeof(u64), + .align = sizeof(u64), + .regset_get = fpmr_get, + .set = fpmr_set, + }, #ifdef CONFIG_ARM64_SVE [REGSET_SVE] = { /* Scalable Vector Extension */ .core_note_type = NT_ARM_SVE, diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 9417309b7230..b54b313bcf07 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -440,6 +440,7 @@ typedef struct elf64_shdr { #define NT_ARM_SSVE 0x40b /* ARM Streaming SVE registers */ #define NT_ARM_ZA 0x40c /* ARM SME ZA registers */ #define NT_ARM_ZT 0x40d /* ARM SME ZT registers */ +#define NT_ARM_FPMR 0x40e /* ARM floating point mode register */ #define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */ #define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note */ #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ From patchwork Tue Nov 14 14:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743902 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9559541229; Tue, 14 Nov 2023 14:36:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AlpAM4p/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71CF3C116B4; Tue, 14 Nov 2023 14:36:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972569; bh=p49U0rB8BLfyvHeTkXNyujHDJxY2xWglioVFZrQRPgM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AlpAM4p/PpDtnGa+P+8MSgHGTJ0ojhyv3MXbEXP5fT2nd+uKNEhre27nS3KShUuOw yv1LT6A8pMrshhhOeqccPV/j0EmbpO89/6v63x7E2GX84G0ngC5F9cPFgUcJypBWLa juOJYFe8Qu7RMoI+ALWZAtXZCEiGkhXTyXIIAFRt7P2O0fRnBsuq0mclLGf3uhM5RT gouns62U5thbp4juKWG56dUPRJrkPJEdTVEHPq0zu3N5AVYZsUUfZVJtVGo+bUnIQe 6KaKGtRtZVsjbYiH9cAmi+qngFKBCBIesxcdg4spOPiOCCXt8MLN26b6G2p19grEG5 vHj3e1XHGxFYg== From: Mark Brown Date: Tue, 14 Nov 2023 14:34:59 +0000 Subject: [PATCH v2 14/21] KVM: arm64: Add newly allocated ID registers to register descriptions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-14-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1330; i=broonie@kernel.org; h=from:subject:message-id; bh=p49U0rB8BLfyvHeTkXNyujHDJxY2xWglioVFZrQRPgM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WfNE845a8JBj/7uYktPGecHrfg665x4pinSKM3 7IYoRbiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFnwAKCRAk1otyXVSH0EPRB/ 0ej5UCRBRTqxqq1+eo0b3oJ3DQGFdnXwe003TSlUsDlKV3KkFJCceXkwq3fxrsW2Q+LMfcDMMSd5OY foJyuloV449NruHS2/7rzQW+3aaURgprNDwmu8yJjtO+cDH6VucQK4dFBWQz36wuw/G3z+L5Sk/4BU BNSeOCUZsXMNqWiH6+bYjN2onVo/oUY1I/JIY/01cCu+XfgYz2SBm0s8dNKf5H8l2MCF6X0yWFxp6j seYcd3kLbVN3MRPNy4LNoCQLgW7uWOf8k+zuC+Zp6IheOj5CPN6l5/I8qZnc9D9B5K/LCco2kyUrJ8 tp3828pzHxoG36ciTt0ft3yCCnuKAx X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023 architecture extensions have allocated some new ID registers, add them to the KVM system register descriptions so that they are visible to guests. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 4735e1b37fb3..b843da5e4bb9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2139,12 +2139,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64PFR0_EL1_AdvSIMD | ID_AA64PFR0_EL1_FP), }, ID_SANITISED(ID_AA64PFR1_EL1), - ID_UNALLOCATED(4,2), + ID_SANITISED(ID_AA64PFR2_EL1), ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), ID_HIDDEN(ID_AA64SMFR0_EL1), ID_UNALLOCATED(4,6), - ID_UNALLOCATED(4,7), + ID_SANITISED(ID_AA64FPFR0_EL1), /* CRm=5 */ { SYS_DESC(SYS_ID_AA64DFR0_EL1), @@ -2171,7 +2171,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | ID_AA64ISAR2_EL1_APA3 | ID_AA64ISAR2_EL1_GPA3)), - ID_UNALLOCATED(6,3), + ID_WRITABLE(ID_AA64ISAR3_EL1, ~ID_AA64ISAR3_EL1_RES0), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), ID_UNALLOCATED(6,6), From patchwork Tue Nov 14 14:35:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744313 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC79B41235; Tue, 14 Nov 2023 14:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vFhCe2sn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 991D6C4AF73; Tue, 14 Nov 2023 14:36:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972572; bh=SgGxSb9kQA/bzFV0T8szlBL5sjGe7ntk4tQniBm8gOw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vFhCe2snOULXdo871SMt+nDCqrS9241TrSxnAc/ZFILxII4Fra0o4TYxIg3ZVyijA YyrSDO+C9E5hA4UJIOwkKJttXi3wz0zJYiXMsrlVOptpHdInl376Nh/tE/i7AWiGlR zBLMIcOMZcdr7snv8Kjulk4prkiA+Lpl6CHUDlRLCvUaY4VJ8NO3GSiXLXpKdWK+EP eSDkylrwSDMaUhIlwWsw5BV4cnNFrvups1kXBcQOgV5dhlkMdpcKCmZQD2VTalsoLn yENYuWd6yhflRqi43RRzYl4lYXWZAvNHMsIB4QqsXzrppsEWwiq96Cy4OzG9jGcFiE L3TrjWeWtpUcg== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:00 +0000 Subject: [PATCH v2 15/21] KVM: arm64: Support FEAT_FPMR for guests Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-15-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=6384; i=broonie@kernel.org; h=from:subject:message-id; bh=SgGxSb9kQA/bzFV0T8szlBL5sjGe7ntk4tQniBm8gOw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WgnXw0TkQR4icJqepbU4lRD4hEfPZbylDbXx7j uZtrMWmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFoAAKCRAk1otyXVSH0M8hB/ wMlQwGWNQy8S+erxBA3wfg9J+HfuTHfSzfU11fVLODJvBFOlZfR+A8m+Hau61Z1Thm78x9jFvdY6NG c2wsjEoKlpsL5u2vwz185ToqMSIrxlC2NvOZJlvf28BxeQ/mN5nlkkuVkD/S6J9DiHzjON7klZdPzb dHSNpnjd/34t2VfOxS24DHXtc3jIIJhfpNGVfjeIma4An/4LsvlCpfUNg+WGfIPaTxdEBAAzsjKcqL EHohTF29nLVI1Tc721mQBZ7DstEsDLTNL9yn+FiNPNJmKDsSN9apdt2iPii+YFszuG1k6M22QviQzg 8SrYrYf82u9Y8uAzrp0VwMOH+63LJA X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_FPMR introduces a new system register FPMR which allows configuration of floating point behaviour, currently for FP8 specific features. Allow use of this in guests, disabling the trap while guests are running and saving and restoring the value along with the rest of the floating point state. Since FPMR is stored immediately after the main floating point state we share it with the hypervisor by adjusting the size of the shared region. Access to FPMR is covered by both a register specific trap HCRX_EL2.EnFPM and the overall floating point access trap so we just unconditionally enable the FPMR specific trap and rely on the floating point access trap to detect guest floating point usage. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_arm.h | 2 +- arch/arm64/include/asm/kvm_host.h | 4 +++- arch/arm64/kvm/fpsimd.c | 20 +++++++++++++++++--- arch/arm64/kvm/hyp/include/hyp/switch.h | 7 ++++++- arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 5 files changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 9f9239d86900..95f3b44e7c3a 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -103,7 +103,7 @@ #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) #define HCRX_GUEST_FLAGS \ - (HCRX_EL2_SMPME | HCRX_EL2_TCR2En | \ + (HCRX_EL2_SMPME | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM | \ (cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn | HCRX_EL2_MCE2) : 0)) #define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index f8d98985a39c..9885adff06fa 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -391,6 +391,8 @@ enum vcpu_sysreg { CNTP_CVAL_EL0, CNTP_CTL_EL0, + FPMR, + /* Memory Tagging Extension registers */ RGSR_EL1, /* Random Allocation Tag Seed Register */ GCR_EL1, /* Tag Control Register */ @@ -517,7 +519,6 @@ struct kvm_vcpu_arch { enum fp_type fp_type; unsigned int sve_max_vl; u64 svcr; - u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; @@ -576,6 +577,7 @@ struct kvm_vcpu_arch { struct kvm_guest_debug_arch external_debug_state; struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ + u64 *host_fpmr; /* hyp VA */ struct task_struct *parent_task; struct { diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index e3e611e30e91..dee078625d0d 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -14,6 +14,16 @@ #include #include +static void *fpsimd_share_end(struct user_fpsimd_state *fpsimd) +{ + void *share_end = fpsimd + 1; + + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + share_end += sizeof(u64); + + return share_end; +} + void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu) { struct task_struct *p = vcpu->arch.parent_task; @@ -23,7 +33,7 @@ void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu) return; fpsimd = &p->thread.uw.fpsimd_state; - kvm_unshare_hyp(fpsimd, fpsimd + 1); + kvm_unshare_hyp(fpsimd, fpsimd_share_end(fpsimd)); put_task_struct(p); } @@ -45,11 +55,15 @@ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu) kvm_vcpu_unshare_task_fp(vcpu); /* Make sure the host task fpsimd state is visible to hyp: */ - ret = kvm_share_hyp(fpsimd, fpsimd + 1); + ret = kvm_share_hyp(fpsimd, fpsimd_share_end(fpsimd)); if (ret) return ret; vcpu->arch.host_fpsimd_state = kern_hyp_va(fpsimd); + if (cpus_have_final_cap(ARM64_HAS_FPMR)) { + WARN_ON_ONCE(¤t->thread.fpmr + 1 != fpsimd_share_end(fpsimd)); + vcpu->arch.host_fpmr = kern_hyp_va(¤t->thread.fpmr); + } /* * We need to keep current's task_struct pinned until its data has been @@ -153,7 +167,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; fp_state.svcr = &vcpu->arch.svcr; - fp_state.fpmr = &vcpu->arch.fpmr; + fp_state.fpmr = &__vcpu_sys_reg(vcpu, FPMR); fp_state.fp_type = &vcpu->arch.fp_type; if (vcpu_has_sve(vcpu)) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index f99d8af0b9af..a51b21a2e26f 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -339,10 +339,15 @@ static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) isb(); /* Write out the host state if it's in the registers */ - if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) + if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) { __fpsimd_save_state(vcpu->arch.host_fpsimd_state); + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + *vcpu->arch.host_fpmr = read_sysreg_s(SYS_FPMR); + } /* Restore the guest state */ + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR); if (sve_guest) __hyp_sve_restore_guest(vcpu); else diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b843da5e4bb9..0789fb632623 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1914,6 +1914,15 @@ static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu, .visibility = hidden_user_visibility, \ } +static unsigned int fpmr_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + return 0; + + return REG_HIDDEN; +} + /* * Since reset() callback and field val are not used for idregs, they will be * used for specific purposes for idregs. @@ -2310,6 +2319,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, { SYS_DESC(SYS_SVCR), undef_access }, + { SYS_DESC(SYS_FPMR), access_rw, reset_unknown, FPMR, + .visibility = fpmr_visibility }, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, From patchwork Tue Nov 14 14:35:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743901 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA3D04121A; Tue, 14 Nov 2023 14:36:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hzsC7g38" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 36F83C433C8; Tue, 14 Nov 2023 14:36:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972576; bh=uh6GFkvx09xfJmabF6Bd3ORGncoAbbDBVJ6AhaRWYCg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hzsC7g38PIv/aHGtgF6psV3mUJXJrj9+HwBqJMH7s5x/1Jz9kHAn0g8MqGj62zIN8 WdQ42hd2qv3BojR4iDS0oZwxKNEkMfsgUOW/Xs+mAw6M24Pd7rVN5jvizaeMzAKUCf WXj7ee/RUw5zEzN7USy+JGV7YABFlCXQcWokpkkn55gh9goq8D3nWfvYfrXlUpuWnI 9Zpai3LTLYW0eyxreHAvdJU6QT26IfqZq/2ZfGlPoedMxLm6wV0fBeiEzH7oXQ16n9 KdcjK0HwnEQAGC/WCpoeCo7pIiBkhsPonVI8RW/JvXPAcqoM/XxZZ2Fff5VmZswuV5 7y+9tDrpcuXow== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:01 +0000 Subject: [PATCH v2 16/21] arm64/hwcap: Define hwcaps for 2023 DPISA features Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-16-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=12825; i=broonie@kernel.org; h=from:subject:message-id; bh=uh6GFkvx09xfJmabF6Bd3ORGncoAbbDBVJ6AhaRWYCg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WhqX1LkWz9PMHfFl/uVB80sHvlPslBun70Ikf1 kgXLu7uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFoQAKCRAk1otyXVSH0NCsB/ 4tQtEohjUFqtNyO6pwEEMAC8HGqGCQVzDxny4+3RJ5ksoB5G6NXiPXzaUBw0ShYiXLJXgzVkXBg4cQ d8T4j3PWPv/el/FEtU5VaBXq5rof1JiwgwX+lJTTjd9BxaZIJ4CA3SRBYUhai+GrMhXxW4k5/GEcuo tvkv0VfUbjlKRA4DwqP9V8Ir3WTVOwWOg9JjSRQEov9QEyZ7pYH+LkkuYJJek1yrg1tXToab0ECYsW wh52IK+WPjuvk8x0D/2qiOTptgCcwrF5mvyR6GMQlQQwy3O9l7iHta+kvZjiAK0bKwuZpapCzbCuPZ pT99fhwygYIucvTq7sBDGnhuHBgLBP X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023 architecture extensions include a large number of floating point features, most of which simply add new instructions. Add hwcaps so that userspace can enumerate these features. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 49 +++++++++++++++++++++++++++++++++ arch/arm64/include/asm/hwcap.h | 15 ++++++++++ arch/arm64/include/uapi/asm/hwcap.h | 15 ++++++++++ arch/arm64/kernel/cpufeature.c | 35 +++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 15 ++++++++++ 5 files changed, 129 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index ced7b335e2e0..448c1664879b 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -317,6 +317,55 @@ HWCAP2_LRCPC3 HWCAP2_LSE128 Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011. +HWCAP2_FPMR + Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001. + +HWCAP2_LUT + Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001. + +HWCAP2_FAMINMAX + Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001. + +HWCAP2_F8CVT + Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1. + +HWCAP2_F8FMA + Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1. + +HWCAP2_F8DP4 + Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1. + +HWCAP2_F8DP2 + Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1. + +HWCAP2_F8E4M3 + Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1. + +HWCAP2_F8E5M2 + Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1. + +HWCAP2_SME_LUTV2 + Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1. + +HWCAP2_SME_F8F16 + Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1. + +HWCAP2_SME_F8F32 + Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1. + +HWCAP2_SME_SF8FMA + Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1. + +HWCAP2_SME_SF8DP4 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. + +HWCAP2_SME_SF8DP2 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1. + +HWCAP2_SME_SF8DP4 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. + + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index cd71e09ea14d..4edd3b61df11 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -142,6 +142,21 @@ #define KERNEL_HWCAP_SVE_B16B16 __khwcap2_feature(SVE_B16B16) #define KERNEL_HWCAP_LRCPC3 __khwcap2_feature(LRCPC3) #define KERNEL_HWCAP_LSE128 __khwcap2_feature(LSE128) +#define KERNEL_HWCAP_FPMR __khwcap2_feature(FPMR) +#define KERNEL_HWCAP_LUT __khwcap2_feature(LUT) +#define KERNEL_HWCAP_FAMINMAX __khwcap2_feature(FAMINMAX) +#define KERNEL_HWCAP_F8CVT __khwcap2_feature(F8CVT) +#define KERNEL_HWCAP_F8FMA __khwcap2_feature(F8FMA) +#define KERNEL_HWCAP_F8DP4 __khwcap2_feature(F8DP4) +#define KERNEL_HWCAP_F8DP2 __khwcap2_feature(F8DP2) +#define KERNEL_HWCAP_F8E4M3 __khwcap2_feature(F8E4M3) +#define KERNEL_HWCAP_F8E5M2 __khwcap2_feature(F8E5M2) +#define KERNEL_HWCAP_SME_LUTV2 __khwcap2_feature(SME_LUTV2) +#define KERNEL_HWCAP_SME_F8F16 __khwcap2_feature(SME_F8F16) +#define KERNEL_HWCAP_SME_F8F32 __khwcap2_feature(SME_F8F32) +#define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) +#define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) +#define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 5023599fa278..285610e626f5 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -107,5 +107,20 @@ #define HWCAP2_SVE_B16B16 (1UL << 45) #define HWCAP2_LRCPC3 (1UL << 46) #define HWCAP2_LSE128 (1UL << 47) +#define HWCAP2_FPMR (1UL << 48) +#define HWCAP2_LUT (1UL << 49) +#define HWCAP2_FAMINMAX (1UL << 50) +#define HWCAP2_F8CVT (1UL << 51) +#define HWCAP2_F8FMA (1UL << 52) +#define HWCAP2_F8DP4 (1UL << 53) +#define HWCAP2_F8DP2 (1UL << 54) +#define HWCAP2_F8E4M3 (1UL << 55) +#define HWCAP2_F8E5M2 (1UL << 56) +#define HWCAP2_SME_LUTV2 (1UL << 57) +#define HWCAP2_SME_F8F16 (1UL << 58) +#define HWCAP2_SME_F8F32 (1UL << 59) +#define HWCAP2_SME_SF8FMA (1UL << 60) +#define HWCAP2_SME_SF8DP4 (1UL << 61) +#define HWCAP2_SME_SF8DP2 (1UL << 62) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index ea0b680792de..33e301b6e31e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -220,6 +220,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), @@ -235,6 +236,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -303,6 +305,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -315,6 +319,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -325,10 +333,22 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), ARM64_FTR_END, }; static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), ARM64_FTR_END, }; @@ -2851,6 +2871,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), + HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), @@ -2864,6 +2885,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), + HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), + HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), @@ -2904,6 +2927,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #ifdef CONFIG_ARM64_SME HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), @@ -2911,12 +2935,23 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), + HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), + HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), #endif /* CONFIG_ARM64_SME */ + HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 8322e968fd0d..29155107d35d 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -130,6 +130,21 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16", [KERNEL_HWCAP_LRCPC3] = "lrcpc3", [KERNEL_HWCAP_LSE128] = "lse128", + [KERNEL_HWCAP_FPMR] = "fpmr", + [KERNEL_HWCAP_LUT] = "lut", + [KERNEL_HWCAP_FAMINMAX] = "faminmax", + [KERNEL_HWCAP_F8CVT] = "f8cvt", + [KERNEL_HWCAP_F8FMA] = "f8fma", + [KERNEL_HWCAP_F8DP4] = "f8dp4", + [KERNEL_HWCAP_F8DP2] = "f8dp2", + [KERNEL_HWCAP_F8E4M3] = "f8e4m3", + [KERNEL_HWCAP_F8E5M2] = "f8e5m2", + [KERNEL_HWCAP_SME_LUTV2] = "smelutv2", + [KERNEL_HWCAP_SME_F8F16] = "smef8f16", + [KERNEL_HWCAP_SME_F8F32] = "smef8f32", + [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", + [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", + [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", }; #ifdef CONFIG_COMPAT From patchwork Tue Nov 14 14:35:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744312 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE7E4122C; Tue, 14 Nov 2023 14:36:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YOS8KG4f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49C02C433B7; Tue, 14 Nov 2023 14:36:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972580; bh=jvyJQ++Epw5Vr3/tG/z6+6Y9vzI/cjN2rH2C/CkHcMI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YOS8KG4fVO3sjgOMo+FAHn64GDHolFxDFhb3NYUj8fzUzQFNPjlDg30ZmOYpBnAru tG/OfUrOJlx0wulfw2zaVlpNjhOWdeaYuZSk1y5WKKBWKQzEkSinYWQGr84FgvntA5 0BVpix+CA8Afc0bEK1SKV53obyaPXfYfAFzJUUHmJaQCyLZwa/IOZ6FhHIqupvjtzE YyOZ4jwEYRZ4XVKVafGt9toXiX4onS80XbKSKL4aHwfL1hQTJl09B+dJl8qQMYfRWw JMD11WTO3b9xoSuP3rvFBMYZsuAd1cMab0AgrmbwOWl6qDrDwwcfT4rP9HYcjwXTO2 nxQSCKgoFAOvg== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:02 +0000 Subject: [PATCH v2 17/21] kselftest/arm64: Handle FPMR context in generic signal frame parser Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-17-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1642; i=broonie@kernel.org; h=from:subject:message-id; bh=jvyJQ++Epw5Vr3/tG/z6+6Y9vzI/cjN2rH2C/CkHcMI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WihBluov0BrNbZHj3lKU43suw3FpTrP5aceS3k ldFYx6eJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFogAKCRAk1otyXVSH0DttB/ 0ZeHEuPXQopSQOn9tAF87i1SQZ/RrZwyxmPptMZxx7JsE7Dw7ko8FabbYbQyX235VU7PY/xaM3E2dq b+hbNedb5201bNO69pYHsDRwZhLvCWOeKTHuTuFUF1B2Fco9O19BN/OgD6iTJ9ccvA+EOh/nA7wtb+ //J11V+Zuw580IfZ5fBSZh77Tqp/53Jo8HzGrd1IozgeHTkQUVevtC4U+AOvXMS7sx7w3S+t85qLZV IDB9PbMAo0L/fpAQb+1NIkEbKiY1WlfT+viZJ978DYMdGUe/QtfwRq5mmPAWY1bXtl3ih4zkhVhT5h 62BCjQdiqLITLvKYF5yOZf0D5qM2kO X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Teach the generic signal frame parsing code about the newly added FPMR frame, avoiding warnings every time one is generated. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/signal/testcases/testcases.c | 8 ++++++++ tools/testing/selftests/arm64/signal/testcases/testcases.h | 1 + 2 files changed, 9 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.c b/tools/testing/selftests/arm64/signal/testcases/testcases.c index 9f580b55b388..674b88cc8c39 100644 --- a/tools/testing/selftests/arm64/signal/testcases/testcases.c +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.c @@ -209,6 +209,14 @@ bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) zt = (struct zt_context *)head; new_flags |= ZT_CTX; break; + case FPMR_MAGIC: + if (flags & FPMR_CTX) + *err = "Multiple FPMR_MAGIC"; + else if (head->size != + sizeof(struct fpmr_context)) + *err = "Bad size for fpmr_context"; + new_flags |= FPMR_CTX; + break; case EXTRA_MAGIC: if (flags & EXTRA_CTX) *err = "Multiple EXTRA_MAGIC"; diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.h b/tools/testing/selftests/arm64/signal/testcases/testcases.h index a08ab0d6207a..7727126347e0 100644 --- a/tools/testing/selftests/arm64/signal/testcases/testcases.h +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.h @@ -19,6 +19,7 @@ #define ZA_CTX (1 << 2) #define EXTRA_CTX (1 << 3) #define ZT_CTX (1 << 4) +#define FPMR_CTX (1 << 5) #define KSFT_BAD_MAGIC 0xdeadbeef From patchwork Tue Nov 14 14:35:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743900 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A40CF4121A; Tue, 14 Nov 2023 14:36:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FhClDHVg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C67B4C433BB; Tue, 14 Nov 2023 14:36:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972583; bh=irtBwegYB+DXpSWW34B5isPMLTYQBsVR3AqcPDPAR5U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FhClDHVgXQ/fUVGGo+9j2VibBnmAldzFuTcCJZ886zPUWd4NIHoFe72o+MSYU+RZ7 FDL8CV47LqKn7c/E8psg7spZeGkAka28Fj/P02/BH6zziAk4ILXBgYlJUHAxEtZRwG jM2IwfPrLcUbv4nDb4E7pgw+Rcuf5HttsEYoK7TzdogX5Uldm0w0+0Ht1Kx06b8/43 OzbfENcf3G/f+CPGIXZ6ZPCGK+8lN85z3vc9kGZy0XKjeO+NgM2TlK12/HR6jol7Rx KZf6ob+3YQBUFbxruPlEp5n58jfq8dAlLlXpvwMHnxMw2kzQVhrS6XCt1QS5s4D9tu XvT0gUR14Zobg== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:03 +0000 Subject: [PATCH v2 18/21] kselftest/arm64: Add basic FPMR test Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-18-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=2813; i=broonie@kernel.org; h=from:subject:message-id; bh=irtBwegYB+DXpSWW34B5isPMLTYQBsVR3AqcPDPAR5U=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WiPCcK6g4XDzQH51CyEevmUoVhDX+62HmCkTct 0KWEm/uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFogAKCRAk1otyXVSH0F2FB/ 0cINuYxh6O1Ud5ocIKz/tH4Kx1xJwIDq45elc+inBWQXF3MQXvo9AuL8Y8wSllDzU034b0PRWp6Q9K 160Wk+yFlP+0QdY07e+iljh0M5eOqMMnlzxK9bIJdtpBGM/Cp3i0ElxXvTOP62YIGL32zhlXeemoWB 4LbITXGpVsQ6KFwFwIpr9+bwoL01Sckmko65LpsNZQHrlnCmsVwt1YHNDKd2jBDi8tgHUtmdRbpAL7 fOesE2IzJT6CwdwPVkeaq37hX3YI3U0EMZG85C+RY15p1hmt1fLdI5kXQfbWhHI7YM3cd8b92gnwQe Q0w/J8+lHLsUuO8KFUbqz7Em9dBuZ2 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Verify that a FPMR frame is generated on systems that support FPMR and not generated otherwise. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/signal/.gitignore | 1 + .../arm64/signal/testcases/fpmr_siginfo.c | 82 ++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/.gitignore b/tools/testing/selftests/arm64/signal/.gitignore index 839e3a252629..1ce5b5eac386 100644 --- a/tools/testing/selftests/arm64/signal/.gitignore +++ b/tools/testing/selftests/arm64/signal/.gitignore @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only mangle_* fake_sigreturn_* +fpmr_* sme_* ssve_* sve_* diff --git a/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c b/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c new file mode 100644 index 000000000000..e9d24685e741 --- /dev/null +++ b/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 ARM Limited + * + * Verify that the FPMR register context in signal frames is set up as + * expected. + */ + +#include +#include +#include +#include +#include +#include + +#include "test_signals_utils.h" +#include "testcases.h" + +static union { + ucontext_t uc; + char buf[1024 * 128]; +} context; + +#define SYS_FPMR "S3_3_C4_C4_2" + +static uint64_t get_fpmr(void) +{ + uint64_t val; + + asm volatile ( + "mrs %0, " SYS_FPMR "\n" + : "=r"(val) + : + : "cc"); + + return val; +} + +int fpmr_present(struct tdescr *td, siginfo_t *si, ucontext_t *uc) +{ + struct _aarch64_ctx *head = GET_BUF_RESV_HEAD(context); + struct fpmr_context *fpmr_ctx; + size_t offset; + bool in_sigframe; + bool have_fpmr; + __u64 orig_fpmr; + + have_fpmr = getauxval(AT_HWCAP2) & HWCAP2_FPMR; + if (have_fpmr) + orig_fpmr = get_fpmr(); + + if (!get_current_context(td, &context.uc, sizeof(context))) + return 1; + + fpmr_ctx = (struct fpmr_context *) + get_header(head, FPMR_MAGIC, td->live_sz, &offset); + + in_sigframe = fpmr_ctx != NULL; + + fprintf(stderr, "FPMR sigframe %s on system %s FPMR\n", + in_sigframe ? "present" : "absent", + have_fpmr ? "with" : "without"); + + td->pass = (in_sigframe == have_fpmr); + + if (have_fpmr && fpmr_ctx) { + if (fpmr_ctx->fpmr != orig_fpmr) { + fprintf(stderr, "FPMR in frame is %llx, was %llx\n", + fpmr_ctx->fpmr, orig_fpmr); + td->pass = false; + } + } + + return 0; +} + +struct tdescr tde = { + .name = "FPMR", + .descr = "Validate that FPMR is present as expected", + .timeout = 3, + .run = fpmr_present, +}; From patchwork Tue Nov 14 14:35:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744311 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C352F41238; Tue, 14 Nov 2023 14:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U2ZzEUiJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E92E0C116B8; Tue, 14 Nov 2023 14:36:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972586; bh=fY7XsyGWBCyMThKR5lWJhW/9PqmzwSI9SznLLw/I8/I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=U2ZzEUiJ3wWx0kzLgjxvRKTz7YA/Pd7m7OqgcVPfgYhBG/daZI5OMXfmYCICpanw2 0M5Hn90wsaxXkivI978MGkZEhPPHYgJBQgYxpIx2xpLD19JHdtlDXJwSIM21RzXbFe vu0wPVTZnYQXIjahhT1VenU1WHC+idr2x9WPlcwIwf+pbI60ZA3bg8W7SViQKiAIz0 QzkoNpKRGbYrm8hSwjc0o4OIZvjC6IM6Rgxbu3z9wrGvEzHOs76aqo+Rl3UO2HBV+t EDJQ6L+hTO/1r4Vjt0KH9M/0X+WzLeHnFZGrrCZQ6EWqSU/+mrvPVF1CkumY5X2auX UeQL9YQIbrbUA== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:04 +0000 Subject: [PATCH v2 19/21] kselftest/arm64: Add 2023 DPISA hwcap test coverage Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-19-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=6393; i=broonie@kernel.org; h=from:subject:message-id; bh=fY7XsyGWBCyMThKR5lWJhW/9PqmzwSI9SznLLw/I8/I=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4Wj/4DkTI74HONGL+kPoEJ65fWKRa+nL0DBlwok B0asQAuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFowAKCRAk1otyXVSH0HvTCA CC7E6j5q4tx6cJuoQwcXq2HmscRKa1+FjE5yC1QvuF/Wq78X3qmB/wV8q1EBRI/Ouz47jBCbS1rwiM yOANxHk/dmXUdIcuFKoci5e+kryBc4oH7BOoXxZbx+7GOWErWjqz1Dh+eK8Yz7xJAv0jq3eHO4+os4 tifWXCbGq2jJ2Y1qpckV8Ii7uzIhFVv8HCF0MyjZEKp2vP0eawXKrbafXH0145gtfn8ce/gCzYngJy hJvv50zhpNQjCF8bP02N1SH6YGT0LO6vf/k7JVS7zypwA4WMPNWS+iWmQ/YSO3jl9ZNcmM05diQh/t 55Q5m0LT6ZjKv9n/q/GFtD6qFc8A5Z X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add the hwcaps added for the 2023 DPISA extensions to the hwcaps test program. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 217 ++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index 1189e77c8152..d8909b2b535a 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -58,11 +58,46 @@ static void cssc_sigill(void) asm volatile(".inst 0xdac01c00" : : : "x0"); } +static void f8cvt_sigill(void) +{ + /* FSCALE V0.4H, V0.4H, V0.4H */ + asm volatile(".inst 0x2ec03c00"); +} + +static void f8dp2_sigill(void) +{ + /* FDOT V0.4H, V0.4H, V0.5H */ + asm volatile(".inst 0xe40fc00"); +} + +static void f8dp4_sigill(void) +{ + /* FDOT V0.2S, V0.2S, V0.2S */ + asm volatile(".inst 0xe00fc00"); +} + +static void f8fma_sigill(void) +{ + /* FMLALB V0.8H, V0.16B, V0.16B */ + asm volatile(".inst 0xec0fc00"); +} + +static void faminmax_sigill(void) +{ + /* FAMIN V0.4H, V0.4H, V0.4H */ + asm volatile(".inst 0x2ec01c00"); +} + static void fp_sigill(void) { asm volatile("fmov s0, #1"); } +static void fpmr_sigill(void) +{ + asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0"); +} + static void ilrcpc_sigill(void) { /* LDAPUR W0, [SP, #8] */ @@ -95,6 +130,12 @@ static void lse128_sigill(void) : "cc", "memory"); } +static void lut_sigill(void) +{ + /* LUTI2 V0.16B, { V0.16B }, V[0] */ + asm volatile(".inst 0x4e801000"); +} + static void mops_sigill(void) { char dst[1], src[1]; @@ -216,6 +257,78 @@ static void smef16f16_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } +static void smef8f16_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT ZA.H[W0, 0], Z0.B-Z1.B, Z0.B-Z1.B */ + asm volatile(".inst 0xc1a01020" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smef8f32_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT ZA.S[W0, 0], { Z0.B-Z1.B }, Z0.B[0] */ + asm volatile(".inst 0xc1500038" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smelutv2_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* LUTI4 { Z0.B-Z3.B }, ZT0, { Z0-Z1 } */ + asm volatile(".inst 0xc08b0000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8dp2_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT Z0.H, Z0.B, Z0.B[0] */ + asm volatile(".inst 0x64204400" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8dp4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT Z0.S, Z0.B, Z0.B[0] */ + asm volatile(".inst 0xc1a41C00" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8fma_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMLALB V0.8H, V0.16B, V0.16B */ + asm volatile(".inst 0xec0fc00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void sve_sigill(void) { /* RDVL x0, #0 */ @@ -353,6 +466,53 @@ static const struct hwcap_data { .cpuinfo = "cssc", .sigill_fn = cssc_sigill, }, + { + .name = "F8CVT", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8CVT, + .cpuinfo = "f8cvt", + .sigill_fn = f8cvt_sigill, + }, + { + .name = "F8DP4", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8DP4, + .cpuinfo = "f8dp4", + .sigill_fn = f8dp4_sigill, + }, + { + .name = "F8DP2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8DP2, + .cpuinfo = "f8dp4", + .sigill_fn = f8dp2_sigill, + }, + { + .name = "F8E5M2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8E5M2, + .cpuinfo = "f8e5m2", + }, + { + .name = "F8E4M3", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8E4M3, + .cpuinfo = "f8e4m3", + }, + { + .name = "F8FMA", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8FMA, + .cpuinfo = "f8fma", + .sigill_fn = f8fma_sigill, + }, + { + .name = "FAMINMAX", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_FAMINMAX, + .cpuinfo = "faminmax", + .sigill_fn = faminmax_sigill, + }, { .name = "FP", .at_hwcap = AT_HWCAP, @@ -360,6 +520,14 @@ static const struct hwcap_data { .cpuinfo = "fp", .sigill_fn = fp_sigill, }, + { + .name = "FPMR", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_FPMR, + .cpuinfo = "fpmr", + .sigill_fn = fpmr_sigill, + .sigill_reliable = true, + }, { .name = "JSCVT", .at_hwcap = AT_HWCAP, @@ -411,6 +579,13 @@ static const struct hwcap_data { .cpuinfo = "lse128", .sigill_fn = lse128_sigill, }, + { + .name = "LUT", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_LUT, + .cpuinfo = "lut", + .sigill_fn = lut_sigill, + }, { .name = "MOPS", .at_hwcap = AT_HWCAP2, @@ -511,6 +686,48 @@ static const struct hwcap_data { .cpuinfo = "smef16f16", .sigill_fn = smef16f16_sigill, }, + { + .name = "SME F8F16", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_F8F16, + .cpuinfo = "smef8f16", + .sigill_fn = smef8f16_sigill, + }, + { + .name = "SME F8F32", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_F8F32, + .cpuinfo = "smef8f32", + .sigill_fn = smef8f32_sigill, + }, + { + .name = "SME LUTV2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_LUTV2, + .cpuinfo = "smelutv2", + .sigill_fn = smelutv2_sigill, + }, + { + .name = "SME SF8FMA", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_SF8FMA, + .cpuinfo = "smesf8fma", + .sigill_fn = smesf8fma_sigill, + }, + { + .name = "SME SF8DP2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_SF8DP2, + .cpuinfo = "smesf8dp2", + .sigill_fn = smesf8dp2_sigill, + }, + { + .name = "SME SF8DP4", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_SF8DP4, + .cpuinfo = "smesf8dp4", + .sigill_fn = smesf8dp4_sigill, + }, { .name = "SVE", .at_hwcap = AT_HWCAP, From patchwork Tue Nov 14 14:35:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 743899 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E562441237; Tue, 14 Nov 2023 14:36:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MZdxZuqQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14499C433BB; Tue, 14 Nov 2023 14:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972589; bh=RtrbRWeplo/J+dSChm3CUN1rkk7mxJJmNnU3ySYX5lo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MZdxZuqQS/XCeGxM/kivPa7IpJWDktjqRlqNdMm66VzqGPfmiiHKa69wsy9kG7jKJ pIx9bouOUxMsa73sOeoGYYXUMmz1/gvvFli6MC5QY1XgU8zQ4+0nOKsEOtVSEKWgIA Q5UK0xyv0Ai9bpF07Roz/X8zcQ+/2Ou2TEJFZ9XuHNUrM1+FyxzHyUFEz5I9ZID4By WkhaP8rJE4UAAATpzfZ9LyyG8huR70oAO743hcixhgk4pzWgaoSn0ocN3S9exlMVgw iplMsk+ZxIr1PArpIQgQg2skqPO+77Lh7DlXXcA9t4aCkBqHBblgJoMZJa1xA4xSwF FZbEk/lXIsz6Q== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:05 +0000 Subject: [PATCH v2 20/21] KVM: arm64: selftests: Document feature registers added in 2023 extensions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-20-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1469; i=broonie@kernel.org; h=from:subject:message-id; bh=RtrbRWeplo/J+dSChm3CUN1rkk7mxJJmNnU3ySYX5lo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4Wk6Rdizd0teYDpHLF5vYfFahxZEHcZmnD2tO0f 90YAn6OJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFpAAKCRAk1otyXVSH0FMfB/ 0a7BR0gFJP7bzs3Z5Q80cNK5sYdcR7PAh7c233DaEhaMh+1cU5qxOgVbRM70SM9IjdNFSs9uPyTfsk r8NQePoJanKT3ZiSLWYPHgTkuCuI8vdUxTqHh+69MEb9JWeHsa6vXaYQfXVtBxuSLbQX1x8/74McdD GMoSizo6vLPiNBgW1xMQDnTF2OMPyfkeGKHeymXcMcD58PnKWxbizCSYgYo5u6GhrBPlBkxaUKwn0p bGvsZzGZO5MHXTAFKDY8P3t/6S183grwwFLqtYVh49dnedOMGCsqawEMqX7SMWgTctXZJIZY8UpN5E ULM26iJ84hgRZq2a3v+tEs7bKbOF82 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023 architecture extensions allocated some previously usused feature registers, add comments mapping the names in get-reg-list as we do for the other allocated registers. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 709d7d721760..71ea6ecec7ce 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -428,7 +428,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 4, 4), /* ID_AA64ZFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 5), /* ID_AA64SMFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 6), - ARM64_SYS_REG(3, 0, 0, 4, 7), + ARM64_SYS_REG(3, 0, 0, 4, 7), /* ID_AA64FPFR_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 0), /* ID_AA64DFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 1), /* ID_AA64DFR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 2), @@ -440,7 +440,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 6, 0), /* ID_AA64ISAR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 1), /* ID_AA64ISAR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 2), /* ID_AA64ISAR2_EL1 */ - ARM64_SYS_REG(3, 0, 0, 6, 3), + ARM64_SYS_REG(3, 0, 0, 6, 3), /* ID_AA64ISAR3_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 4), ARM64_SYS_REG(3, 0, 0, 6, 5), ARM64_SYS_REG(3, 0, 0, 6, 6), From patchwork Tue Nov 14 14:35:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 744310 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F67B41236; Tue, 14 Nov 2023 14:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NJ9jhbCZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31FD3C116B8; Tue, 14 Nov 2023 14:36:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699972592; bh=uwufjRPZpufB4WAKz4BvxO1YI+sO9dPrjMMi385iZbk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NJ9jhbCZtT33Qvof3TlCzkkFhz5s+fq7thPKABIDhzv7DUXN8pq3oHHiIRGSktlnL 72ejabE3GFSkmCUq/2YFLnc+cZDPYbw0e/kjIyvkxRWtZbyYGa4IiJQfayH/fIfkqf 92R+7hAZa7klpM9Fb0GqNK+XEUE7cWnUj4IcowB8lyqnbVzb1oLcEUMcgl1XsDtcnV 300Bv9ThGLCHhms8Hq8sl+5ZoO8zlP7QoqX9W/DysaVyRU0errvieR7fHGoiZpOZST U0uJMg3MijVfNMRWpz05QcirghdcvKuGLyvSxIm27WI84zoGz+Ce42un29uyb65Mlm XCncXueZaM1RQ== From: Mark Brown Date: Tue, 14 Nov 2023 14:35:06 +0000 Subject: [PATCH v2 21/21] KVM: arm64: selftests: Teach get-reg-list about FPMR Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231114-arm64-2023-dpisa-v2-21-47251894f6a8@kernel.org> References: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> In-Reply-To: <20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1321; i=broonie@kernel.org; h=from:subject:message-id; bh=uwufjRPZpufB4WAKz4BvxO1YI+sO9dPrjMMi385iZbk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlU4WljyZx9r11YL8tcSv5B8kuEfjpvUQEKebxv1Zj Tas9auiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZVOFpQAKCRAk1otyXVSH0BRGB/ 0eKQ35FdG4nEY5EMIhWlYN7NyAik/Z8VmcnuImgEnedGuih5QNXSXGmyTcg+eoM3Ug+sF+9HdXnYs6 r7BGS+4K0FAIhZ8EemtAZnN7MHTkCtiaWndEdzRG4u9ekRHwvcfslpdgQoETJVHO6h0n2/gRIpZGlI 90D1oWpNyYWZjFpTh61erW89DUsGuj0ljQU26xo5eMnef9S3riMClGoK/1AqLOtlu/98ZZ4ebfvCI6 gh0C7bmQdtzP2sd32hYuAJk6OUQ8etGAoh9fxNtgUKKSZLRhfTCIkBjGkrhMKR6W9/MheCeCvIADvH bKXZvUhzzWTmEAEKQBIeFt8R0l5BPO X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_FPMR defines a new register FMPR which is available at all ELs and is discovered via ID_AA64PFR2_EL1.FPMR, add this to the set of registers that get-reg-list knows to check for with the required identification register depdendency. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 71ea6ecec7ce..1e43511d1440 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -40,6 +40,12 @@ static struct feature_id_reg feat_id_regs[] = { ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ 4, 1 + }, + { + ARM64_SYS_REG(3, 3, 4, 4, 2), /* FPMR */ + ARM64_SYS_REG(3, 0, 0, 4, 2), /* ID_AA64PFR2_EL1 */ + 32, + 1 } }; @@ -481,6 +487,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ + ARM64_SYS_REG(3, 3, 4, 4, 2), /* FPMR */ ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ };