From patchwork Sat Aug 17 18:36:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 171537 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp989892ily; Sat, 17 Aug 2019 11:36:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxPkxq6+BosjA2kLqSECGoYpyrLeOo+m/S4lMwSPEye3esiYj1816RT40p/t2hlbHUHp/zR X-Received: by 2002:a63:2447:: with SMTP id k68mr13194521pgk.219.1566066998612; Sat, 17 Aug 2019 11:36:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566066998; cv=none; d=google.com; s=arc-20160816; b=EJ2kE9Hy5n3WfthMVShZyb2JpH+zKUG9c5KtCsTB9pHEte3JUgq28TDybfg1xRhow3 nuXCpsmbYGNwRYEt0qTU8+mxU0V3qKlffmabQEwQtkz7JnNUT3qIXnAaQrR1Kg+yuAqT hKfGA7BnDZx7dS/8OVw0ixZ50Bl+SoRL5sJARs57PpNSCSTXc58DFHzDQWb3QghuP2WG 6oQr3CwZTEaziZNjTOryDWEggZcW83TE+AFywrqeYXiWMOyxQetUvX3t8CxhYSZPNgFQ dzfk03N7fYkk/GIR+DjQoAIgNm4Ftqgb54neNA8h3Z1tY+lEw+uA9B06kFPmxiiPdDo+ r32w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=hn5wSwGbfV1ASKyLdnZBx4wD4svsXsjBYVfQupeV/uk=; b=MZ6kqEx0sOVm3u223pw8kfprQLrRdotuV90y8+jO4kLcXR4jCuxP9kKzB2Ltilsif5 dtIbCwu4ZcCt8Dp/BZfD2zKNUI+faQ9fprxNXg4b6jQBC1n6sJxIZ2s3X9fPTydaiB5H Nb1PA8p+8F6HLkZkeSdx25mwRlxt/cFogRVEUl1qvSJP0GxtPBklzbpftUQqxHK5+jqg 5icWTv5j7eteSGoeIGZzsFmOIBmaW6I/iNdxaXjSo96Kkc5oQXzEtRYosNlsaZ/+pdds I3apaiRcyQGapF8KcN5dglExLArwKeZXScoQjwidIqFH7yUuSG16AkJKFK+sBAh8x5ZM m0QQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mTFdpglV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 31si6513005pld.65.2019.08.17.11.36.38; Sat, 17 Aug 2019 11:36:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mTFdpglV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726303AbfHQSgh (ORCPT + 8 others); Sat, 17 Aug 2019 14:36:37 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:39350 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726298AbfHQSgh (ORCPT ); Sat, 17 Aug 2019 14:36:37 -0400 Received: by mail-pg1-f194.google.com with SMTP id u17so4579726pgi.6 for ; Sat, 17 Aug 2019 11:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hn5wSwGbfV1ASKyLdnZBx4wD4svsXsjBYVfQupeV/uk=; b=mTFdpglV1XCrnX4v6GdHyklH4I6FWazbCF2q3yIZTX7zkzdu+heV9b4EnakjJCv8CA Xml/FdAUBvt33eL/9HRxPnegF59Ez3OYOlrGrdvUF+E5pJ3+B/fqILgk1PZLGVaT2y8i QorAGjENqYzTucRPyVdu9ISJjCMAVs7qZ1FUZQO9v86tvus4LPQd+9lPzqO2Zhz0taLX zJdwV1zHEBZQeoTtc5Xdga1pPX4N+LOjcAV7r1tXpa4L3+ENuAE6AjyzRxm/7AkhcwN/ SPJVPj6YZdyxVh5GlnvA+vqgXqjiiSm1tg+BWMrqgxTuEi0DAI07vQdSfQWBOtkSfVFn +U0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hn5wSwGbfV1ASKyLdnZBx4wD4svsXsjBYVfQupeV/uk=; b=S26I3OUOm5cVxO01uw68R8mfNXUSZytpDdLDTn43gnh6m0j95/Xq95RSDn/mbAphOS Hpyhzu8aPzuuTycuiuv+yH0iF3ueSZOAqgmIMzWI/gkv03P3NrfpIZLpx2E2CuEGf5sQ RVZd7sNWVigC+UVMUpqpist4GJbdqmeA5t8KfL6flC4eh/Vh2+FXMlRnZn5qgvTb0MmA 5E7jzbtm2dgT5wAyuiHKlzbSPlge5waINKHza+wDrKOXKp911/dQ4VdklHSzO5Gyw0+m MymvB+NDa1Lud9mcQBkzlacAZerTGcnK9C6cLtMWncDSq+KISG3CvcW81WjTKnwP0iiL uTxw== X-Gm-Message-State: APjAAAV8VWsp9dadRL98erT8wLZuq2caRO6JzWnS4EfcUF/80SlGypsX hD5N6c9VppA5A761eg76ajkk7hEhmw== X-Received: by 2002:a17:90a:77c9:: with SMTP id e9mr12399635pjs.141.1566066996491; Sat, 17 Aug 2019 11:36:36 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:909:4559:9185:a772:a21d:70ac]) by smtp.gmail.com with ESMTPSA id 33sm8588640pgy.22.2019.08.17.11.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Aug 2019 11:36:35 -0700 (PDT) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v2 1/7] dt-bindings: clock: Add devicetree binding for BM1880 SoC Date: Sun, 18 Aug 2019 00:06:08 +0530 Message-Id: <20190817183614.8429-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190817183614.8429-1-manivannan.sadhasivam@linaro.org> References: <20190817183614.8429-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add YAML devicetree binding for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam --- .../bindings/clock/bitmain,bm1880-clk.yaml | 83 +++++++++++++++++++ include/dt-bindings/clock/bm1880-clock.h | 82 ++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 include/dt-bindings/clock/bm1880-clock.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml new file mode 100644 index 000000000000..a457f996287d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Clock Controller + +maintainers: + - Manivannan Sadhasivam + +description: | + The Bitmain BM1880 clock controller generates and supplies clock to + various peripherals within the SoC. + + This binding uses common clock bindings + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + oneOf: + - items: + - enum: + - bitmain,bm1880-clk + + reg: + minItems: 2 + maxItems: 2 + items: + - description: pll registers + - description: system registers + + reg-names: + items: + - const: pll + - const: sys + + clocks: + maxItems: 1 + description: Phandle of the input reference clock + + clock-names: + maxItems: 1 + items: + - const: osc + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock controller node: + - | + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + + # Example UART controller node that consumes clock generated by the clock controller: + - | + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>; + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + +... diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h new file mode 100644 index 000000000000..895646d66b07 --- /dev/null +++ b/include/dt-bindings/clock/bm1880-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree binding constants for Bitmain BM1880 SoC + * + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_BM1880_H +#define __DT_BINDINGS_CLOCK_BM1880_H + +#define BM1880_CLK_OSC 0 +#define BM1880_CLK_MPLL 1 +#define BM1880_CLK_SPLL 2 +#define BM1880_CLK_FPLL 3 +#define BM1880_CLK_DDRPLL 4 +#define BM1880_CLK_A53 5 +#define BM1880_CLK_50M_A53 6 +#define BM1880_CLK_AHB_ROM 7 +#define BM1880_CLK_AXI_SRAM 8 +#define BM1880_CLK_DDR_AXI 9 +#define BM1880_CLK_EFUSE 10 +#define BM1880_CLK_APB_EFUSE 11 +#define BM1880_CLK_AXI5_EMMC 12 +#define BM1880_CLK_EMMC 13 +#define BM1880_CLK_100K_EMMC 14 +#define BM1880_CLK_AXI5_SD 15 +#define BM1880_CLK_SD 16 +#define BM1880_CLK_100K_SD 17 +#define BM1880_CLK_500M_ETH0 18 +#define BM1880_CLK_AXI4_ETH0 19 +#define BM1880_CLK_500M_ETH1 20 +#define BM1880_CLK_AXI4_ETH1 21 +#define BM1880_CLK_AXI1_GDMA 22 +#define BM1880_CLK_APB_GPIO 23 +#define BM1880_CLK_APB_GPIO_INTR 24 +#define BM1880_CLK_GPIO_DB 25 +#define BM1880_CLK_AXI1_MINER 26 +#define BM1880_CLK_AHB_SF 27 +#define BM1880_CLK_SDMA_AXI 28 +#define BM1880_CLK_SDMA_AUD 29 +#define BM1880_CLK_APB_I2C 30 +#define BM1880_CLK_APB_WDT 31 +#define BM1880_CLK_APB_JPEG 32 +#define BM1880_CLK_JPEG_AXI 33 +#define BM1880_CLK_AXI5_NF 34 +#define BM1880_CLK_APB_NF 35 +#define BM1880_CLK_NF 36 +#define BM1880_CLK_APB_PWM 37 +#define BM1880_CLK_DIV_0_RV 38 +#define BM1880_CLK_DIV_1_RV 39 +#define BM1880_CLK_MUX_RV 40 +#define BM1880_CLK_RV 41 +#define BM1880_CLK_APB_SPI 42 +#define BM1880_CLK_TPU_AXI 43 +#define BM1880_CLK_DIV_UART_500M 44 +#define BM1880_CLK_UART_500M 45 +#define BM1880_CLK_APB_UART 46 +#define BM1880_CLK_APB_I2S 47 +#define BM1880_CLK_AXI4_USB 48 +#define BM1880_CLK_APB_USB 49 +#define BM1880_CLK_125M_USB 50 +#define BM1880_CLK_33K_USB 51 +#define BM1880_CLK_DIV_12M_USB 52 +#define BM1880_CLK_12M_USB 53 +#define BM1880_CLK_APB_VIDEO 54 +#define BM1880_CLK_VIDEO_AXI 55 +#define BM1880_CLK_VPP_AXI 56 +#define BM1880_CLK_APB_VPP 57 +#define BM1880_CLK_DIV_0_AXI1 58 +#define BM1880_CLK_DIV_1_AXI1 59 +#define BM1880_CLK_AXI1 60 +#define BM1880_CLK_AXI2 61 +#define BM1880_CLK_AXI3 62 +#define BM1880_CLK_AXI4 63 +#define BM1880_CLK_AXI5 64 +#define BM1880_CLK_DIV_0_AXI6 65 +#define BM1880_CLK_DIV_1_AXI6 66 +#define BM1880_CLK_MUX_AXI6 67 +#define BM1880_CLK_AXI6 68 +#define BM1880_NR_CLKS 69 + +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ From patchwork Sat Aug 17 18:36:09 2019 Content-Type: text/plain; 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Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index d65453f99a99..8471662413da 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -4,6 +4,7 @@ * Author: Manivannan Sadhasivam */ +#include #include #include @@ -66,6 +67,12 @@ ; }; + osc: osc { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -94,6 +101,15 @@ reg = <0x400 0x120>; }; + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + rst: reset-controller@c00 { compatible = "bitmain,bm1880-reset"; reg = <0xc00 0x8>; From patchwork Sat Aug 17 18:36:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 171539 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp990042ily; Sat, 17 Aug 2019 11:36:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJBLb3zcFtis3HOYrBRqv3Up/rmG42YTjfpIKcmn4jXo40Fm6hn0UtYVgeMlgGJJKX9Uz6 X-Received: by 2002:a17:90a:bf01:: with SMTP id c1mr12278156pjs.30.1566067011161; Sat, 17 Aug 2019 11:36:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566067011; cv=none; d=google.com; s=arc-20160816; b=KW22a/TfnOLa+0b/5Qcxt/d9PrkP1Ww38zVEMPVgXdPEAnLVD/dDr4p9EPGtqUabFq ee1hVSGhw3gSFV5/jXUmqgYAfX/gN15y00D15nRKkNSZmHnixGG5dReN/+dXLfNOyF0F cwfPje+0vr8lw6lfoorpZWf3dAvdY3bMwCZlHtCTe5AgMlX00Hu4W7rSedzS2MwN54Cv JFA7l9pyUcIN5UF39F+QBnGiC7XQMa5HyMVzNGdFjSL1sYvbeLv170F+Sa0hZUEbmlbZ DjHn8rk7xYjBgpgi0MUVTsUVQ0Y2Xk3y8LWQ5apD9ZvgaxAzF8XexvQaNJCJlGCDbKdy C2zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kgB5pCuOS2QWyyNQUlCeMbbF7mRF+VE6sHHJ2GG7b1c=; b=YIdxcCeLefhimkGJrdtn59PDj1yEAorJe1P7qdbiuaj2rx14lXW9sorE105ygZykFD 9xx82FufEi95Q9eEIxTbPPFVyMPbckgUSt7Qlz6hQxWd+6Gz4BjuzuKnkZ5CgOGHsQ59 eMgBWBn6aCLQtFpNdU/M4LorQADYTgIpp6FZxA08UBI1AF8avMi5GezY384AeFqKZkvZ aaDg/CKxwtl5+Sdi1xiFdosAwa4HQmLsYIneurYYF3Boz8P4nuin2CZKkvEov6H5xySF PDwYDn6ZmGlovWG36Rod8p2sPkeHIfLmK1MVsY/ZhohQdPkc2vrG3Z4A1tLgoFOk5faC udkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uW56X9mB; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts | 9 --------- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts index 3e8c70778e24..7a2c7f9c2660 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts +++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts @@ -49,12 +49,6 @@ reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <500000000>; - #clock-cells = <0>; - }; - soc { gpio0: gpio@50027000 { porta: gpio-controller@0 { @@ -173,21 +167,18 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &uart2 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_default>; }; diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index 8471662413da..fa6e6905f588 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -174,6 +174,9 @@ uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -184,6 +187,9 @@ uart1: serial@5801A000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801a000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -194,6 +200,9 @@ uart2: serial@5801C000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801c000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -204,6 +213,9 @@ uart3: serial@5801E000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801e000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-shift = <2>; reg-io-width = <4>; From patchwork Sat Aug 17 18:36:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 171541 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp990227ily; Sat, 17 Aug 2019 11:37:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqyMkVn3fTocUhcGOi3c/idaVxH31mu53DqAeXx1Ilh8PNujYos5d7qakhmu7+/HGL4+IFLz X-Received: by 2002:a65:47c1:: with SMTP id f1mr12794589pgs.169.1566067025824; Sat, 17 Aug 2019 11:37:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566067025; cv=none; d=google.com; s=arc-20160816; b=EVKzKUmpKC4H8NQolOpZVmcjiv+r2gvaFv3ySqCzoXoA/orzc3AT/y/+pggh0LW8Pg ZqQX5bENZChZQ2nL3KjxG+aOa7dAe592w2JjWcR+8HnO61y6vs7p/KgET/5drPTJjh9g VacKmcPRq+uXvi5BKeBzObSO8nYEgqgiM+d6rjid0drEBIfLfNT9Lek3Wq6P4j013L0U unJaYdbuukv5h3ep1BTcAqgqI0ZSOnWtNFaeM41LTkt9Z4dzWP1cg9Hi/fKSTRtBM+0M TOGWB2yWCJoAnQgk4kG8dVLFDcOvD9BDFOzxUmIw246TBctK/zouFpXifcm7NQnaWUX5 85kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=K+pJPk2iXl0LixGuiysFHZxmO1vjBGFGOdrJivWtPCQ=; b=JX9CpMeDQbi1RpTYHyd2KfsoHnn4XJyeOSaZ9B24BuovLCd9M5yMLUomfSmLXGMimM hqAYHm2i6kdYg65j1+RroD/iHCh52+2C/9RR8p58Ae+NoHdazSgVgP2+C+vEjcpMP0s+ H0OcygwhzprYlt4EwodhxkPFtj7RIU4TwhaBXUPgrUHetjYDhBz4xnKgnY3r9So7HTFI vpvswh3vYgmlXDOr9JpIiaRI+1ryRWUtdssa0dGK7SJLifBKVRfPM7/EITkZMU4YPv9M TuD+yjxtZ03Ckncg3WC4W3ulFFab+9F8cZmoBF69Xa8ukIpDx6g94CF4HJ4IrtQu8vRZ QsHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dqguwweG; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index 997a4f8fe88e..280defec35b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1503,8 +1503,10 @@ M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/bitmain/ +F: drivers/clk/clk-bm1880.c F: drivers/pinctrl/pinctrl-bm1880.c F: Documentation/devicetree/bindings/arm/bitmain.yaml +F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt ARM/CALXEDA HIGHBANK ARCHITECTURE