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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id bi8-20020a05620a318800b007671cfe8a18sm2833350qkb.13.2023.11.14.09.44.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 09:44:03 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/4] drm/msm/dsi: add a comment to explain pkt_per_line encoding Date: Tue, 14 Nov 2023 12:42:14 -0500 Message-Id: <20231114174218.19765-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114174218.19765-1-jonathan@marek.ca> References: <20231114174218.19765-1-jonathan@marek.ca> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index bddc57726fb9..2ea2fc105fbf 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -875,6 +875,8 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits + * + * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); From patchwork Tue Nov 14 17:42:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 743824 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92B292C194 for ; Tue, 14 Nov 2023 17:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marek.ca header.i=@marek.ca header.b="H46kxdtM" Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5ED6192 for ; Tue, 14 Nov 2023 09:44:14 -0800 (PST) Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-77ba6d5123fso1561585a.0 for ; Tue, 14 Nov 2023 09:44:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1699983853; x=1700588653; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LxJSud2bUpEWb5+zdKhsCdpc+jFCEiyn/rkkbqMyRnU=; b=H46kxdtM39JzFf+LiuZsCA4xkC9uXqQPJJmPtN8byJufdLblbxs8j9x84ekLl5Vd6e aMsG4JU+0vI8Pv/bFXzOx5UoA5+ZTlCkWfQltXAe70Spdhb3h1OetvPcn7QRjcMuhWaX HEQz5WszLmr6TEw6wJosYC3CUwUr8TYJ9EpZ2+WsUXzPrjkyZ2KI1RJCSuNzvs08MkQb CifyUDKl6k5fMz2iP9MRTIHx5Y0G7qXmNLzAW3GUozrRUCCIWCZbt7PCSSHiyUHCq9+u tM6F8UN11YjPbSdBEeZv1tvKToSishGG5eHPImFn7u8vMJz0RowHq4bjEOTKqLxKR7bj 6EaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699983853; x=1700588653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LxJSud2bUpEWb5+zdKhsCdpc+jFCEiyn/rkkbqMyRnU=; b=Rk1RzNGMed/TGr+2NKjR3JAL6IOoWAMm83k9UNnxT3166sPrT7HXVwVVHxgQoyqo6I WP9hpPdXTqK0r+h8XF/dji9/DF7LTKH3Yg8tkt8JZm3bTuY3xa79juKj7JAHRuhXEb3v /1lmOjtUD9qx2aW2PjfZ7Lh/6Lzu++8yoVO3iFefBRlbR0NTu81Hxk7Hxk629EQqIfqz EqbyWHB86AeDE0QZfCD8ydaKIQVNAhDEHTXImytJxs3GplSABg5aVjmY7juus8fH8VpS zN/tsRyHTe0px2cQ7lG4NbcO6ApL+MZ8CcFs57nDkIrJ2jone6k4+Pnu00BwhtUt3qPq 2k3Q== X-Gm-Message-State: AOJu0YxEwFVT88Ug5p56rDjj62mQQm/UYxo4sHuDP2v5LUFtFTv7tShk dOPNEw/Kugcf83TSQgxybK8QdA== X-Google-Smtp-Source: AGHT+IFQfSiyA6caJXGmA0kjldo9K1Mp143S3RfZtOQoQPR93hcHUbZgAlUeJDg/XI9hn6gk8MAd8A== X-Received: by 2002:a05:620a:1993:b0:76c:b7f0:2bc9 with SMTP id bm19-20020a05620a199300b0076cb7f02bc9mr5333777qkb.16.1699983853651; Tue, 14 Nov 2023 09:44:13 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id bi8-20020a05620a318800b007671cfe8a18sm2833350qkb.13.2023.11.14.09.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 09:44:13 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , Doug Anderson , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/4] drm/msm/dsi: fix DSC for the bonded DSI case Date: Tue, 14 Nov 2023 12:42:16 -0500 Message-Id: <20231114174218.19765-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114174218.19765-1-jonathan@marek.ca> References: <20231114174218.19765-1-jonathan@marek.ca> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For the bonded DSI case, DSC pic_width and timing calculations should use the width of a single panel instead of the total combined width. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi.h | 3 ++- drivers/gpu/drm/msm/dsi/dsi_host.c | 20 +++++++++++--------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 28379b1af63f..3a641e69447c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -93,7 +93,8 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode, + bool is_bonded_dsi); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7284346ab787..a6286eb9d006 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -938,8 +938,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) mode->hdisplay, mode->vdisplay); return; } - - dsc->pic_width = mode->hdisplay; + dsc->pic_width = hdisplay; dsc->pic_height = mode->vdisplay; DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); @@ -950,6 +949,11 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (ret) return; + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) + dsi_update_dsc_timing(msm_host, false, hdisplay); + else + dsi_update_dsc_timing(msm_host, true, hdisplay); + /* Divide the display by 3 but keep back/font porch and * pulse width same */ @@ -966,9 +970,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) } if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, false, mode->hdisplay); - dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -987,9 +988,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, true, mode->hdisplay); - /* image data and 1 byte write_memory_start cmd */ if (!msm_host->dsc) wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; @@ -2487,7 +2485,8 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, } enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + bool is_bonded_dsi) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); struct drm_dsc_config *dsc = msm_host->dsc; @@ -2497,6 +2496,9 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, if (!msm_host->dsc) return MODE_OK; + if (is_bonded_dsi) + pic_width = mode->hdisplay / 2; + if (pic_width % dsc->slice_width) { pr_err("DSI: pic_width %d has to be multiple of slice %d\n", pic_width, dsc->slice_width); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 896f369fdd53..2ca1a7ca3659 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -455,7 +455,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, return MODE_ERROR; } - return msm_dsi_host_check_dsc(host, mode); + return msm_dsi_host_check_dsc(host, mode, IS_BONDED_DSI()); } static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {