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Mon, 13 Nov 2023 10:17:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , qemu-stable@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Jiaxun Yang Subject: [PULL 1/5] hw/mips: LOONGSON3V depends on UNIMP device Date: Mon, 13 Nov 2023 19:17:40 +0100 Message-ID: <20231113181744.49537-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113181744.49537-1-philmd@linaro.org> References: <20231113181744.49537-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Marc-André Lureau Signed-off-by: Marc-André Lureau Cc: qemu-stable@nongnu.org Fixes: c76b409fef ("hw/mips: Add Loongson-3 machine support") Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231107140615.3034763-1-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 66ec536e06..505381a0bb 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -46,6 +46,7 @@ config LOONGSON3V select PCI_EXPRESS_GENERIC_BRIDGE select MSI_NONBROKEN select FW_CFG_MIPS + select UNIMP config MIPS_CPS bool From patchwork Mon Nov 13 18:17:41 2023 Content-Type: text/plain; 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Fixes: 02218aedb1 ("hw/display/vmware_vga: replace fprintf calls with trace events") Signed-off-by: Alexandra Diupina Reviewed-by: Thomas Huth Message-ID: <20231110174104.13280-1-adiupina@astralinux.ru> Signed-off-by: Philippe Mathieu-Daudé --- hw/display/vmware_vga.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index 7490d43881..3f26bea190 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -336,8 +336,8 @@ static inline bool vmsvga_verify_rect(DisplaySurface *surface, return false; } if (h > SVGA_MAX_HEIGHT) { - trace_vmware_verify_rect_greater_than_bound(name, "y", SVGA_MAX_HEIGHT, - y); + trace_vmware_verify_rect_greater_than_bound(name, "h", SVGA_MAX_HEIGHT, + h); return false; } if (y + h > surface_height(surface)) { From patchwork Mon Nov 13 18:17:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 743478 Delivered-To: patch@linaro.org Received: by 2002:a5d:67cf:0:b0:32d:baff:b0ca with SMTP id n15csp1773516wrw; Mon, 13 Nov 2023 10:18:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IEU4CZ7KajoIJ1Su3+3gdbsd6MJdI2ZcBooXl7ZG5zSz0uckm3B/83GEHI8TVtZRdI/GrVd X-Received: by 2002:a81:498e:0:b0:5be:7067:e1eb with SMTP id w136-20020a81498e000000b005be7067e1ebmr5744209ywa.18.1699899504452; Mon, 13 Nov 2023 10:18:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699899504; cv=none; d=google.com; s=arc-20160816; b=bBAAm5wWzeSqV5Zk3FNLrDTGD/34TAI7H2ixsmACeUTxTHwRVIEvnfZd9LREePrV8E pt2D3YCu9Ys2fTsBWtdF+ZKI48xq4QaqKquH4mjopDeuMNgWFxckveDJpCQCenUcTHyC j9uo2YZngySx/XJvCpLhZ9ac/zorj1mgpQVuLiEGHgPn0MQLBmHwmvXzVlCJNb/eZAq1 jaKTRy/7mI1sunVLIWoAJ3goGOWexlBSYtiwje2IE4MNnzfRCTnvxC2/NcUzxCkfQngY dAnU+iOTotCVE8iMyqZFaMk1mrHNttS+8MvJnbvs6gdIoqk/svLZ+o7CHRSAbza0swli xQEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cIDYmW795avdqlddhv1SI9qKCLfA9vhXJay8WJOaVbQ=; fh=4WcwRIKVvPrCQdmAH7idwQmhswG3NxTnPC6nP87Zg9g=; b=xACXTrPc+0r9pN8CArzePVftvf3XNl2EO4MrB/XRkl44iDTxsi3Tw3hBl+OPDXNteM xHz9S3mJVXS+i1OoXPfBjxcJi682BZ31zWopUlR55keQoeoluLhAdFm6smORMkD9UaKS KkJLScskFpio2mu48E75cy0Aj+yDoG6SGMcEVM2qqNgFQ/1u71wp3AajN2AN2xkcDWe4 ZV0Jganvi7gPW2fIPL13jL+DR1LdWdUSg5Y/pwUEY6it/0wxrobQWY3EcIrTIr/4ZodC aM9xlkcI6C+gtF9ljB5RzbM8NqSRbtNm5AIvwKXl2mb1Rord4fIz6KJkZ9jrKH1rAE4s r6/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m3QClHer; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This change adds a test to make sure QEMU fails to start with a specific error message when an attempt is made to start a VM with more memory than what the processor can directly address. The test also checks for passing cases when the address space of the processor is capable of addressing all memory. Boundary cases are tested. CC: imammedo@redhat.com CC: David Hildenbrand Acked-by: David Hildenbrand Acked-by: Philippe Mathieu-Daudé Signed-off-by: Ani Sinha Message-ID: <20231109045601.33349-1-anisinha@redhat.com> Message-ID: [PMD: Use SPDX tag] Signed-off-by: Philippe Mathieu-Daudé --- tests/avocado/mem-addr-space-check.py | 356 ++++++++++++++++++++++++++ 1 file changed, 356 insertions(+) create mode 100644 tests/avocado/mem-addr-space-check.py diff --git a/tests/avocado/mem-addr-space-check.py b/tests/avocado/mem-addr-space-check.py new file mode 100644 index 0000000000..be949222a4 --- /dev/null +++ b/tests/avocado/mem-addr-space-check.py @@ -0,0 +1,356 @@ +# Check for crash when using memory beyond the available guest processor +# address space. +# +# Copyright (c) 2023 Red Hat, Inc. +# +# Author: +# Ani Sinha +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from avocado_qemu import QemuSystemTest +import signal +import time + +class MemAddrCheck(QemuSystemTest): + # after launch, in order to generate the logs from QEMU we need to + # wait for some time. Launching and then immediately shutting down + # the VM generates empty logs. A delay of 1 second is added for + # this reason. + DELAY_Q35_BOOT_SEQUENCE = 1 + + # first, lets test some 32-bit processors. + # for all 32-bit cases, pci64_hole_size is 0. + def test_phybits_low_pse36(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + With pse36 feature ON, a processor has 36 bits of addressing. So it can + access up to a maximum of 64GiB of memory. Memory hotplug region begins + at 4 GiB boundary when "above_4g_mem_size" is 0 (this would be true when + we have 0.5 GiB of VM memory, see pc_q35_init()). This means total + hotpluggable memory size is 60 GiB. Per slot, we reserve 1 GiB of memory + for dimm alignment for all newer machines (see enforce_aligned_dimm + property for pc machines and pc_get_device_memory_range()). That leaves + total hotpluggable actual memory size of 59 GiB. If the VM is started + with 0.5 GiB of memory, maxmem should be set to a maximum value of + 59.5 GiB to ensure that the processor can address all memory directly. + Note that 64-bit pci hole size is 0 in this case. If maxmem is set to + 59.6G, QEMU should fail to start with a message "phy-bits are too low". + If maxmem is set to 59.5G with all other QEMU parameters identical, QEMU + should start fine. + """ + self.vm.add_args('-S', '-machine', 'q35', '-m', + '512,slots=1,maxmem=59.6G', + '-cpu', 'pentium,pse36=on', '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_low_pae(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + With pae feature ON, a processor has 36 bits of addressing. So it can + access up to a maximum of 64GiB of memory. Rest is the same as the case + with pse36 above. + """ + self.vm.add_args('-S', '-machine', 'q35', '-m', + '512,slots=1,maxmem=59.6G', + '-cpu', 'pentium,pae=on', '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_pentium_pse36(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Setting maxmem to 59.5G and making sure that QEMU can start with the + same options as the failing case above with pse36 cpu feature. + """ + self.vm.add_args('-machine', 'q35', '-m', + '512,slots=1,maxmem=59.5G', + '-cpu', 'pentium,pse36=on', '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_pentium_pae(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Test is same as above but now with pae cpu feature turned on. + Setting maxmem to 59.5G and making sure that QEMU can start fine + with the same options as the case above. + """ + self.vm.add_args('-machine', 'q35', '-m', + '512,slots=1,maxmem=59.5G', + '-cpu', 'pentium,pae=on', '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_pentium2(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Pentium2 has 36 bits of addressing, so its same as pentium + with pse36 ON. + """ + self.vm.add_args('-machine', 'q35', '-m', + '512,slots=1,maxmem=59.5G', + '-cpu', 'pentium2', '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_low_nonpse36(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Pentium processor has 32 bits of addressing without pse36 or pae + so it can access physical address up to 4 GiB. Setting maxmem to + 4 GiB should make QEMU fail to start with "phys-bits too low" + message because the region for memory hotplug is always placed + above 4 GiB due to the PCI hole and simplicity. + """ + self.vm.add_args('-S', '-machine', 'q35', '-m', + '512,slots=1,maxmem=4G', + '-cpu', 'pentium', '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + # now lets test some 64-bit CPU cases. + def test_phybits_low_tcg_q35_70_amd(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + For q35 7.1 machines and above, there is a HT window that starts at + 1024 GiB and ends at 1 TiB - 1. If the max GPA falls in this range, + "above_4G" memory is adjusted to start at 1 TiB boundary for AMD cpus + in the default case. Lets test without that case for machines 7.0. + For q35-7.0 machines, "above 4G" memory starts are 4G. + pci64_hole size is 32 GiB. Since TCG_PHYS_ADDR_BITS is defined to + be 40, TCG emulated CPUs have maximum of 1 TiB (1024 GiB) of + directly addressible memory. + Hence, maxmem value at most can be + 1024 GiB - 4 GiB - 1 GiB per slot for alignment - 32 GiB + 0.5 GiB + which is equal to 987.5 GiB. Setting the value to 988 GiB should + make QEMU fail with the error message. + """ + self.vm.add_args('-S', '-machine', 'pc-q35-7.0', '-m', + '512,slots=1,maxmem=988G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_low_tcg_q35_71_amd(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + AMD_HT_START is defined to be at 1012 GiB. So for q35 machines + version > 7.0 and AMD cpus, instead of 1024 GiB limit for 40 bit + processor address space, it has to be 1012 GiB , that is 12 GiB + less than the case above in order to accomodate HT hole. + Make sure QEMU fails when maxmem size is 976 GiB (12 GiB less + than 988 GiB). + """ + self.vm.add_args('-S', '-machine', 'pc-q35-7.1', '-m', + '512,slots=1,maxmem=976G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_tcg_q35_70_amd(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Same as q35-7.0 AMD case except that here we check that QEMU can + successfully start when maxmem is < 988G. + """ + self.vm.add_args('-S', '-machine', 'pc-q35-7.0', '-m', + '512,slots=1,maxmem=987.5G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_tcg_q35_71_amd(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Same as q35-7.1 AMD case except that here we check that QEMU can + successfully start when maxmem is < 976G. + """ + self.vm.add_args('-S', '-machine', 'pc-q35-7.1', '-m', + '512,slots=1,maxmem=975.5G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_tcg_q35_71_intel(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Same parameters as test_phybits_low_tcg_q35_71_amd() but use + Intel cpu instead. QEMU should start fine in this case as + "above_4G" memory starts at 4G. + """ + self.vm.add_args('-S', '-cpu', 'Skylake-Server', + '-machine', 'pc-q35-7.1', '-m', + '512,slots=1,maxmem=976G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_low_tcg_q35_71_amd_41bits(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + AMD processor with 41 bits. Max cpu hw address = 2 TiB. + By setting maxram above 1012 GiB - 32 GiB - 4 GiB = 976 GiB, we can + force "above_4G" memory to start at 1 TiB for q35-7.1 machines + (max GPA will be above AMD_HT_START which is defined as 1012 GiB). + + With pci_64_hole size at 32 GiB, in this case, maxmem should be 991.5 + GiB with 1 GiB per slot for alignment and 0.5 GiB as non-hotplug + memory for the VM (1024 - 32 - 1 + 0.5). With 992 GiB, QEMU should + fail to start. + """ + self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41', + '-machine', 'pc-q35-7.1', '-m', + '512,slots=1,maxmem=992G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_tcg_q35_71_amd_41bits(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + AMD processor with 41 bits. Max cpu hw address = 2 TiB. + Same as above but by setting maxram beween 976 GiB and 992 Gib, + QEMU should start fine. + """ + self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41', + '-machine', 'pc-q35-7.1', '-m', + '512,slots=1,maxmem=990G', + '-display', 'none', + '-object', 'memory-backend-ram,id=mem1,size=1G', + '-device', 'pc-dimm,id=vm0,memdev=mem1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_low_tcg_q35_intel_cxl(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + cxl memory window starts after memory device range. Here, we use 1 GiB + of cxl window memory. 4G_mem end aligns at 4G. pci64_hole is 32 GiB and + starts after the cxl memory window. + So maxmem here should be at most 986 GiB considering all memory boundary + alignment constraints with 40 bits (1 TiB) of processor physical bits. + """ + self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40', + '-machine', 'q35,cxl=on', '-m', + '512,slots=1,maxmem=987G', + '-display', 'none', + '-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1', + '-M', 'cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=1G') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + self.vm.wait() + self.assertEquals(self.vm.exitcode(), 1, "QEMU exit code should be 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + + def test_phybits_ok_tcg_q35_intel_cxl(self): + """ + :avocado: tags=machine:q35 + :avocado: tags=arch:x86_64 + + Same as above but here we do not reserve any cxl memory window. Hence, + with the exact same parameters as above, QEMU should start fine even + with cxl enabled. + """ + self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40', + '-machine', 'q35,cxl=on', '-m', + '512,slots=1,maxmem=987G', + '-display', 'none', + '-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1') + self.vm.set_qmp_monitor(enabled=False) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') From patchwork Mon Nov 13 18:17:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 743482 Delivered-To: patch@linaro.org Received: by 2002:a5d:67cf:0:b0:32d:baff:b0ca with SMTP id n15csp1773909wrw; Mon, 13 Nov 2023 10:19:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IFXHLPisi092EY+CDMh4ZAMxRAkXIg+MGbGfhns95ZSoVyGL6ccvtCZPtpqFieTnY2VPZ4k X-Received: by 2002:a25:ae56:0:b0:d9c:a583:9db0 with SMTP id g22-20020a25ae56000000b00d9ca5839db0mr6670084ybe.39.1699899556952; Mon, 13 Nov 2023 10:19:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699899556; cv=none; d=google.com; s=arc-20160816; b=e4LJHEwc2eUKPl3VmndNdw5VS5DWyA6SkKPkYlAsHCRax0kMuM1p3ggkrQsyJ4sZGj 013N/3FaUC8i9TtlKVKpxlVog17FCHhCMWfpoUycyk5p4JjU6upEveJkqbre+Peux8wv kSs9gPElqNF1wRfgKByduX1NqD6ap7CbPdKG3nA8Rupr3JyRgQTLHVi5ZH6CICbVY5/F lmq2hFatkAe7GpXDBj98Gt7Hn4+qN8drROmjwbYCQHt9dn7nS1xQqmM1ooc9W3B/9/Q9 pOGIuZje9Utq8rmCL/beW06Oz+uW3nqAU8RttwuUTPASq/MCSL3HtPEXVghgBJein5EC 1SjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ifmwVFTsAvMvKqxRkmI19PrzZdtj10CaHWbOV7iF2UM=; fh=xhTf0SM7jzWRyUj14BX5Q5Fv3LT4hL4rStqTr6cdsYU=; b=oPvtCJL8Ta0mXo4BROcSetQZYLzPHxAHEbi2bn63GCvzl/07WuL8ODF38b2TpsmGeS /Kef5v2k3HungKXCm1Sp6qwV7MF+OfLU3wz2rD6hn3iIue3rp1M3DMPGRxeDcgBu54Zq m1nfzQAPXGRc98PyPk+e9PvQ7MTpnhO7he+cq2DnluIaTWz72zxnoxXhMxR+9AhLChhv q7l7SOpr8wjBjAoWJ8YLFlX0cPRm9ZngtJaobO6O81VrRLjfXyzjIaO7N9Kfg95z6mlm rIdSD/Vr/D08g6f9dNPoauq7VczflgWzWscydmaXaWfjnV6uHFYXNR117PhwnaxN7lZV JHSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yveT8bMv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Silence the warning by using raw strings here instead. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231113140721.46903-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- tests/avocado/machine_s390_ccw_virtio.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/avocado/machine_s390_ccw_virtio.py b/tests/avocado/machine_s390_ccw_virtio.py index e1f493bc44..ffd914ded9 100644 --- a/tests/avocado/machine_s390_ccw_virtio.py +++ b/tests/avocado/machine_s390_ccw_virtio.py @@ -36,8 +36,8 @@ def wait_for_crw_reports(self): dmesg_clear_count = 1 def clear_guest_dmesg(self): exec_command_and_wait_for_pattern(self, 'dmesg -c > /dev/null; ' - 'echo dm_clear\ ' + str(self.dmesg_clear_count), - 'dm_clear ' + str(self.dmesg_clear_count)) + r'echo dm_clear\ ' + str(self.dmesg_clear_count), + r'dm_clear ' + str(self.dmesg_clear_count)) self.dmesg_clear_count += 1 def test_s390x_devices(self): @@ -121,15 +121,15 @@ def test_s390x_devices(self): 'cat /sys/bus/ccw/devices/0.1.1111/cutype', '3832/01') exec_command_and_wait_for_pattern(self, - 'cat /sys/bus/pci/devices/0005\:00\:00.0/subsystem_vendor', - '0x1af4') + r'cat /sys/bus/pci/devices/0005\:00\:00.0/subsystem_vendor', + r'0x1af4') exec_command_and_wait_for_pattern(self, - 'cat /sys/bus/pci/devices/0005\:00\:00.0/subsystem_device', - '0x0001') + r'cat /sys/bus/pci/devices/0005\:00\:00.0/subsystem_device', + r'0x0001') # check fid propagation exec_command_and_wait_for_pattern(self, - 'cat /sys/bus/pci/devices/000a\:00\:00.0/function_id', - '0x0000000c') + r'cat /sys/bus/pci/devices/000a\:00\:00.0/function_id', + r'0x0000000c') # add another device self.clear_guest_dmesg() self.vm.cmd('device_add', driver='virtio-net-ccw', @@ -235,7 +235,7 @@ def test_s390x_fedora(self): 'while ! (dmesg | grep gpudrmfb) ; do sleep 1 ; done', 'virtio_gpudrmfb frame buffer device') exec_command_and_wait_for_pattern(self, - 'echo -e "\e[?25l" > /dev/tty0', ':/#') + r'echo -e "\e[?25l" > /dev/tty0', ':/#') exec_command_and_wait_for_pattern(self, 'for ((i=0;i<250;i++)); do ' 'echo " The qu ick fo x j ump s o ver a laz y d og" >> fox.txt;' 'done', From patchwork Mon Nov 13 18:17:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 743481 Delivered-To: patch@linaro.org Received: by 2002:a5d:67cf:0:b0:32d:baff:b0ca with SMTP id n15csp1773827wrw; Mon, 13 Nov 2023 10:19:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IGAn2euXCasd6rXpFj+Y+UPC2XyJ4paWXYMXvWVqDoZ3BCZOoNErZ76Pm6X4VUu3qyiN7sL X-Received: by 2002:ac8:7d54:0:b0:421:bd62:ff6e with SMTP id h20-20020ac87d54000000b00421bd62ff6emr11113756qtb.68.1699899547137; Mon, 13 Nov 2023 10:19:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699899547; cv=none; d=google.com; s=arc-20160816; b=kgVvImH1tOrYjVM9nDY/WtstgFEd0TiEUzBcNIgrZhGz7LU5pDyyappmi11HYv3LBd 7NV30VhulXnbpcpDF+sq/uHQCmiCgHre7+bPT4WDsa91S0zf0HFAJGIBWwJaIeqlEn/n k5IqS78i+oJz52efPkkQQNkBIjeU2xWkMAph8JTvova3Etp+TLybUReBhh7x4Na/UNoD n30Q6cbObPhbI1en1zv1NicoiePSu4Kk4IQ/pLD7HGHLQh2fo5VGLybRofOkuLb8YnlE TBfWFDfwQ2WyyTzbyHRj/o9FK1GUhqGrLBV5Z+qfwrRkb/Ug0xX+3bzVPwY0+jdppso8 5Rrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lf1rwmHWhRIdzPASs5If2b7PrmSQYo/bsdIg+fGMWc0=; fh=f7x4MWM5hq9W0sIWTZGJgDXpD202fmlvLAGaZ3NqDbo=; b=sGrZNX0HotM0Z3k8mRRxKG05v6TDApRiuoP4xsoN9lHEQLnUNvz3Nwr4b7WvRn13Mq gyOUPo4jzvMklumoztU7YrC35PxiNENZI8jcTq/vV+oi389hYKB2j6RN+DvMgLoWjLOI GIOxXqzJZJz9d/j7B5oRF1JEoNEk7qRda8ZUpqf+kdcDOaAOqX6/J2LdsdK/Wf4Gah5d p6Q5VanJvUmuFASdFMYTSMOu7UsLHExD3SnKdWRNSdgneIGJFSw8wO6aA4X3cS0/2/+J 3FqjgnSZMXQKE/s15jTZkOS3Dp9zll4V0H5lFU2fQl16WPlHF6e7rbdwjP1TwFIdcoXP lv5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AWRfajKq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Switch to the new mailing list address. Cc: Philippe Mathieu-Daudé Cc: Vivek Goyal Cc: German Maglione Cc: Hanna Czenczek Signed-off-by: Stefan Hajnoczi Reviewed-by: German Maglione Message-ID: <20231111004920.148348-1-stefanha@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index e73a3ff544..c52df9f76c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2241,7 +2241,7 @@ M: Stefan Hajnoczi S: Supported F: hw/virtio/vhost-user-fs* F: include/hw/virtio/vhost-user-fs.h -L: virtio-fs@redhat.com +L: virtio-fs@lists.linux.dev virtio-input M: Gerd Hoffmann