From patchwork Fri Nov 10 00:30:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 743351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E074C4332F for ; Fri, 10 Nov 2023 00:30:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231624AbjKJAah (ORCPT ); Thu, 9 Nov 2023 19:30:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229581AbjKJAag (ORCPT ); Thu, 9 Nov 2023 19:30:36 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40E542D7C; Thu, 9 Nov 2023 16:30:34 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1FPd-00041W-2M; Fri, 10 Nov 2023 00:30:17 +0000 Date: Fri, 10 Nov 2023 00:30:13 +0000 From: Daniel Golle To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/2] dt-bindings: watchdog: mediatek,mtk-wdt: add MT7988 watchdog and toprgu Message-ID: <6912f6f406bc45674020681184f3eeca2f2cb63f.1699576174.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add binding description for mediatek,mt7988-wdt. Signed-off-by: Daniel Golle --- .../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + include/dt-bindings/reset/mediatek,mt7988-resets.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index cc502838bc398..8d2520241e37f 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt6735-wdt - mediatek,mt6795-wdt - mediatek,mt7986-wdt + - mediatek,mt7988-wdt - mediatek,mt8183-wdt - mediatek,mt8186-wdt - mediatek,mt8188-wdt diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h new file mode 100644 index 0000000000000..fa7c937505e08 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +/* TOPRGU resets */ +#define MT7988_TOPRGU_SGMII0_GRST 1 +#define MT7988_TOPRGU_SGMII1_GRST 2 +#define MT7988_TOPRGU_XFI0_GRST 12 +#define MT7988_TOPRGU_XFI1_GRST 13 +#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14 +#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15 +#define MT7988_TOPRGU_XFI_PLL_GRST 16 + +#define MT7988_TOPRGU_SW_RST_NUM 24 From patchwork Fri Nov 10 00:30:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 743056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8A12C4332F for ; Fri, 10 Nov 2023 00:30:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233763AbjKJAav (ORCPT ); Thu, 9 Nov 2023 19:30:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229581AbjKJAau (ORCPT ); Thu, 9 Nov 2023 19:30:50 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3921F2590; Thu, 9 Nov 2023 16:30:48 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1FPz-00041m-2U; Fri, 10 Nov 2023 00:30:39 +0000 Date: Fri, 10 Nov 2023 00:30:36 +0000 From: Daniel Golle To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 2/2] watchdog: mediatek: mt7988: add wdt support Message-ID: References: <6912f6f406bc45674020681184f3eeca2f2cb63f.1699576174.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <6912f6f406bc45674020681184f3eeca2f2cb63f.1699576174.git.daniel@makrotopia.org> Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add support for watchdog and reset generator unit of the MediaTek MT7988 SoC. Signed-off-by: Daniel Golle --- drivers/watchdog/mtk_wdt.c | 56 +++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index b2330b16b497a..b98b8c29735aa 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -58,6 +59,8 @@ #define WDT_SWSYSRST 0x18U #define WDT_SWSYS_RST_KEY 0x88000000 +#define WDT_SWSYSRST_EN 0xfc + #define DRV_NAME "mtk-wdt" #define DRV_VERSION "1.0" @@ -71,44 +74,85 @@ struct mtk_wdt_dev { struct reset_controller_dev rcdev; bool disable_wdt_extrst; bool reset_by_toprgu; + bool has_swsysrst_en; }; struct mtk_wdt_data { int toprgu_sw_rst_num; + bool has_swsysrst_en; }; static const struct mtk_wdt_data mt2712_data = { .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; static const struct mtk_wdt_data mt6795_data = { .toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; static const struct mtk_wdt_data mt7986_data = { .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, +}; + +static const struct mtk_wdt_data mt7988_data = { + .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = true, }; static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; static const struct mtk_wdt_data mt8186_data = { .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; static const struct mtk_wdt_data mt8188_data = { .toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; static const struct mtk_wdt_data mt8192_data = { .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; static const struct mtk_wdt_data mt8195_data = { .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, + .has_swsysrst_en = false, }; +static int toprgu_reset_sw_enable(struct reset_controller_dev *rcdev, + unsigned long id, bool enable) +{ + unsigned int tmp; + unsigned long flags; + struct mtk_wdt_dev *data = + container_of(rcdev, struct mtk_wdt_dev, rcdev); + + if (!data->has_swsysrst_en) + return 0; + + spin_lock_irqsave(&data->lock, flags); + + tmp = readl(data->wdt_base + WDT_SWSYSRST_EN); + if (enable) + tmp |= BIT(id); + else + tmp &= ~BIT(id); + + writel(tmp, data->wdt_base + WDT_SWSYSRST_EN); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -135,13 +179,20 @@ static int toprgu_reset_update(struct reset_controller_dev *rcdev, static int toprgu_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { + int ret; + + ret = toprgu_reset_sw_enable(rcdev, id, true); + if (ret) + return ret; + return toprgu_reset_update(rcdev, id, true); } static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { - return toprgu_reset_update(rcdev, id, false); + toprgu_reset_update(rcdev, id, false); + return toprgu_reset_sw_enable(rcdev, id, false); } static int toprgu_reset(struct reset_controller_dev *rcdev, @@ -406,6 +457,8 @@ static int mtk_wdt_probe(struct platform_device *pdev) wdt_data->toprgu_sw_rst_num); if (err) return err; + + mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en; } mtk_wdt->disable_wdt_extrst = @@ -444,6 +497,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, + { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },