From patchwork Fri Nov 10 09:19:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 742911 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEB7510A22; Fri, 10 Nov 2023 09:20:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Bg2yebPe" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 506272BE0B; Fri, 10 Nov 2023 01:20:16 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AA7gTCc018016; Fri, 10 Nov 2023 09:20:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=WTE+qVUfTHI5VNl6dbyRtN/JhVRxKZcIKC4hsuTCdOs=; b=Bg2yebPe9zR9JTZqxI+AfKYtjIqJcRXaGyWRy4cfaR1GYqSvaK8I93YgQFHmym4ft8ja fyKkaWFP2gnV6z7u1MH6Z/yXgCGtPwZ/47U/OPTtf6bV98PvPBGa7Ga6B6Rd4R7sytob w632+9qwjYrMzy0CumxbOmChYdZaAc+bFT/z1MhMfBPRhgOCrCFsdVL8bv3IuHgkS8pX kya8BxHV7v68W1pHRj0RlcxyDYvbmB5oONQ8ZMT1Ftoat/lBf9vbuZxxFMirQLCHR9gr imOS6oAbfm22IIT3tKrtcTkbo4+GwSyutcuz/YfB1YF4Au7cFHrTP9NseF/Z8wEoaf5Z xQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u8u2bu7yq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:12 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AA9KAV3022817 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:11 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 10 Nov 2023 01:20:03 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v6 01/11] dt-bindings: remoteproc: qcom: Add support for multipd model Date: Fri, 10 Nov 2023 14:49:29 +0530 Message-ID: <20231110091939.3025413-2-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> References: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: c1qGLAmOzJTKgU5KCjeo6GGTe7P58cvG X-Proofpoint-ORIG-GUID: c1qGLAmOzJTKgU5KCjeo6GGTe7P58cvG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-10_05,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 mlxscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311100075 Add new binding document for multipd model remoteproc. IPQ5332, IPQ9574 follows multipd model. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in v6: - No changes. Changes in v5: - No changes. Changes in v4: - No changes. Changes in v3: - Pick up R-b tag Changes in v2: - Fixed all comments and rebased on linux-next. - Changed to BSD-3-Clause - Added firmware-name. .../bindings/remoteproc/qcom,multipd-pil.yaml | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml new file mode 100644 index 000000000000..c52ac1640d7a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,multipd-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multipd Secure Peripheral Image Loader + +maintainers: + - Manikanta Mylavarapu + +description: + Multipd Peripheral Image Loader loads firmware and boots Q6 protection domain, + WCSS protection domain remoteproc's on the Qualcomm IPQ9574, IPQ5332 SoC. + Protection domain is similar to process in Linux. Here QDSP6 processor runs + each wifi radio functionality on a separate process. One process can't access + other process resources, so this is termed as PD i.e protection domain. + +properties: + compatible: + enum: + - qcom,ipq5332-q6-mpd + - qcom,ipq9574-q6-mpd + + reg: + maxItems: 1 + + firmware-name: + maxItems: 2 + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown Q6 + - description: Stop Q6 + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + + memory-region: + items: + - description: Q6 reserved region + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + unevaluatedProperties: false + +patternProperties: + "^pd-1|pd-2|pd-3": + type: object + description: + WCSS means 'wireless connectivity sub system', in simple words it's a + wifi radio block. In multipd model, Q6 root protection domain will + provide services to WCSS user protection domain. In other words WCSS + protection domains depends on Q6 protection domain i.e Q6 should be up + before WCSS, similarly Q6 should shut down after all WCSS domains are + down. It can be achieved by building parent-child topology between Q6 + and WCSS domain's i.e keeping wcss node as sub node of Q6 device node. + + properties: + firmware-name: + maxItems: 1 + + interrupts: + items: + - description: Fatal interrupt + - description: Ready interrupt + - description: Spawn acknowledge interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: fatal + - const: ready + - const: spawn-ack + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown WCSS pd + - description: Stop WCSS pd + - description: Spawn WCSS pd + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + - const: spawn + + required: + - firmware-name + - interrupts + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + + additionalProperties: false + +required: + - compatible + - firmware-name + - reg + - interrupts + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + - memory-region + +additionalProperties: false + +examples: + - | + #include + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5332-q6-mpd"; + reg = <0xd100000 0x4040>; + firmware-name = "ath11k/IPQ5332/hw1.0/q6_fw0.mdt", + "ath11k/IPQ5332/hw1.0/iu_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + pd-1 { + firmware-name = "ath11k/IPQ5332/hw1.0/q6_fw1.mdt"; + interrupts-extended = <&wcss_smp2p_in 8 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 9 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 12 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 11 IRQ_TYPE_NONE>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + }; From patchwork Fri Nov 10 09:19:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 742910 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2956411C86; Fri, 10 Nov 2023 09:20:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LI4afS+6" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 326732BE17; Fri, 10 Nov 2023 01:20:30 -0800 (PST) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AA7fgOa031331; Fri, 10 Nov 2023 09:20:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=3oXcR2fgkQUnVZRUf8EM5mbxCM+GrpWo02mNYAvfJSQ=; b=LI4afS+6vFY5aZVf788+S0ytveto+0qWiYQJF0Df0CFXsU7c55IHagoi2yEzxBKbyVS8 oDgppMgcEny/uLKmC90vg6J19mvnGWO3DY3YXPPBWTHSPZSjOKRBzfTHz1B9KspP0Dxb Co6hDYrEevt3c6EY2/nCQJPPdDgMlJt36rOI8WYwnBC8fTaGv42ClymvknQPar55K66r kvEQtqnuw1VpSqTEd8vCXcdb+xavVI7vwup8BCGFeHnVDfShTKCkWQZTjgE4d7AW2p3N Hz8tkbottASV9g5R/nQWJG/sfmaJ+bL4PICE8Hap6jzvSJ87yzobdPswow4QbAaWLA6s Eg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u9f3k0e7c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:26 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AA9KPdr032202 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:25 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 10 Nov 2023 01:20:17 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v6 03/11] clk: qcom: ipq9574: remove q6 bring up clocks Date: Fri, 10 Nov 2023 14:49:31 +0530 Message-ID: <20231110091939.3025413-4-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> References: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4tCrXYpbuvVTGXqYZjzsIbiRK2SkxGsf X-Proofpoint-GUID: 4tCrXYpbuvVTGXqYZjzsIbiRK2SkxGsf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-10_05,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 bulkscore=0 mlxscore=0 priorityscore=1501 phishscore=0 clxscore=1015 mlxlogscore=998 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311100075 In multipd model Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu --- Changes in v6: - Rebased on linux-next. Changes in v5: - Rebased on linux-next. Changes in v4: - In V3 series this patch is [04/11]. Here it's moved to [03/11] because to compile dt-bindings patches. Changes in v3: - Rebased on linux-next. drivers/clk/qcom/gcc-ipq9574.c | 326 --------------------------------- 1 file changed, 326 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e8190108e1ae..e6d8ab5fbf29 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2567,24 +2567,6 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = { }, }; -static struct clk_branch gcc_q6ss_boot_clk = { - .halt_reg = 0x25080, - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x25080, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_boot_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_bfdcd_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_snoc_clk = { .halt_reg = 0x17028, .clkr = { @@ -2655,91 +2637,6 @@ static struct clk_rcg2 wcss_ahb_clk_src = { }, }; -static struct clk_branch gcc_q6_ahb_clk = { - .halt_reg = 0x25014, - .clkr = { - .enable_reg = 0x25014, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_ahb_s_clk = { - .halt_reg = 0x25018, - .clkr = { - .enable_reg = 0x25018, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ecahb_clk = { - .halt_reg = 0x25058, - .clkr = { - .enable_reg = 0x25058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_ecahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_acmt_clk = { - .halt_reg = 0x2505c, - .clkr = { - .enable_reg = 0x2505c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_acmt_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { - .halt_reg = 0x2e030, - .clkr = { - .enable_reg = 0x2e030, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_sys_noc_wcss_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(133333333, P_GPLL0, 6, 0, 0), @@ -2760,23 +2657,6 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { }, }; -static struct clk_branch gcc_anoc_wcss_axi_m_clk = { - .halt_reg = 0x2e0a8, - .clkr = { - .enable_reg = 0x2e0a8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_anoc_wcss_axi_m_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_axi_m_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_qdss_at_clk_src[] = { F(240000000, P_GPLL4, 5, 0, 0), { } @@ -2795,40 +2675,6 @@ static struct clk_rcg2 qdss_at_clk_src = { }, }; -static struct clk_branch gcc_q6ss_atbm_clk = { - .halt_reg = 0x2501c, - .clkr = { - .enable_reg = 0x2501c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_atbm_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { - .halt_reg = 0x2503c, - .clkr = { - .enable_reg = 0x2503c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_atb_clk = { .halt_reg = 0x17014, .clkr = { @@ -3065,40 +2911,6 @@ static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { }, }; -static struct clk_branch gcc_q6_tsctr_1to2_clk = { - .halt_reg = 0x25020, - .clkr = { - .enable_reg = 0x25020, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_tsctr_1to2_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { - .halt_reg = 0x25040, - .clkr = { - .enable_reg = 0x25040, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_tsctr_div2_clk = { .halt_reg = 0x2d044, .clkr = { @@ -3273,74 +3085,6 @@ static struct clk_branch gcc_qdss_tsctr_div16_clk = { }, }; -static struct clk_branch gcc_q6ss_pclkdbg_clk = { - .halt_reg = 0x25024, - .clkr = { - .enable_reg = 0x25024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_pclkdbg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_trig_clk = { - .halt_reg = 0x25068, - .clkr = { - .enable_reg = 0x25068, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_trig_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { - .halt_reg = 0x25038, - .clkr = { - .enable_reg = 0x25038, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { - .halt_reg = 0x25044, - .clkr = { - .enable_reg = 0x25044, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_dap_clk = { .halt_reg = 0x2d058, .clkr = { @@ -3462,58 +3206,6 @@ static struct clk_rcg2 q6_axi_clk_src = { }, }; -static struct clk_branch gcc_q6_axim_clk = { - .halt_reg = 0x2500c, - .clkr = { - .enable_reg = 0x2500c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_axim_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_q6_tbu_clk = { - .halt_reg = 0x12050, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(6), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_q6_tbu_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mem_noc_q6_axi_clk = { - .halt_reg = 0x19010, - .clkr = { - .enable_reg = 0x19010, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_q6_axi_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_q6_axim2_clk_src[] = { F(342857143, P_GPLL4, 3.5, 0, 0), { } @@ -4063,16 +3755,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, - [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, - [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, @@ -4085,27 +3769,18 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, - [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, - [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, @@ -4129,7 +3804,6 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, - [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, From patchwork Fri Nov 10 09:19:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 742909 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAAB01170A; Fri, 10 Nov 2023 09:20:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="M/c0l8rY" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED64B2BE20; Fri, 10 Nov 2023 01:20:43 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AA8dgEb013228; Fri, 10 Nov 2023 09:20:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=p6pAPvM4zriW4ahI/z+/NN7MKgZTz9a9Js+G28M3g1U=; b=M/c0l8rY/n4AJDRPWqy23TUfAaRQzXls5RFEHVq5sdKy3hhb0pFw4gxbqUQ5PL8vbbdN sl1x4mf+yGI7ETeK1LfONIgsprl/IjotGTU0YzrNsUTwMKk6zqRNkVl0nYWSPxzw30Yi c1c/pgH7ahGQ8a5dp3ikEtb8QDeBKWQmgY7Es6EEd8YTtMqujcXXLr3kGgcqUq0tTkKp qOtMTD72b6SpU2CkRRcIks7K3f1Zt4cy1I24mEKTfAnCTfDZXiA4ykBlctC2XILPdvde 7vIDq3WaGKXMoPdEyh7rnSPoqMWXSwG6QiIf2ZFZR/zMjz1jjv6wczQC/ApclkYCUWZY wQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u99e910fh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:40 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AA9Kd5C024337 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:39 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 10 Nov 2023 01:20:31 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v6 05/11] dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros Date: Fri, 10 Nov 2023 14:49:33 +0530 Message-ID: <20231110091939.3025413-6-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> References: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: I6LfiAmaFdM6UWnUfMJ2BBZMNqFpTOmN X-Proofpoint-ORIG-GUID: I6LfiAmaFdM6UWnUfMJ2BBZMNqFpTOmN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-10_05,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 mlxlogscore=945 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311100075 In multipd model Q6 firmware takes care of bringup clocks, so remove them. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in v6: - No changes Changes in v5: - No changes Changes in v4: - Pick up R-b tag Changes in v3: - Rebased on linux-next include/dt-bindings/clock/qcom,ipq9574-gcc.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..9217b90f6847 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -132,16 +132,8 @@ #define GCC_NSSNOC_SNOC_1_CLK 123 #define GCC_QDSS_ETR_USB_CLK 124 #define WCSS_AHB_CLK_SRC 125 -#define GCC_Q6_AHB_CLK 126 -#define GCC_Q6_AHB_S_CLK 127 -#define GCC_WCSS_ECAHB_CLK 128 -#define GCC_WCSS_ACMT_CLK 129 -#define GCC_SYS_NOC_WCSS_AHB_CLK 130 #define WCSS_AXI_M_CLK_SRC 131 -#define GCC_ANOC_WCSS_AXI_M_CLK 132 #define QDSS_AT_CLK_SRC 133 -#define GCC_Q6SS_ATBM_CLK 134 -#define GCC_WCSS_DBG_IFC_ATB_CLK 135 #define GCC_NSSNOC_ATB_CLK 136 #define GCC_QDSS_AT_CLK 137 #define GCC_SYS_NOC_AT_CLK 138 @@ -154,27 +146,18 @@ #define QDSS_TRACECLKIN_CLK_SRC 145 #define GCC_QDSS_TRACECLKIN_CLK 146 #define QDSS_TSCTR_CLK_SRC 147 -#define GCC_Q6_TSCTR_1TO2_CLK 148 -#define GCC_WCSS_DBG_IFC_NTS_CLK 149 #define GCC_QDSS_TSCTR_DIV2_CLK 150 #define GCC_QDSS_TS_CLK 151 #define GCC_QDSS_TSCTR_DIV4_CLK 152 #define GCC_NSS_TS_CLK 153 #define GCC_QDSS_TSCTR_DIV8_CLK 154 #define GCC_QDSS_TSCTR_DIV16_CLK 155 -#define GCC_Q6SS_PCLKDBG_CLK 156 -#define GCC_Q6SS_TRIG_CLK 157 -#define GCC_WCSS_DBG_IFC_APB_CLK 158 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 #define GCC_QDSS_DAP_CLK 160 #define GCC_QDSS_APB2JTAG_CLK 161 #define GCC_QDSS_TSCTR_DIV3_CLK 162 #define QPIC_IO_MACRO_CLK_SRC 163 #define GCC_QPIC_IO_MACRO_CLK 164 #define Q6_AXI_CLK_SRC 165 -#define GCC_Q6_AXIM_CLK 166 -#define GCC_WCSS_Q6_TBU_CLK 167 -#define GCC_MEM_NOC_Q6_AXI_CLK 168 #define Q6_AXIM2_CLK_SRC 169 #define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 #define GCC_NSSNOC_MEMNOC_CLK 171 @@ -199,7 +182,6 @@ #define GCC_UNIPHY2_SYS_CLK 190 #define GCC_CMN_12GPLL_SYS_CLK 191 #define GCC_NSSNOC_XO_DCD_CLK 192 -#define GCC_Q6SS_BOOT_CLK 193 #define UNIPHY_SYS_CLK_SRC 194 #define NSS_TS_CLK_SRC 195 #define GCC_ANOC_PCIE0_1LANE_M_CLK 196 From patchwork Fri Nov 10 09:19:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 742908 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CBCD111A0; Fri, 10 Nov 2023 09:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="E8n7XMSL" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34BED2BE1C; Fri, 10 Nov 2023 01:20:58 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AA7gHaH005839; Fri, 10 Nov 2023 09:20:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=LEKaFKmg7Zmof/1cUm2OdkZS+CnpveGMBmIrGWIwXkk=; b=E8n7XMSLRAiKoh+YQW4L1zOgAPX4YYRqXpLaI3XYepGa7MoNFcbVvXc+gbGxTIfVMxR/ 8FVxh2C7Df3CXTdgp6gD56QRQerohwUvAq3UQEcx+ohMQSUsWayqQxbEeRdAlvpLh63J WAeb1MV1TTRD6GjD3rxylTwQA+217Xb/qRl6hJbJi1CXrw3FLdJ1kL9C+EG+RBCzplAH A1nFmVUBEcKLdX5cHVkDai+2JzXdiC4spjN7A4QdpCzkhn4BW4nO+QjyWDY5nN0MhFwM Ny7q09HUjEAFb6pzG98TmVWkWTWakIF/6avxwv+/qao857vs4Tp7DPKszR9/2v3oOc5H 6w== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u9g4n09a0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:54 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AA9KrbQ024854 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:20:53 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 10 Nov 2023 01:20:45 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v6 07/11] firmware: qcom_scm: ipq5332: add msa lock/unlock support Date: Fri, 10 Nov 2023 14:49:35 +0530 Message-ID: <20231110091939.3025413-8-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> References: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _5FvaVEgDcTu7AQEn8FU9wa2da2cyHe_ X-Proofpoint-GUID: _5FvaVEgDcTu7AQEn8FU9wa2da2cyHe_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-10_05,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311100075 IPQ5332 user pd remoteproc firmwares need to be locked with MSA(modem secure access) features. This patch add support to lock/unlock MSA features. Signed-off-by: Manikanta Mylavarapu --- Changes in v6: - Removed extern keyword from msa lock/unlock function prototype. Changes in v5: - Moved to EXPORT_SYMBOL_GPL() because scm driver moved to using EXPORT_SYMBOL_GPL() now. Changes in v4: - Rebased on linux-next drivers/firmware/qcom/qcom_scm.c | 78 ++++++++++++++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 2 + include/linux/firmware/qcom/qcom_scm.h | 2 + 3 files changed, 82 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 865f07c020a7..965164e3506b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -754,6 +754,84 @@ bool qcom_scm_pas_supported(u32 peripheral) } EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); +/** + * qcom_scm_msa_lock() - Lock given peripheral firmware region as MSA + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qcom_scm_msa_lock(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_MSA_LOCK, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_MSA_LOCK)) + return 0; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL_GPL(qcom_scm_msa_lock); + +/** + * qcom_scm_msa_unlock() - Unlock given peripheral MSA firmware region + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qcom_scm_msa_unlock(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_MSA_UNLOCK, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_MSA_UNLOCK)) + return 0; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL_GPL(qcom_scm_msa_unlock); + static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { struct qcom_scm_desc desc = { diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 4342d795940b..3b8fd08e8033 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -99,6 +99,8 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a +#define QCOM_SCM_MSA_LOCK 0x24 +#define QCOM_SCM_MSA_UNLOCK 0x25 #define QCOM_SCM_SVC_IO 0x05 #define QCOM_SCM_IO_READ 0x01 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index ccaf28846054..5526369d9568 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -79,6 +79,8 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size); int qcom_scm_pas_auth_and_reset(u32 peripheral); int qcom_scm_pas_shutdown(u32 peripheral); bool qcom_scm_pas_supported(u32 peripheral); +int qcom_scm_msa_lock(u32 peripheral); +int qcom_scm_msa_unlock(u32 peripheral); int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); From patchwork Fri Nov 10 09:19:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 742907 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F2CF11726; Fri, 10 Nov 2023 09:21:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="I8GPuFeS" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 773B72BE2A; Fri, 10 Nov 2023 01:21:26 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AA8g8e1021754; Fri, 10 Nov 2023 09:21:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=KcmNwekZBih2/kLilI9rfgVt+CDdVES2r8XqVetPnsc=; b=I8GPuFeSLoI0DirGfOjV/Km2VcOPQU4l+SGxTib3eBAMzbVwi5S8ugqrG331oSGHbHSw 5XAv9tZjSWnwAAKM1NFf7n2RTYY684BksDU9skWfyspJ0yPC/NJS4j7Y0Xl2P2C3Qo5Z JIaXASTMtWZh4fK03Gw0BXBveN/RIW24ck/fQQte7ohogxq1Q4jMU2rJMitjOTPa1Pkj adpP0QXV0Abeln5y34I5VmmXqt9RSV24U0BBEIvpW2G11wC0O/L0Q7F1mm6wA9G6FD4E pRf1YvmxfCiYEVJQsYEr+PhbAlANeMRk4e7FYoSX4+ZDEsSLASPrjFUi5Vko4msD7eaH cg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u99j80yh9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:21:22 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AA9LLFA025727 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Nov 2023 09:21:21 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 10 Nov 2023 01:21:14 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v6 11/11] arm64: dts: qcom: ipq9574: Add nodes to bring up multipd Date: Fri, 10 Nov 2023 14:49:39 +0530 Message-ID: <20231110091939.3025413-12-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> References: <20231110091939.3025413-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ckHZrrbs8Ly7wHI0Gp7IYQ3HdAqaeJwR X-Proofpoint-GUID: ckHZrrbs8Ly7wHI0Gp7IYQ3HdAqaeJwR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-10_05,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=594 clxscore=1015 mlxscore=0 malwarescore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311100075 Enable nodes required for multipd remoteproc bring up. Signed-off-by: Manikanta Mylavarapu --- Changes in v6: - Rebased on linux-next Changes in v5: - Rebased on linux-next Changes in v4: - Rebased on linux-next Changes in v3: - Fixed all comments and rebased on linux-next. - Removed WCSS userpd nodes from dtsi file, because it vary based on no of radio's connected. Changes in v2: - Corrected syntax like alignmnet and kept nodes in sorted order. - Added 'firmware-name' property. arch/arm64/boot/dts/qcom/ipq9574.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5f83ee42a719..96cc5bb2e0be 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -212,6 +212,11 @@ smem@4aa00000 { hwlocks = <&tcsr_mutex 3>; no-map; }; + + q6_region: wcnss@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x2b00000>; + no-map; + }; }; soc: soc@0 { @@ -741,6 +746,36 @@ frame@b128000 { status = "disabled"; }; }; + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq9574-q6-mpd"; + reg = <0x0cd00000 0x4040>; + firmware-name = "ath11k/IPQ9574/hw1.0/q6_fw.mdt", + "ath11k/IPQ9574/hw1.0/m3_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; }; thermal-zones { @@ -998,4 +1033,28 @@ timer { , ; }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; };