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[209.51.188.17]) by mx.google.com with ESMTPS id d3-20020a05620a204300b0077767d37ffbsi6966772qka.782.2023.11.07.04.26.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Nov 2023 04:26:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=crFDbXpt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0L8s-0005Lu-Jf; Tue, 07 Nov 2023 07:25:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0L8o-0005Go-J9 for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:10 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0L8Z-0004f9-PP for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:09 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4084095722aso42504355e9.1 for ; Tue, 07 Nov 2023 04:24:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699359891; x=1699964691; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xQIx7Qo+vYb4U5X/jCWdqru6+jgyWVX+HEchvZf2EPw=; b=crFDbXptn9AogKys/42RfC4yUmdED8y5lYwhf7soQRCfspxd4XV0fpC1T3GJ+M93HE 4H0x1XG0a3yA3t8QuIUbcHbnrWdBJ5pY6ZG1giBT7WbgTrwh3/K1aIQ9YBb0BBaGMCAm cdXUPZk7Wl+UDPeuzuPmIFK7Gg26aL0B3defVOxiyH/IWR0hM60FuQM51zZjJoNuWjrt Defu1cs2mpGXM6QHz+Tpr3EgbBLiFHRqJ2GFvMRGtxGtRoUTqelV+09hRtCrOs+OoXa9 FHocc/FNWFfwUJ1+DTDtKKbYLOm/rv3bsOUscDbNqjjW3wc6zspHVRIYpD8cTjde6Gbn 1kFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699359891; x=1699964691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xQIx7Qo+vYb4U5X/jCWdqru6+jgyWVX+HEchvZf2EPw=; b=himhajB2fVS3URWD07FcA8I9vtGbn+gnM5pW6Y7iXtnQXks7zBnuqC2VCsjmgd/fTJ 63MeOvCcQ664xgu8icnNab42halDCwKgf+YOgvYePRyHQ5flrWfhJPb9HYxcW0pdTlV+ oQrMU4oeUBX4VaCEnrWvHtzEsnIMYUYjU/Ezust+ncRKjaZveL/1fnOvO0R4WDReWRqH pEADyBof88srqXieL4G9pBg6Q+ZAWsj7XG9aVmbffEMboF8fsx3sryxTWZ34iCPVqYyr XGO2nFSGSva4pP1Fj1v+5FnLEEL0iY/6zu6DrGMUJc6ELZwAdUgEpRNnK2wWe5P/W6Gl tlcw== X-Gm-Message-State: AOJu0YwG3StxmqbvLyMqCJMQd5vhXKRCcSqJF7UAAJQxDK3PbBa3ySFu 29QmoBcittxP1iH2UEIdh7FjvwfPNm09J6Mhm9A= X-Received: by 2002:a05:600c:2b0d:b0:409:19a0:d26f with SMTP id y13-20020a05600c2b0d00b0040919a0d26fmr2323873wme.23.1699359890958; Tue, 07 Nov 2023 04:24:50 -0800 (PST) Received: from m1x-phil.lan ([176.187.216.69]) by smtp.gmail.com with ESMTPSA id fc13-20020a05600c524d00b004068de50c64sm15791988wmb.46.2023.11.07.04.24.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Nov 2023 04:24:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Richard Henderson , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= , Nicholas Piggin , Daniel Henrique Barboza Subject: [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h' Date: Tue, 7 Nov 2023 13:24:26 +0100 Message-ID: <20231107122442.58674-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PM instructions are only used by TCG helpers. No need to expose to other hardware. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20231013125630.95116-3-philmd@linaro.org> --- target/ppc/cpu-qom.h | 10 ---------- target/ppc/internal.h | 9 +++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 41df51269b..f681bfb4a6 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -114,16 +114,6 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER10, }; -/*****************************************************************************/ -/* PM instructions */ -typedef enum { - PPC_PM_DOZE, - PPC_PM_NAP, - PPC_PM_SLEEP, - PPC_PM_RVWINKLE, - PPC_PM_STOP, -} powerpc_pm_insn_t; - /*****************************************************************************/ /* Input pins model */ typedef enum powerpc_input_t powerpc_input_t; diff --git a/target/ppc/internal.h b/target/ppc/internal.h index c881c67a8b..5b20ecbd33 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -20,6 +20,15 @@ #include "hw/registerfields.h" +/* PM instructions */ +typedef enum { + PPC_PM_DOZE, + PPC_PM_NAP, + PPC_PM_SLEEP, + PPC_PM_RVWINKLE, + PPC_PM_STOP, +} powerpc_pm_insn_t; + #define FUNC_MASK(name, ret_type, size, max_val) \ static inline ret_type name(uint##size##_t start, \ uint##size##_t end) \ From patchwork Tue Nov 7 12:24:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741866 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587783wrr; Tue, 7 Nov 2023 04:27:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IFkjZnGlNv7OloveazDPZDV8rMAMyW5vLyjPsZC/GNkkpNuPUx9BOiRDBZmhoTIp7cvsLNQ X-Received: by 2002:a05:622a:10f:b0:417:f85b:5a5a with SMTP id u15-20020a05622a010f00b00417f85b5a5amr35480255qtw.5.1699360067641; Tue, 07 Nov 2023 04:27:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360067; cv=none; d=google.com; s=arc-20160816; b=mYnFnO/x+kklQG8cfFIJSm5d6UzamAuXu4az/F3AYVlLdGf3MFPaqt5kf2U/lqYNXZ X1TZrU4HKSVMBHPRP1WNHR7gDP5aHfdnM9YrfWWAD9vydEdxyrBYdsABLUHFjzECXz/b eNet9aITJkeyYb83clS+JfVblTmBk1AMwJbtDws8liNwEaE3RI7BMrISsgqEysI3B1h6 OqqOhlGIE4SUZMpizQOJ6iV+Oz1jlLSaS0ziL2wtLDzki4NS5K3ZSSfxik49vrOslxgb C9cCXlbQlMQfJJwclqYRvxGYgEhllB10JPEWA4FIQM5QGr5RJITrhaCFgjPOgRTamaY+ xRaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vwIwGURbiF//KmePmfvAI1hLU80w6lpRnRx+VzJZixg=; fh=zqCJK/GNKinD327RpwX+nzDujFsGQ+TAosBHb+QbdKo=; b=sf/5iK6Ay2ZlgdQodsRcrDrBE10L0wwm6n2wHJRW3SdKYgwUUdc0DzF2+2qvHErKYa OjcPZmAX4J7QEur8bVX0MN/6Uz0CpjnrfECt179sIQtTGLNpnZ6F3PQpe6+UiEbgoNHg w8MaIgPZ4ChNHSXSNywWTKwizhEqTt+iQN7e9q9cn9n+nGnT9kiLl2anBWGpS5gMUqBG 1wWNlsvW5Re8/bRR19TZIeWammnY5VpXMxYRAPbkIlkdhlACtABtuzs2RQmKOnQX6QS/ iK18YG6BZ8y9ztaO/HIj9d1lvO2+wge6zb7r+txfmir9kzQzwyjwlrdQvJ01W0yB8KGm zpuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IeYl6qcm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20231013125630.95116-4-philmd@linaro.org> --- target/ppc/cpu-qom.h | 2 -- target/ppc/cpu.h | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index f681bfb4a6..0b8dfa5fee 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -36,8 +36,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -ObjectClass *ppc_cpu_class_by_name(const char *name); - typedef struct CPUArchState CPUPPCState; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_dcr_t ppc_dcr_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 02619e5d54..f3ddfd7a26 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1342,6 +1342,7 @@ struct ArchCPU { }; +ObjectClass *ppc_cpu_class_by_name(const char *name); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc); From patchwork Tue Nov 7 12:24:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741868 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587861wrr; Tue, 7 Nov 2023 04:27:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/jPo1WDcl5Dya1bg3Dv4otCJ1O4XddZzZU4MgA/wuwpfOKU7iBGqksRrMPAtgWUh0uuy/ X-Received: by 2002:a05:622a:15c6:b0:41e:236d:9474 with SMTP id d6-20020a05622a15c600b0041e236d9474mr38081877qty.64.1699360077318; Tue, 07 Nov 2023 04:27:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360077; cv=none; d=google.com; s=arc-20160816; b=dKwDNFunWIhDHBixzXRkhuQ56wZk3l9JybC65bIssIYBoEqNKNOdMw12HdwRdXhnWu i/o6rYlzlnXTfVtKvCZrEuLhX/wccdDq9kYjcPB8CLaVEQqsmCFWp+iD2J6cLBYfvVDD BqcMCLJXSPsGKIB+ylSR6tFCkj26ribGVJxgMrWmt/yzPdjL7gkQbSvVk/zxJy32EepK PBQalv+O0/HR/P++IA07zjeOiAeEp8FMUW5qseQnX5xSUNloimMAqlFr7m1ldFzadXsl gVPvaVI4i6PvuJoDWrHYZD9xkLXgKI2Go9jFQ+p6l4LeNBq7/cI6VnKYjts67kQVDF3N v4sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IukOQrcvFKTQKQHU+Gn7+JZ4VvtRt6lfWofdjUUbwSE=; fh=YV4gNTMS90pCJFtdEnyCZ1ABVtsCB59kwLHicky2n2c=; b=ZVPWjJ6RrvEFxfpPg2ZWRJCeWApTr/n+SD6dpkky3sZrPs6zkE4W1IDeE3niCgcSpR cNrQdf7LENJeUy0iJBzTjSb96UTPb0Jl89pFAU9K8R7ewr9vYB9Q9aoQ1tpaIpLkuYkf Kp8m2tnx+iic50XYyL0jOt7xCrvjxfLnCbVqn4ZFZ49lu3gHGZnjIiUkv5SHtYucs6jP LZ5raUE/yeznYmosj56KR2bDAJ+8AxIpJMNBhpdDlv6OLZ72pQORsb+6bTrM2vlh5dij agqS/Lzx1fAIVOe5sRrIJrp+FdudnJ+U3RKyV4ghVRv8cE9tBFHj8xZDGSMNLdBgBA8U ThxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uoGCNbkP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t12-20020ac8588c000000b0041e3143e812si6839092qta.263.2023.11.07.04.27.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Nov 2023 04:27:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uoGCNbkP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0L96-0005ki-CT; Tue, 07 Nov 2023 07:25:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0L95-0005ex-1Z for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:27 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0L8j-0004nM-KK for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:26 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-40906fc54fdso43003605e9.0 for ; Tue, 07 Nov 2023 04:25:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699359903; x=1699964703; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IukOQrcvFKTQKQHU+Gn7+JZ4VvtRt6lfWofdjUUbwSE=; b=uoGCNbkPbk5ggg2wqkztH6sYNd/Ke1nPYSEC+ls9IyKuOIkdpsnze50BZTVi8UhmB5 AvRtYcvC3O6W+G4pYuW8CLjmtSU4GitY42Rg+dN3ACV/9IlwR2eGP88d3078LsHJ3hF2 U//PYLOGSYhAKVYzWyHP4gQT37QmRIKLBUFngFXH3uowx3fO6Hvs630dOGEbITZXtxW8 HbLDLekwFoJrBSH9gA4PCkvB4dQYgFol2bY8SwrA6B+H916AgHE2x7i1ioodgUkq4uks UMbIqNAYi2lpGu3NxcAKvUhSbA17CU2vnVd6epwOiE8dcngwPmf0Y4WcoXaMsCW9ZKQx PQUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699359903; x=1699964703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IukOQrcvFKTQKQHU+Gn7+JZ4VvtRt6lfWofdjUUbwSE=; b=v24zbLbxF43RhaXjSi86pRZit8RHaddVqy9RFIzSEDrvC3JfQgO+KQzb8MZL4Q22+t 3lJBHXC7AQzbD/VTdfGMfig4oqe7Pe9yldwNUNenzX4okBHvigjA6hvd7/37DSfQkCd2 49J0ldjzzUf9WZkAThjwfTx2fQLmeqYy4JbShS3YfWP9Me2trTdDmeqngrBGCTVmmf6q YtPjw9ufgoJBAE38289WeGXyLJjNtUnfFXcbD6DZc+mkKDZbscdVFOcwBfmyceqQ+bfz zq7+WtrsOYQ8sqzaBrr+mtVlX+rzGno3zhWd1xMXG9TX88ZWxmKawOeuF0EhFPDJq2ND geSg== X-Gm-Message-State: AOJu0YwVG5HmpbC6vowPoITubZOuKZnB5nBVRW90USUI5/Dax/98lG0G wg0QwVCGP19fR5Ip8jQOzjjlN/JHmSrZo3pcawU= X-Received: by 2002:a05:600c:35d1:b0:406:52e4:cd23 with SMTP id r17-20020a05600c35d100b0040652e4cd23mr2108351wmq.0.1699359902878; Tue, 07 Nov 2023 04:25:02 -0800 (PST) Received: from m1x-phil.lan ([176.187.216.69]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15681877wmr.14.2023.11.07.04.25.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Nov 2023 04:25:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Richard Henderson , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 38/75] target/ppc: Move PowerPCCPUClass definition to 'cpu.h' Date: Tue, 7 Nov 2023 13:24:28 +0100 Message-ID: <20231107122442.58674-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The OBJECT_DECLARE_CPU_TYPE() macro forward-declares the PowerPCCPUClass type. This forward declaration is sufficient for code in hw/ to use the QOM definitions. No need to expose the structure definition. Keep it local to target/ppc/ by moving it to target/ppc/cpu.h. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013125630.95116-5-philmd@linaro.org> --- include/hw/ppc/ppc.h | 2 +- target/ppc/cpu-qom.h | 56 -------------------------------------------- target/ppc/cpu.h | 51 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 57 deletions(-) diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 17a8dfc107..d5d119ea7f 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -1,7 +1,7 @@ #ifndef HW_PPC_H #define HW_PPC_H -#include "target/ppc/cpu-qom.h" +#include "target/ppc/cpu.h" void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level); PowerPCCPU *ppc_get_vcpu_by_pir(int pir); diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 0b8dfa5fee..65a640470f 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_PPC_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #ifdef TARGET_PPC64 #define TYPE_POWERPC_CPU "powerpc64-cpu" @@ -36,10 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -typedef struct CPUArchState CPUPPCState; -typedef struct ppc_tb_t ppc_tb_t; -typedef struct ppc_dcr_t ppc_dcr_t; - /*****************************************************************************/ /* MMU model */ typedef enum powerpc_mmu_t powerpc_mmu_t; @@ -133,57 +128,6 @@ enum powerpc_input_t { PPC_FLAGS_INPUT_RCPU, }; -typedef struct PPCHash64Options PPCHash64Options; - -/** - * PowerPCCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A PowerPC CPU model. - */ -struct PowerPCCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - DeviceUnrealize parent_unrealize; - ResettablePhases parent_phases; - void (*parent_parse_features)(const char *type, char *str, Error **errp); - - uint32_t pvr; - /* - * If @best is false, match if pcc is in the family of pvr - * Else match only if pcc is the best match for pvr in this family. - */ - bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best); - uint64_t pcr_mask; /* Available bits in PCR register */ - uint64_t pcr_supported; /* Bits for supported PowerISA versions */ - uint32_t svr; - uint64_t insns_flags; - uint64_t insns_flags2; - uint64_t msr_mask; - uint64_t lpcr_mask; /* Available bits in the LPCR */ - uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ - powerpc_mmu_t mmu_model; - powerpc_excp_t excp_model; - powerpc_input_t bus_model; - uint32_t flags; - int bfd_mach; - uint32_t l1_dcache_size, l1_icache_size; -#ifndef CONFIG_USER_ONLY - unsigned int gdb_num_sprs; - const char *gdb_spr_xml; -#endif - const PPCHash64Options *hash64_opts; - struct ppc_radix_page_info *radix_page_info; - uint32_t lrg_decr_bits; - int n_host_threads; - void (*init_proc)(CPUPPCState *env); - int (*check_pow)(CPUPPCState *env); -}; - #ifndef CONFIG_USER_ONLY typedef struct PPCTimebase { uint64_t guest_timebase; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f3ddfd7a26..55330d9319 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -200,9 +200,14 @@ typedef struct opc_handler_t opc_handler_t; /*****************************************************************************/ /* Types used to describe some PowerPC registers etc. */ typedef struct DisasContext DisasContext; +typedef struct ppc_dcr_t ppc_dcr_t; typedef struct ppc_spr_t ppc_spr_t; +typedef struct ppc_tb_t ppc_tb_t; typedef union ppc_tlb_t ppc_tlb_t; typedef struct ppc_hash_pte64 ppc_hash_pte64_t; +typedef struct PPCHash64Options PPCHash64Options; + +typedef struct CPUArchState CPUPPCState; /* SPR access micro-ops generations callbacks */ struct ppc_spr_t { @@ -1341,6 +1346,52 @@ struct ArchCPU { int32_t mig_slb_nr; }; +/** + * PowerPCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A PowerPC CPU model. + */ +struct PowerPCCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; + ResettablePhases parent_phases; + void (*parent_parse_features)(const char *type, char *str, Error **errp); + + uint32_t pvr; + /* + * If @best is false, match if pcc is in the family of pvr + * Else match only if pcc is the best match for pvr in this family. + */ + bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best); + uint64_t pcr_mask; /* Available bits in PCR register */ + uint64_t pcr_supported; /* Bits for supported PowerISA versions */ + uint32_t svr; + uint64_t insns_flags; + uint64_t insns_flags2; + uint64_t msr_mask; + uint64_t lpcr_mask; /* Available bits in the LPCR */ + uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ + powerpc_mmu_t mmu_model; + powerpc_excp_t excp_model; + powerpc_input_t bus_model; + uint32_t flags; + int bfd_mach; + uint32_t l1_dcache_size, l1_icache_size; +#ifndef CONFIG_USER_ONLY + unsigned int gdb_num_sprs; + const char *gdb_spr_xml; +#endif + const PPCHash64Options *hash64_opts; + struct ppc_radix_page_info *radix_page_info; + uint32_t lrg_decr_bits; + int n_host_threads; + void (*init_proc)(CPUPPCState *env); + int (*check_pow)(CPUPPCState *env); +}; ObjectClass *ppc_cpu_class_by_name(const char *name); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); From patchwork Tue Nov 7 12:24:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741873 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1588155wrr; Tue, 7 Nov 2023 04:28:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IHU1vLIADq8Fsev+N5DDqRh/Hs45QU9FetprBFVqjAIRxRC57xZKFFTihKO9O4LnbAeENqK X-Received: by 2002:ad4:5f89:0:b0:670:fa29:eb51 with SMTP id jp9-20020ad45f89000000b00670fa29eb51mr35086442qvb.12.1699360123703; Tue, 07 Nov 2023 04:28:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360123; cv=none; d=google.com; s=arc-20160816; b=MqyCUAZ3FkUv2mT/a/F43OeoCFMDiBAbw+3u4zXfk1BORmZoLQRIsR1XzMDpyDLmvC nVaZdT3SPfZPsSpHTB628zpTwXAW6TUoN/qnSrGWfKprTTDWVu7YvL48lwPk7+mI7Nss en/i7bedvxFlhk601lHMf54VESPCrF323FibSTmKBNxxyHRL0aDm+5EBNho5BM4sdC3d X0XzZDK1dkzRhGd5rvQ90Y7ymX4zRn6v9u62Qt4dnTqIOZxKux+w4n5YNl6eADgqfLLf SV9OGNcyluazFDHRW08yXpVY5Id1Jib7k86aUfKkiE1WSe3qzE1HXuCnOQEgKWu2XeN7 33gg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id c6-20020a05621401c600b0067540fd3ebasi6615270qvt.269.2023.11.07.04.28.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Nov 2023 04:28:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uvFaXAlb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0L98-0005n1-79; Tue, 07 Nov 2023 07:25:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0L95-0005ho-HJ for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:27 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0L8o-0004so-IQ for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:27 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4084b0223ccso40723675e9.2 for ; Tue, 07 Nov 2023 04:25:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699359909; x=1699964709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UxnI5l2WrvXzGWFNPDGJXP6PFry6juDuplDEP4dg9mo=; b=uvFaXAlbTD379AqDpzf2RuvSSg/B3IUDqFXxKNUMDaHwUKROqW5G6RBHIJF8Y6pY6u RwsXoJflvDktMUYpGZX1aocKFVVG8f9gsxt8covcgQ6XwzP019l2482uQ2Giwbm4d26Q ej4joL7l23BIcufuSkxaHM6RES0l1pBVr8vxK9jrcsuQzWvodFKip4EsmexvOppsuZZw +PFoSiXZV3pJE8DahoR+V/QBvdDnkNR0T3s/RSuoz8E+n7flkzUuYmNIchxQWCHTqks5 3TNdTDrh4H0kTuphjqY+qkfenlVbU2ZpSp3G97Ts8IIH3qvlc8iZAtEZ0vjOZ3MNMIpJ tSOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699359909; x=1699964709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UxnI5l2WrvXzGWFNPDGJXP6PFry6juDuplDEP4dg9mo=; b=WKntkLsAuhFWC+iGCkDjazf1Np6VzML0la29ib2jMFPZUVcLU4XUBT9xecliKnEy33 yaRuKWbi+SYBRL+EzngcerLdFXpAfcxV8fabq+sJTCvf8eeZexmYesHrKY128w5j8QQw wZTMjQgSdrvAp8iLl2EHvN2dF1mBzomQ4NY80XOI6DROP4QMTpWMG3ScjBZ2UGyRTxnA z7kr08WusZ4+mfuDhNSQUHdZwVs3njxiXSMetA5gg6JpNT6epeKAHyLMB8usYlELSrWM OwPICu8oULoddYiAP+binWxXj8xOkk/KHTdJ6m6Z7pHXHxbq/XG3oU7K8O8xNsGTx5e6 VzVg== X-Gm-Message-State: AOJu0YzFJARKuFnrDAj9vheiuQSMTjquIFZOa11KMAgHozOixxaNtjkY hsVrmV3+wlgebm3TQ3TwFJn/KNzYnshXNs59RLk= X-Received: by 2002:adf:f1d0:0:b0:32d:84e8:eef2 with SMTP id z16-20020adff1d0000000b0032d84e8eef2mr22297913wro.33.1699359908952; Tue, 07 Nov 2023 04:25:08 -0800 (PST) Received: from m1x-phil.lan ([176.187.216.69]) by smtp.gmail.com with ESMTPSA id t11-20020a5d49cb000000b003248a490e3asm2215974wrs.39.2023.11.07.04.25.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Nov 2023 04:25:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Richard Henderson , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= , Nicholas Piggin , Daniel Henrique Barboza Subject: [PULL 39/75] target/ppc: Move powerpc_excp_t definition to 'cpu.h' Date: Tue, 7 Nov 2023 13:24:29 +0100 Message-ID: <20231107122442.58674-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The powerpc_excp_t definition is only used by target/ppc/, no need to expose it. Restrict it by moving it to "target/ppc/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20231013125630.95116-6-philmd@linaro.org> --- target/ppc/cpu-qom.h | 29 ----------------------------- target/ppc/cpu.h | 27 +++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 29 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 65a640470f..acc5f1a1dc 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -78,35 +78,6 @@ static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) return mmu_model & POWERPC_MMU_64; } -/*****************************************************************************/ -/* Exception model */ -typedef enum powerpc_excp_t powerpc_excp_t; -enum powerpc_excp_t { - POWERPC_EXCP_UNKNOWN = 0, - /* Standard PowerPC exception model */ - POWERPC_EXCP_STD, - /* PowerPC 40x exception model */ - POWERPC_EXCP_40x, - /* PowerPC 603/604/G2 exception model */ - POWERPC_EXCP_6xx, - /* PowerPC 7xx exception model */ - POWERPC_EXCP_7xx, - /* PowerPC 74xx exception model */ - POWERPC_EXCP_74xx, - /* BookE exception model */ - POWERPC_EXCP_BOOKE, - /* PowerPC 970 exception model */ - POWERPC_EXCP_970, - /* POWER7 exception model */ - POWERPC_EXCP_POWER7, - /* POWER8 exception model */ - POWERPC_EXCP_POWER8, - /* POWER9 exception model */ - POWERPC_EXCP_POWER9, - /* POWER10 exception model */ - POWERPC_EXCP_POWER10, -}; - /*****************************************************************************/ /* Input pins model */ typedef enum powerpc_input_t powerpc_input_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 55330d9319..94a804a605 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -192,6 +192,33 @@ enum { POWERPC_EXCP_TRAP = 0x40, }; +/* Exception model */ +typedef enum powerpc_excp_t { + POWERPC_EXCP_UNKNOWN = 0, + /* Standard PowerPC exception model */ + POWERPC_EXCP_STD, + /* PowerPC 40x exception model */ + POWERPC_EXCP_40x, + /* PowerPC 603/604/G2 exception model */ + POWERPC_EXCP_6xx, + /* PowerPC 7xx exception model */ + POWERPC_EXCP_7xx, + /* PowerPC 74xx exception model */ + POWERPC_EXCP_74xx, + /* BookE exception model */ + POWERPC_EXCP_BOOKE, + /* PowerPC 970 exception model */ + POWERPC_EXCP_970, + /* POWER7 exception model */ + POWERPC_EXCP_POWER7, + /* POWER8 exception model */ + POWERPC_EXCP_POWER8, + /* POWER9 exception model */ + POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, +} powerpc_excp_t; + #define PPC_INPUT(env) ((env)->bus_model) /*****************************************************************************/ From patchwork Tue Nov 7 12:24:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741865 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587711wrr; Tue, 7 Nov 2023 04:27:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IEtMcNPvu4o20s72oJB7ncASSs91qxQfXPnwgW/YE2hjTf4/+0+R+CZn00ukqejvm/+4eYZ X-Received: by 2002:a67:b707:0:b0:45f:4e55:9c51 with SMTP id h7-20020a67b707000000b0045f4e559c51mr4197208vsf.18.1699360056134; Tue, 07 Nov 2023 04:27:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360056; cv=none; d=google.com; s=arc-20160816; b=eWbqF0q2oM59sdgBwZE32og+lKU0Pb10VIi0KJwvIQqkPw4yKiKfFIjJhiw+ZfeSdB IvAE3NWEffV6U8OnK2vNGp4JBNsy9n3AdJLqbePK7//p8TD8IytYBB96JKhfU/2W0K1d u6OOIEXOntINsmzK3CzLw6VNHnvHPWlbU0OG/Brj2KgsYZmH/y5CV5TjQzweuISP6pdH JLfW1uHrXlPjdYp+xrWETWxNOSo3XA2k3E5IOAjaOJQH7W17y/Un0EaKcDmDScLjxD6n uX8xnDl870DTq4VIJ+4sDSqTPhLw8hIf9luic0KJL5pCcLZQgSKCkQkBznLkzTxI/0Cj kl/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zKkOBDyOAp9TL8xTunrffYZIxVubjYo+GnkmnNkOpdA=; fh=zqCJK/GNKinD327RpwX+nzDujFsGQ+TAosBHb+QbdKo=; b=yF4NFqLih4B1yQwHcIPgWaR6zPdDVq//efbLio4P9CE/LXy5SjOAwzRMxBsyZCqUGf WOkhVpoY/jTcYwSZmkgBAVXQwNTc4pASV8+YPvCp3JFzGfmoYKOUkDlmV/kOXIr86O4b TgJyochNl7W8Uo+P4mZUNY6sr8wronJ6hkmQJQ9vSdDpScRg4MDGH0GFr3LfvOpjeiYp iGnFjulvJYNuJf8nHCnb7BqpPSXpxp1nE9+ef0r3R+ah/jbBCPYyYiikD4ouY6VVXiwk ghFU5PYuAX3RKhMTZ0kK1DrAdW47R8D/EV/U2EHnfXnGWlha9o9Duadz4+O/NOqne9OC 0caw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZTIHENBM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Restrict it by moving it to "target/ppc/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20231013125630.95116-7-philmd@linaro.org> --- target/ppc/cpu-qom.h | 43 ------------------------------------------- target/ppc/cpu.h | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 43 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index acc5f1a1dc..c35374e15f 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -35,49 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -/*****************************************************************************/ -/* MMU model */ -typedef enum powerpc_mmu_t powerpc_mmu_t; -enum powerpc_mmu_t { - POWERPC_MMU_UNKNOWN = 0x00000000, - /* Standard 32 bits PowerPC MMU */ - POWERPC_MMU_32B = 0x00000001, - /* PowerPC 6xx MMU with software TLB */ - POWERPC_MMU_SOFT_6xx = 0x00000002, - /* - * PowerPC 74xx MMU with software TLB (this has been - * disabled, see git history for more information. - * keywords: tlbld tlbli TLBMISS PTEHI PTELO) - */ - POWERPC_MMU_SOFT_74xx = 0x00000003, - /* PowerPC 4xx MMU with software TLB */ - POWERPC_MMU_SOFT_4xx = 0x00000004, - /* PowerPC MMU in real mode only */ - POWERPC_MMU_REAL = 0x00000006, - /* Freescale MPC8xx MMU model */ - POWERPC_MMU_MPC8xx = 0x00000007, - /* BookE MMU model */ - POWERPC_MMU_BOOKE = 0x00000008, - /* BookE 2.06 MMU model */ - POWERPC_MMU_BOOKE206 = 0x00000009, -#define POWERPC_MMU_64 0x00010000 - /* 64 bits PowerPC MMU */ - POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, - /* Architecture 2.03 and later (has LPCR) */ - POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, - /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, - /* Architecture 2.07 variant */ - POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, - /* Architecture 3.00 variant */ - POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, -}; - -static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) -{ - return mmu_model & POWERPC_MMU_64; -} - /*****************************************************************************/ /* Input pins model */ typedef enum powerpc_input_t powerpc_input_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 94a804a605..d859c45a2e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -219,6 +219,48 @@ typedef enum powerpc_excp_t { POWERPC_EXCP_POWER10, } powerpc_excp_t; +/*****************************************************************************/ +/* MMU model */ +typedef enum powerpc_mmu_t { + POWERPC_MMU_UNKNOWN = 0x00000000, + /* Standard 32 bits PowerPC MMU */ + POWERPC_MMU_32B = 0x00000001, + /* PowerPC 6xx MMU with software TLB */ + POWERPC_MMU_SOFT_6xx = 0x00000002, + /* + * PowerPC 74xx MMU with software TLB (this has been + * disabled, see git history for more information. + * keywords: tlbld tlbli TLBMISS PTEHI PTELO) + */ + POWERPC_MMU_SOFT_74xx = 0x00000003, + /* PowerPC 4xx MMU with software TLB */ + POWERPC_MMU_SOFT_4xx = 0x00000004, + /* PowerPC MMU in real mode only */ + POWERPC_MMU_REAL = 0x00000006, + /* Freescale MPC8xx MMU model */ + POWERPC_MMU_MPC8xx = 0x00000007, + /* BookE MMU model */ + POWERPC_MMU_BOOKE = 0x00000008, + /* BookE 2.06 MMU model */ + POWERPC_MMU_BOOKE206 = 0x00000009, +#define POWERPC_MMU_64 0x00010000 + /* 64 bits PowerPC MMU */ + POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, + /* Architecture 2.03 and later (has LPCR) */ + POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, + /* Architecture 2.06 variant */ + POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, + /* Architecture 2.07 variant */ + POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, + /* Architecture 3.00 variant */ + POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, +} powerpc_mmu_t; + +static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) +{ + return mmu_model & POWERPC_MMU_64; +} + #define PPC_INPUT(env) ((env)->bus_model) /*****************************************************************************/ From patchwork Tue Nov 7 12:24:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741875 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1588315wrr; Tue, 7 Nov 2023 04:29:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVMi7B7zX6WtXxBJhoNwxoDyxCEzjZD3jym/Kkj9u+GV+GPodSX6a0lJTQyPeCBnHMAJsM X-Received: by 2002:ac8:5fc3:0:b0:418:a364:c4ea with SMTP id k3-20020ac85fc3000000b00418a364c4eamr37291184qta.30.1699360145058; Tue, 07 Nov 2023 04:29:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360145; cv=none; d=google.com; s=arc-20160816; b=nmPt3zsVC/AAPsrdHNfhMynh7EMZqoM8Jvd7DMXOUlK8vCoYlbhcEzPMxipdHuSJoy Osga5hLC3KmU9mkL/F8vnciYDl+Wv11rmihCR5kIX429oliPQBc1JBRBPsQgEZighTk5 ybeX7OMKfyo1sw93DzxV+Mxa8Xdg4VmCXidfyHDi9/QqTi7EOltXs9msuG1mGipj/RG6 QD50goGvOCDRKp3h95SM9+Fv7Ain0hCjs8WEcA6xtxO+VL9VqbFhQYjjiNRzJkxSi2dz GQ+1J9m+SJlx4A8xaZv+VI08IvbffkiMOBUGm5Ad3r/xuPzxd5rjgfaLPmprvYZUNEhb gzTA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id n8-20020a05622a040800b004134681883esi6783473qtx.601.2023.11.07.04.29.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Nov 2023 04:29:05 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hXsEyFg6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0L9x-0006jT-Kl; Tue, 07 Nov 2023 07:26:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0L9P-00067I-H9 for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:54 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0L92-0004vY-3U for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:25:43 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4083f613272so48429415e9.1 for ; Tue, 07 Nov 2023 04:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699359921; x=1699964721; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4cBhoinmiIEOsb8jCdcceaN6JxCpOf4XdeJF400+y0=; b=hXsEyFg6eqEJIcw44ySSreJrmPVDQXSDoL50JWIkZd62bWCUWTZIGNxHtVexR2D9Io JeywT/gO5swBPzaPeI/PTypY8278J376Jvx0sZexilBE/BBdfG0co35HLZu8SQVS6EEm cW9jjk0Rne6uFZZKHddK88xgMpAmYnsZWIkJMTkEpflR9SUKiHYz9MtuJWLZpsgpG1wU 9XlY9Vsq6xEjACXepCNhKdF25dnSsSbMtKDB65TPGCM4kbdJRIhVbyIL0Nlud8PW21XE 4nRueoVsCV/UabaQ0obCT7FW41aHeM8XtoFKLkrUpCXJbQ6G2GiKFXssct5MKcgQoVhJ zHBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699359921; x=1699964721; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4cBhoinmiIEOsb8jCdcceaN6JxCpOf4XdeJF400+y0=; b=D7D9rudGHZN2TyOp2v/OT86EgH1h2QDjqEVzZI8/oDGzyTQK795BTZGv5nsS/LXs+P QMNSqeiUpZKGaRy5wa4uffZYpOe/aAgyNKL4tTOGgEjKrL43z21O2V9/cTd8Kzdfaz0Z +XRl8uwoM/MxjcPo+RosxS5XSReLZ7veljZ0cBADgOn6MIn2NI0syax0lcZ1zemYbw9A 3ZqWPPGZjOyFYoBh8/s5ZIgWjUHPHfGPnIhTWIDR+ls19UF0LZJ+OlGX87Q6F3ZJvypL 4AWrcgZFVEOoDs/yfYlFZv89mJLfuebWKgPjVcBv0RsWiifWaBZQ2o8hPuLidInZoNrl PtCw== X-Gm-Message-State: AOJu0YzELNJiYynFj9tZbEquVxbPeTyNXbTLVfeoWXjnCRbx6RIDVZDM 07RWnhvqnPXoCCN3oStVB69ausELEi3Ntmc/jDg= X-Received: by 2002:a5d:588f:0:b0:32f:7e1d:f039 with SMTP id n15-20020a5d588f000000b0032f7e1df039mr23964336wrf.46.1699359921327; Tue, 07 Nov 2023 04:25:21 -0800 (PST) Received: from m1x-phil.lan ([176.187.216.69]) by smtp.gmail.com with ESMTPSA id k4-20020a5d6d44000000b0032dc1fc84f2sm2241399wri.46.2023.11.07.04.25.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Nov 2023 04:25:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Richard Henderson , =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= , Nicholas Piggin , Daniel Henrique Barboza Subject: [PULL 41/75] target/ppc: Move powerpc_input_t definition to 'cpu.h' Date: Tue, 7 Nov 2023 13:24:31 +0100 Message-ID: <20231107122442.58674-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The powerpc_input_t definition is only used by target/ppc/, no need to expose it. Restrict it by moving it to "target/ppc/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20231013125630.95116-8-philmd@linaro.org> --- target/ppc/cpu-qom.h | 21 --------------------- target/ppc/cpu.h | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index c35374e15f..0241609efe 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -35,27 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") -/*****************************************************************************/ -/* Input pins model */ -typedef enum powerpc_input_t powerpc_input_t; -enum powerpc_input_t { - PPC_FLAGS_INPUT_UNKNOWN = 0, - /* PowerPC 6xx bus */ - PPC_FLAGS_INPUT_6xx, - /* BookE bus */ - PPC_FLAGS_INPUT_BookE, - /* PowerPC 405 bus */ - PPC_FLAGS_INPUT_405, - /* PowerPC 970 bus */ - PPC_FLAGS_INPUT_970, - /* PowerPC POWER7 bus */ - PPC_FLAGS_INPUT_POWER7, - /* PowerPC POWER9 bus */ - PPC_FLAGS_INPUT_POWER9, - /* Freescale RCPU bus */ - PPC_FLAGS_INPUT_RCPU, -}; - #ifndef CONFIG_USER_ONLY typedef struct PPCTimebase { uint64_t guest_timebase; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d859c45a2e..f8101ffa29 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -261,6 +261,26 @@ static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) return mmu_model & POWERPC_MMU_64; } +/*****************************************************************************/ +/* Input pins model */ +typedef enum powerpc_input_t { + PPC_FLAGS_INPUT_UNKNOWN = 0, + /* PowerPC 6xx bus */ + PPC_FLAGS_INPUT_6xx, + /* BookE bus */ + PPC_FLAGS_INPUT_BookE, + /* PowerPC 405 bus */ + PPC_FLAGS_INPUT_405, + /* PowerPC 970 bus */ + PPC_FLAGS_INPUT_970, + /* PowerPC POWER7 bus */ + PPC_FLAGS_INPUT_POWER7, + /* PowerPC POWER9 bus */ + PPC_FLAGS_INPUT_POWER9, + /* Freescale RCPU bus */ + PPC_FLAGS_INPUT_RCPU, +} powerpc_input_t; + #define PPC_INPUT(env) ((env)->bus_model) /*****************************************************************************/ From patchwork Tue Nov 7 12:24:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741869 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587949wrr; Tue, 7 Nov 2023 04:28:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IE1jk4w1Ou/J+8LscIeAx83eyE5pyy2eHQIm1497HbecKtT/AywQ6GH4YVcPHWjIc4bcoa4 X-Received: by 2002:a05:6808:2394:b0:3a6:fb16:c782 with SMTP id bp20-20020a056808239400b003a6fb16c782mr40882193oib.30.1699360092887; Tue, 07 Nov 2023 04:28:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360092; cv=none; d=google.com; s=arc-20160816; b=iQePpvn5rm09NOJ9aa8oIUEHG+79+Mof1AwlLkH1kYJjEc3Apn4sWY/8FnCST8EHIr dKVmf5AJWOQMt7pFR69yBtyXf/bLaFDFC6MFpUleYMP8tfqXCkAk8ed4k+5rIydjmzn9 Y7ZWeIeRjK3alglF6ugQTl5TNguGme00rQZwaaBemryxHmRVjFYrRiB2ac6V0DcdJfzA z7WHoUWnLRtL/lSlQV5SYK5X2CC7AxYleoYdTXQ+2ut4U+crRaRMIdCW3n8j2Fv5BExx 00G4m/yMHhweUCqxKmoLJKXrvQsIh3jWYBvfdxD/wHdOVrhcavA+t6GjOt460rfPuwNj abjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oCI52AvMWABS83lFYxVvO8TS7PMofgyHZSbSztgXemQ=; fh=jaTVlK7hrJgn83CZVzTjLDxNv9IBdB/6li9Pe02QIGM=; b=QLd9RCz/55JmiPtJkG01COjP+7Vk1Lx02P8t/xU96QB1nRJBck/F5+CWwvLuh7dQMQ XdWdFdP8TUpiErdYJuqtStpOudO4XpIPCjujs5pwnkkZgSkQxDzDFMgc6HR9Hc6cNXIH Z2qtHPD8Zxc540fev7EnoYlzFAUjoksP9/e5aVMYOpN1CNOKGh7MPcsPft5cVU6BbvIg HwMpJTJ2PUBhLxvxKHiQR5daZb1rnOgMC+EgMeIfJatbkWR5HiHGjriSZIhGk2m0r+kS xR9BvMSeZ/sJlfMNJ0YNqzj9MI0/r1WNU0471CQNYBEoY5Qaqv7Ujx5VhoaoBqugn/S0 6b2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f02lqKVv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 07 Nov 2023 04:25:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Thomas Huth , Halil Pasic , Christian Borntraeger , Eric Farman , Richard Henderson , David Hildenbrand , Ilya Leoshkevich Subject: [PULL 42/75] hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState Date: Tue, 7 Nov 2023 13:24:32 +0100 Message-ID: <20231107122442.58674-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philmd@linaro.org; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "hw/s390x/css.h" is a header used by target-agnostic objects (such hw/s390x/virtio-ccw-gpu.c), thus can not use target-specific types, such CPUS390XState. Have css_do_sic() take S390CPU a pointer, which is target-agnostic. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20231106114500.5269-2-philmd@linaro.org> --- include/hw/s390x/css.h | 2 +- hw/s390x/css.c | 3 ++- target/s390x/kvm/kvm.c | 2 +- target/s390x/tcg/misc_helper.c | 3 ++- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h index 75e5381613..ba72ee3dd2 100644 --- a/include/hw/s390x/css.h +++ b/include/hw/s390x/css.h @@ -233,7 +233,7 @@ typedef enum { } CssIoAdapterType; void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc); -int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode); +int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode); uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc); void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, uint8_t flags, Error **errp); diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 95d1b3a3ce..bcedec2fc8 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -644,8 +644,9 @@ void css_conditional_io_interrupt(SubchDev *sch) } } -int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode) +int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode) { + CPUS390XState *env = &cpu->env; S390FLICState *fs = s390_get_flic(); S390FLICStateClass *fsc = s390_get_flic_class(fs); int r; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 0f0e784b2a..1ddad0bec1 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1358,7 +1358,7 @@ static int kvm_sic_service_call(S390CPU *cpu, struct kvm_run *run) mode = env->regs[r1] & 0xffff; isc = (env->regs[r3] >> 27) & 0x7; - r = css_do_sic(env, isc, mode); + r = css_do_sic(cpu, isc, mode); if (r) { kvm_s390_program_interrupt(cpu, -r); } diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index e85658ce22..56c7f00cf9 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -761,10 +761,11 @@ void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint64_t r3) { + S390CPU *cpu = env_archcpu(env); int r; qemu_mutex_lock_iothread(); - r = css_do_sic(env, (r3 >> 27) & 0x7, r1 & 0xffff); + r = css_do_sic(cpu, (r3 >> 27) & 0x7, r1 & 0xffff); qemu_mutex_unlock_iothread(); /* css_do_sic() may actually return a PGM_xxx value to inject */ if (r) { From patchwork Tue Nov 7 12:24:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741870 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587951wrr; Tue, 7 Nov 2023 04:28:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IFm4m+yIfWubiCo4k8hT2XcGkgX8AXJbwggzp+R1rZbUJwDvFu6iSqFU7ZEETJoaxGUQPsR X-Received: by 2002:a05:622a:15c6:b0:41e:236d:9474 with SMTP id d6-20020a05622a15c600b0041e236d9474mr38082473qty.64.1699360093897; Tue, 07 Nov 2023 04:28:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360093; cv=none; d=google.com; s=arc-20160816; b=i1x4jv3L2KMd3OnjMoS4eI2SkVd/gmfKHX2YuT9YvkgdB55DD+MGPxF8pMU3y4Msga L9+hH/SzgifVGLwZNomkDmMph11lfpLOY8ndRucHDTdwchFwfWuhYDcNQUm1qcy7Mwmo aM1eL0U80M+levcM3xRcXVQ/F0qLIKvOLXlBWgTBzck2K5bGr+E2Qadpe9pi4J7Kvb3T GNR6/9+0l39MPZrDvGdvCJ+jXFGlJYz3uVLeTnHHOOCMndQPA/+mddz+/9vSoYCpe6+B nW9OFjW000UfMj93Prwlb3RbPCoRQSXSulDrrDPQGNcE8BNOaGpDpzScr9a93C02P85y r26g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8o7ytDCjKPudtYHMOoHYjJ8HM4/zixXAYrUBK2BQdgM=; fh=jaTVlK7hrJgn83CZVzTjLDxNv9IBdB/6li9Pe02QIGM=; b=nLJERqX30XA48Y804bO1WSmPxNiNY59ix4exJFnq1mn2nJ1nUwMKuDx73TmuJWGm6D XPYAY3Z8zMmfvMzz7qxtg/0sex8NtxaDwECxHCKHqRSFKGFuLRdNSCe2lEw4/MfhELU1 XSZ0Egt2D3cYpSAaOSKzhBm7P6HXfsoNDJ3Fz49OA3OWpo1+br6TTvJKFwHKcXZ8Jl3f tzEQVJOxmbI5rVQrtzdErEcY5RFJwhcObr4MLpAEUrzmV9I5+pRtirxkdh3PGGB4bQ9z M2LZrd03C02+Cvb/fp0cqn/B8wlRHoXqe0ji4eZdj60qAf4AEXgIoNcFbTW42JoTLFuk QFBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nc0Baros; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 07 Nov 2023 04:25:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Thomas Huth , Halil Pasic , Christian Borntraeger , Eric Farman , Richard Henderson , David Hildenbrand , Ilya Leoshkevich Subject: [PULL 43/75] hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU* Date: Tue, 7 Nov 2023 13:24:33 +0100 Message-ID: <20231107122442.58674-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "hw/s390x/sclp.h" is a header used by target-agnostic objects (such hw/char/sclpconsole[-lm].c), thus can not use target-specific types, such CPUS390XState. Have sclp_service_call[_protected]() take a S390CPU pointer, which is target-agnostic. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20231106114500.5269-3-philmd@linaro.org> --- include/hw/s390x/sclp.h | 5 ++--- hw/s390x/sclp.c | 7 ++++--- target/s390x/kvm/kvm.c | 4 ++-- target/s390x/tcg/misc_helper.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/s390x/sclp.h b/include/hw/s390x/sclp.h index 9aef6d9370..e229b81a67 100644 --- a/include/hw/s390x/sclp.h +++ b/include/hw/s390x/sclp.h @@ -227,8 +227,7 @@ static inline int sccb_data_len(SCCB *sccb) void s390_sclp_init(void); void sclp_service_interrupt(uint32_t sccb); void raise_irq_cpu_hotplug(void); -int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code); -int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb, - uint32_t code); +int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code); +int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code); #endif diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c index d339cbb7e4..893e71a41b 100644 --- a/hw/s390x/sclp.c +++ b/hw/s390x/sclp.c @@ -269,9 +269,9 @@ static void sclp_execute(SCLPDevice *sclp, SCCB *sccb, uint32_t code) * service_interrupt call. */ #define SCLP_PV_DUMMY_ADDR 0x4000 -int sclp_service_call_protected(CPUS390XState *env, uint64_t sccb, - uint32_t code) +int sclp_service_call_protected(S390CPU *cpu, uint64_t sccb, uint32_t code) { + CPUS390XState *env = &cpu->env; SCLPDevice *sclp = get_sclp_device(); SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp); SCCBHeader header; @@ -296,8 +296,9 @@ out_write: return 0; } -int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code) +int sclp_service_call(S390CPU *cpu, uint64_t sccb, uint32_t code) { + CPUS390XState *env = &cpu->env; SCLPDevice *sclp = get_sclp_device(); SCLPDeviceClass *sclp_c = SCLP_GET_CLASS(sclp); SCCBHeader header; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 1ddad0bec1..33ab3551f4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1174,12 +1174,12 @@ static void kvm_sclp_service_call(S390CPU *cpu, struct kvm_run *run, break; case ICPT_PV_INSTR: g_assert(s390_is_pv()); - sclp_service_call_protected(env, sccb, code); + sclp_service_call_protected(cpu, sccb, code); /* Setting the CC is done by the Ultravisor. */ break; case ICPT_INSTRUCTION: g_assert(!s390_is_pv()); - r = sclp_service_call(env, sccb, code); + r = sclp_service_call(cpu, sccb, code); if (r < 0) { kvm_s390_program_interrupt(cpu, -r); return; diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 56c7f00cf9..6aa7907438 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -102,7 +102,7 @@ uint64_t HELPER(stck)(CPUS390XState *env) uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2) { qemu_mutex_lock_iothread(); - int r = sclp_service_call(env, r1, r2); + int r = sclp_service_call(env_archcpu(env), r1, r2); qemu_mutex_unlock_iothread(); if (r < 0) { tcg_s390_program_interrupt(env, -r, GETPC()); From patchwork Tue Nov 7 12:24:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741874 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1588221wrr; Tue, 7 Nov 2023 04:28:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IEAtn/LAtlbSJMl5TaPOBQoG/kFFGxuYuEV6eFyMuNa8BkcD6k6qAeRHmyqqKLoMn62esJ9 X-Received: by 2002:ac8:7f8c:0:b0:41e:4773:5603 with SMTP id z12-20020ac87f8c000000b0041e47735603mr38925430qtj.63.1699360130633; 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[209.51.188.17]) by mx.google.com with ESMTPS id o11-20020a05622a138b00b004128bd63451si7273636qtk.493.2023.11.07.04.28.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Nov 2023 04:28:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CvKBMHhB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0LA7-0007Fw-5X; Tue, 07 Nov 2023 07:26:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0L9d-0006Fy-ET for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:26:05 -0500 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0L9K-00057a-Ea for qemu-devel@nongnu.org; Tue, 07 Nov 2023 07:26:00 -0500 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2c50305c5c4so80522671fa.1 for ; Tue, 07 Nov 2023 04:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699359939; x=1699964739; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uzHw9gxC37cDWskQ8Q09i1BaQBpN31WzD4SH6IynXXc=; b=CvKBMHhBGXTLC6ew4HjO2vX1SrgW4YEzhsR/cEtPTzKXNJGY/F87F7afNw0jSdQvRX ibvrxSO27zkrDE0gafJSNnh5tpCD6+K2nT31rLFKbA0QpkwwvHEt/6xnwr2OuhEzZiS3 dEzudWcDJhSga5FzeRVYsaienTSX0lWUuVQufwpRnBW0e3JJJm6Wbps9hEQBmKCb89AC d7v0mwBUq6qTzXS+1L/CDJLlkxDq9cj2bKHm7/DgAMBvb0CX70thTkiZhwetqGRYYHOP CdJTSQ1nMBc2ZaHN1Q2irxZAEL8dph4kDEQvNqKLmeChXXMnb+zA3N85CwHsiijJ3qe+ 0wzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699359939; x=1699964739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uzHw9gxC37cDWskQ8Q09i1BaQBpN31WzD4SH6IynXXc=; b=KzA/t1YhtkpKywF4WhepEbLYvg+A7X/IS+QeNs/2To6dLm8D1UT6akMXN7Zbq0xnZJ M79jB4LFY3jWiJG5YJ4KRsIPoYMXMdVjQsTVaXl4YnMUHdKFbPDDAPmDhxPmpDbMSkv9 WHfhhBlq7v07fHLQ6oEUXiXf8VXuEtTVNQCpwfAvKzdk1L7nO6ZDuMh4zjLQexSpOLWr FbBhDqfK6ycLFqrCJ2MPV422PaL46EZnPmA1uI/xUXTqk/aOtmsG5ngQ8VQ347dheO6T eWvax49Ig7MuLifsquZUUnuIWcv2kUynX29L2gVIpR/lIG+rgi00gFoZ6mpfb3UEvcko eWBA== X-Gm-Message-State: AOJu0Yxi4vBHT3Vig3HLaXtNSie2Kj+Q6Q429KZbGzDG2DYA5gnuTTRz s/6PkH9c4MJICOPges3EEczlVZQzw4+Pr+QBhlQ= X-Received: by 2002:a2e:3910:0:b0:2bc:d8cb:59fe with SMTP id g16-20020a2e3910000000b002bcd8cb59femr22459267lja.8.1699359938985; Tue, 07 Nov 2023 04:25:38 -0800 (PST) Received: from m1x-phil.lan ([176.187.216.69]) by smtp.gmail.com with ESMTPSA id l26-20020a05600c1d1a00b003fef5e76f2csm12701908wms.0.2023.11.07.04.25.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Nov 2023 04:25:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Thomas Huth , Richard Henderson , David Hildenbrand , Ilya Leoshkevich Subject: [PULL 44/75] target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG Date: Tue, 7 Nov 2023 13:24:34 +0100 Message-ID: <20231107122442.58674-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_get_tb_cpu_state() is TCG specific. Another accelerator calling it would be a bug, so restrict the definition to TCG, along with "tcg_s390x.h" header inclusion. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20231106114500.5269-4-philmd@linaro.org> --- target/s390x/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 38d7197f4c..110902fa3c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -29,7 +29,6 @@ #include "cpu_models.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -#include "tcg/tcg_s390x.h" #include "qapi/qapi-types-machine-common.h" #define ELF_MACHINE_UNAME "S390X" @@ -383,6 +382,10 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) #endif } +#ifdef CONFIG_TCG + +#include "tcg/tcg_s390x.h" + static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { @@ -405,6 +408,8 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } } +#endif /* CONFIG_TCG */ + /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 From patchwork Tue Nov 7 12:24:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741864 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587698wrr; Tue, 7 Nov 2023 04:27:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IEiq1DY0eHlfZ3xQLqWAo3tR+PB++tuBJHwGXGgVsRan6/RNKJeohMDP1PpNrKoKen2NZ/a X-Received: by 2002:a05:620a:2989:b0:77a:40ae:2e71 with SMTP id r9-20020a05620a298900b0077a40ae2e71mr3021467qkp.28.1699360054012; Tue, 07 Nov 2023 04:27:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360054; cv=none; d=google.com; s=arc-20160816; b=CdMMAShFRyrRr36xJaHOCU6wG56Rh7MFYr67hNwJFfFfq1zO0+a5/EpTKzJWvB/sQm K61ezR/HpC9ow+diwTFHeH0Xw4T0hdo2YcqGC7CR8u8lLfrJAN8r9ODoCNN/b/m2NA+l 3cguCl0w5vXCpwTpw4AGtO+RtywKPmXyYzeM83tKvngsLNxV6UI3RLfaHlp0AKiZcczo M7BhtV3RRj8bd9tmWNwom+yp10rSq7oEQ4VdFkpS9Dj43cWUCUlRrM7byJcxh3qE69iI 57E+RZwdNiR4S5beguprFhgMTbO3xTALponcUJk05F4hpLNL2rRxh6wIvs6uX9YUMHj9 4WOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TWjAMfnV0kRvK1CF0UWrM+tNZeOmTMW+hMb8e74FNo4=; fh=fIxgkU9hKSKE+S/E1Sv9exqhyypVK9uhZLhwSHjMAp4=; b=QvwWS3QXfxNY1ugh0Eq+MM5p0oD+ukNAK+Q+ZZCkBKNmCJiRTlF3KkhaShy+KLi5z0 SjorvlYtBpMgyysX5hkfNiy/1skVYt7hK3nD2sLuoRJDVPTetppFHAjgfwPOU3P9FoxY 9qOqTvMI6b5jXZYqLtkAnM9zU8u6V4e4izzcLU4sG1aTfzyyFJXFek6qa/MopZ8HR1ER ncO1Gf/2wFYkkgYbidS1l6VPjzNO8hml8Pn0TctWn8MUjiBsZ7CRNzKh1uFRPutByX58 SxI2GfYxl+21ULvF1YgJduxfvesKbiKwtdsf4uSXfleJIiTm8eLtB2oGdYXQW9RzCFIT dHtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eqhVJ7Qu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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However, it currently declares CPUS390XState, which is target-specific. Move that declaration to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20231106114500.5269-5-philmd@linaro.org> --- target/s390x/cpu-qom.h | 2 -- target/s390x/cpu.h | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index fcd70daddf..ccf126b7a9 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -33,8 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU) typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; -typedef struct CPUArchState CPUS390XState; - typedef enum cpu_reset_type { S390_CPU_RESET_NORMAL, S390_CPU_RESET_INITIAL, diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 110902fa3c..942589c597 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -55,7 +55,7 @@ typedef struct PSW { uint64_t addr; } PSW; -struct CPUArchState { +typedef struct CPUArchState { uint64_t regs[16]; /* GP registers */ /* * The floating point registers are part of the vector registers. @@ -157,7 +157,7 @@ struct CPUArchState { /* currently processed sigp order */ uint8_t sigp_order; -}; +} CPUS390XState; static inline uint64_t *get_freg(CPUS390XState *cs, int nr) { From patchwork Tue Nov 7 12:24:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741871 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587948wrr; Tue, 7 Nov 2023 04:28:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IFJ/T/lBRxfFYfUmajFStnr5o7Be3StSPmQPHQ9IBeyOUHVWqluoI1p0Qf7GeAauGXRDB6d X-Received: by 2002:a9d:74c6:0:b0:6c6:4e73:f83d with SMTP id a6-20020a9d74c6000000b006c64e73f83dmr31977710otl.32.1699360092753; Tue, 07 Nov 2023 04:28:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360092; cv=none; d=google.com; s=arc-20160816; b=jQN3BfxQpwvLUq0jGSOdV4Kv87p32t07t9R66AZasb4dJ44SrKuKH/KL4tYZPf/N38 irKjbiNsOFQ77Wvpmgl1l67K0fu0EpWqfsHLvwFW3uA1oCk9hG4aHTW8+Om0XLYI6Ox6 z/2T0MJ2ZomtfmI0zdY431S+YEyecLhz1u+zu5EXKJWwbdGTLTq9xiWSNH7QTap/nGSj 4pK223W9DDjpUFsNSA+dOPJT4E+s0r1lUBQfHMdUqvxzLYPLqP0mt1BYx0xjsbKgrTqF LyOfa2cJ+oJyXUpTw3J8+axdL5GnOUDTXpJGPdsT9JrzSERQPYTFnFhxgOfvENqCuKHt VJug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X6m1nbquoS1MYyDpO5xOr1CfJvW0CpELsWVLgaH+Epo=; fh=uEuNimT+BZN/VyD5oONjykU3EmggfMWPtNc1vN/UDwo=; b=igxLJ/ZAl0GnSqdLwtVdXKzu+mfQLyx+9CDRH8q5qmPp/5RSTa/e2HEmqt5ZKwa/IR /RLsAD7xdtCaBi5CQKBsDfewehlpVDg4VW7zcWhSD8GW7GcjP5r8N8e8U5/WlX0IX5sT vBCPFO+rlc6R4hwUYbJ2UjY3VG3QQzze0aIKkALC3dbuwohyFNpL+vpsHQ3ZcOdDTKUp 4rSaHRyNT5EZj6kvgwRsSiVfoGuwvnfsn8uAUGNjt1h8qyxZJZ48zi9BPcTR15ljqfVU OEyWGufpwaEp8wQwK7pHFHnM73mIkZeUYWLAFO/0WhgYaL2Sj6oHdavyKirTrdtthAzz NKTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="DxIC/jR5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PULL 47/75] target: Move ArchCPUClass definition to 'cpu.h' Date: Tue, 7 Nov 2023 13:24:36 +0100 Message-ID: <20231107122442.58674-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each ArchCPUClass type. These forward declarations are sufficient for code in hw/ to use the QOM definitions. No need to expose these structure definitions. Keep each local to their target/ by moving them to the corresponding "cpu.h" header. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-13-philmd@linaro.org> --- target/alpha/cpu-qom.h | 16 --------------- target/alpha/cpu.h | 13 +++++++++++++ target/arm/cpu-qom.h | 27 ------------------------- target/arm/cpu.h | 25 ++++++++++++++++++++++++ target/avr/cpu-qom.h | 16 --------------- target/avr/cpu.h | 14 +++++++++++++ target/cris/cpu-qom.h | 19 ------------------ target/cris/cpu.h | 16 +++++++++++++++ target/hexagon/cpu-qom.h | 1 - target/hppa/cpu-qom.h | 16 --------------- target/hppa/cpu.h | 14 +++++++++++++ target/i386/cpu-qom.h | 39 ------------------------------------- target/i386/cpu.h | 38 ++++++++++++++++++++++++++++++++++++ target/loongarch/cpu-qom.h | 1 - target/m68k/cpu-qom.h | 16 --------------- target/m68k/cpu.h | 13 +++++++++++++ target/microblaze/cpu-qom.h | 16 --------------- target/microblaze/cpu.h | 13 +++++++++++++ target/mips/cpu-qom.h | 20 ------------------- target/mips/cpu.h | 17 ++++++++++++++++ target/nios2/cpu-qom.h | 1 - target/openrisc/cpu-qom.h | 1 - target/riscv/cpu-qom.h | 16 --------------- target/riscv/cpu.h | 16 +++++++++++++++ target/rx/cpu-qom.h | 15 -------------- target/rx/cpu.h | 14 +++++++++++++ target/s390x/cpu-qom.h | 35 --------------------------------- target/s390x/cpu.h | 30 ++++++++++++++++++++++++++++ target/s390x/cpu_models.h | 8 ++++---- target/sh4/cpu-qom.h | 23 ---------------------- target/sh4/cpu.h | 20 +++++++++++++++++++ target/sparc/cpu-qom.h | 18 ----------------- target/sparc/cpu.h | 18 +++++++++++++++-- target/tricore/cpu-qom.h | 10 ---------- target/tricore/cpu.h | 6 ++++++ target/xtensa/cpu-qom.h | 21 -------------------- target/xtensa/cpu.h | 20 +++++++++++++++++-- 37 files changed, 287 insertions(+), 335 deletions(-) diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index c4a4523993..1b32b18d34 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_ALPHA_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_ALPHA_CPU "alpha-cpu" @@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX -/** - * AlphaCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. - * - * An Alpha CPU model. - */ -struct AlphaCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - DeviceReset parent_reset; -}; - - #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 3bff56c565..d672e911dd 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -267,6 +267,19 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; +/** + * AlphaCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * An Alpha CPU model. + */ +struct AlphaCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + DeviceReset parent_reset; +}; #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_alpha_cpu; diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 35c3b0924e..02b914c876 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_ARM_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_ARM_CPU "arm-cpu" @@ -29,35 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU -typedef struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -} ARMCPUInfo; - -/** - * ARMCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * An ARM CPU model. - */ -struct ARMCPUClass { - CPUClass parent_class; - - const ARMCPUInfo *info; - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - - #define TYPE_AARCH64_CPU "aarch64-cpu" typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) -struct AArch64CPUClass { - ARMCPUClass parent_class; -}; - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4a86c8f831..a0282e0d28 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1116,6 +1116,31 @@ struct ArchCPU { uint64_t gt_cntfrq_hz; }; +typedef struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} ARMCPUInfo; + +/** + * ARMCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * An ARM CPU model. + */ +struct ARMCPUClass { + CPUClass parent_class; + + const ARMCPUInfo *info; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +struct AArch64CPUClass { + ARMCPUClass parent_class; +}; + /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index 75590cdd97..38dbcc0535 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -22,7 +22,6 @@ #define TARGET_AVR_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_AVR_CPU "avr-cpu" @@ -31,19 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) #define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU #define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) -/** - * AVRCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A AVR CPU model. - */ -struct AVRCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - - #endif /* TARGET_AVR_CPU_QOM_H */ diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 0487399cb2..8a17862737 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -147,6 +147,20 @@ struct ArchCPU { CPUAVRState env; }; +/** + * AVRCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A AVR CPU model. + */ +struct AVRCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + extern const struct VMStateDescription vms_avr_cpu; void avr_cpu_do_interrupt(CPUState *cpu); diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index d7e5f33e62..741ca97a1b 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_CRIS_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_CRIS_CPU "cris-cpu" @@ -30,22 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) -/** - * CRISCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * @vr: Version Register value. - * - * A CRIS CPU model. - */ -struct CRISCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; - - uint32_t vr; -}; - - #endif diff --git a/target/cris/cpu.h b/target/cris/cpu.h index b821bb7983..1be7f90319 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -179,6 +179,22 @@ struct ArchCPU { CPUCRISState env; }; +/** + * CRISCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * @vr: Version Register value. + * + * A CRIS CPU model. + */ +struct CRISCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; + + uint32_t vr; +}; #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_cris_cpu; diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h index f02df7ee6f..da92fe7468 100644 --- a/target/hexagon/cpu-qom.h +++ b/target/hexagon/cpu-qom.h @@ -10,7 +10,6 @@ #define QEMU_HEXAGON_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_HEXAGON_CPU "hexagon-cpu" diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b7d9cdfe11..5c454bf543 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -21,26 +21,10 @@ #define QEMU_HPPA_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_HPPA_CPU "hppa-cpu" #define TYPE_HPPA64_CPU "hppa64-cpu" OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) -/** - * HPPACPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. - * - * An HPPA CPU model. - */ -struct HPPACPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - DeviceReset parent_reset; -}; - - #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index b39bae00d3..cecec59700 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -253,6 +253,20 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; +/** + * HPPACPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * An HPPA CPU model. + */ +struct HPPACPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + DeviceReset parent_reset; +}; + #include "exec/cpu-all.h" static inline bool hppa_is_pa20(CPUHPPAState *env) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index dffc74c1ce..d4e216d000 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -21,8 +21,6 @@ #define QEMU_I386_CPU_QOM_H #include "hw/core/cpu.h" -#include "qemu/notify.h" -#include "qom/object.h" #ifdef TARGET_X86_64 #define TYPE_X86_CPU "x86_64-cpu" @@ -35,41 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) -typedef struct X86CPUModel X86CPUModel; - -/** - * X86CPUClass: - * @cpu_def: CPU model definition - * @host_cpuid_required: Whether CPU model requires cpuid from host. - * @ordering: Ordering on the "-cpu help" CPU model list. - * @migration_safe: See CpuDefinitionInfo::migration_safe - * @static_model: See CpuDefinitionInfo::static - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * An x86 CPU model or family. - */ -struct X86CPUClass { - CPUClass parent_class; - - /* CPU definition, automatically loaded by instance_init if not NULL. - * Should be eventually replaced by subclass-specific property defaults. - */ - X86CPUModel *model; - - bool host_cpuid_required; - int ordering; - bool migration_safe; - bool static_model; - - /* Optional description of CPU model. - * If unavailable, cpu_def->model_id is used */ - const char *model_description; - - DeviceRealize parent_realize; - DeviceUnrealize parent_unrealize; - ResettablePhases parent_phases; -}; - - #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6c6b066986..0028aeb0ef 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2037,6 +2037,44 @@ struct ArchCPU { bool xen_vapic; }; +typedef struct X86CPUModel X86CPUModel; + +/** + * X86CPUClass: + * @cpu_def: CPU model definition + * @host_cpuid_required: Whether CPU model requires cpuid from host. + * @ordering: Ordering on the "-cpu help" CPU model list. + * @migration_safe: See CpuDefinitionInfo::migration_safe + * @static_model: See CpuDefinitionInfo::static + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * An x86 CPU model or family. + */ +struct X86CPUClass { + CPUClass parent_class; + + /* + * CPU definition, automatically loaded by instance_init if not NULL. + * Should be eventually replaced by subclass-specific property defaults. + */ + X86CPUModel *model; + + bool host_cpuid_required; + int ordering; + bool migration_safe; + bool static_model; + + /* + * Optional description of CPU model. + * If unavailable, cpu_def->model_id is used. + */ + const char *model_description; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; + ResettablePhases parent_phases; +}; #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_x86_cpu; diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h index 82c86d146d..fa3fcf7186 100644 --- a/target/loongarch/cpu-qom.h +++ b/target/loongarch/cpu-qom.h @@ -9,7 +9,6 @@ #define LOONGARCH_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_LOONGARCH_CPU "loongarch-cpu" #define TYPE_LOONGARCH32_CPU "loongarch32-cpu" diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index df0cc8b7a3..273e8eae41 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_M68K_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_M68K_CPU "m68k-cpu" @@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX -/* - * M68kCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A Motorola 68k CPU model. - */ -struct M68kCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - - #endif diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7f34686a6f..6cfc696d2b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -169,6 +169,19 @@ struct ArchCPU { CPUM68KState env; }; +/* + * M68kCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A Motorola 68k CPU model. + */ +struct M68kCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; #ifndef CONFIG_USER_ONLY void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index 78f549b57d..92e539fb2f 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -21,25 +21,9 @@ #define QEMU_MICROBLAZE_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_MICROBLAZE_CPU "microblaze-cpu" OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU) -/** - * MicroBlazeCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A MicroBlaze CPU model. - */ -struct MicroBlazeCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - - #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e8000237d8..b5374365f5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -355,6 +355,19 @@ struct ArchCPU { MicroBlazeCPUConfig cfg; }; +/** + * MicroBlazeCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A MicroBlaze CPU model. + */ +struct MicroBlazeCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; #ifndef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs); diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 5822dfb1d2..0eea2a2598 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_MIPS_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #ifdef TARGET_MIPS64 #define TYPE_MIPS_CPU "mips64-cpu" @@ -34,23 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX -/** - * MIPSCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A MIPS CPU model. - */ -struct MIPSCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; - const struct mips_def_t *cpu_def; - - /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ - bool no_data_aborts; -}; - - #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 12cc1bfafd..52f13f0363 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1217,6 +1217,23 @@ struct ArchCPU { Clock *count_div; /* Divider for CP0_Count clock */ }; +/** + * MIPSCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A MIPS CPU model. + */ +struct MIPSCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; + const struct mips_def_t *cpu_def; + + /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ + bool no_data_aborts; +}; void mips_cpu_list(void); diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h index 931bc69b10..2fd9121540 100644 --- a/target/nios2/cpu-qom.h +++ b/target/nios2/cpu-qom.h @@ -10,7 +10,6 @@ #define QEMU_NIOS2_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_NIOS2_CPU "nios2-cpu" diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h index 1ba9fb0a4c..14bac33312 100644 --- a/target/openrisc/cpu-qom.h +++ b/target/openrisc/cpu-qom.h @@ -10,7 +10,6 @@ #define QEMU_OPENRISC_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_OPENRISC_CPU "or1k-cpu" diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 76efb614a6..91b3361dec 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -20,7 +20,6 @@ #define RISCV_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" @@ -44,21 +43,6 @@ #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") -typedef struct CPUArchState CPURISCVState; - OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) -/** - * RISCVCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A RISCV CPU model. - */ -struct RISCVCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b49fa17e68..bf58b0f0b5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -32,6 +32,8 @@ #include "qapi/qapi-types-common.h" #include "cpu-qom.h" +typedef struct CPUArchState CPURISCVState; + #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #if defined(TARGET_RISCV32) @@ -436,6 +438,20 @@ struct ArchCPU { GHashTable *pmu_event_ctr_map; }; +/** + * RISCVCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A RISCV CPU model. + */ +struct RISCVCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa_ext & ext) != 0; diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 6213d877f7..ac2e5785ef 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -20,7 +20,6 @@ #define RX_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_RX_CPU "rx-cpu" @@ -31,18 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX -/* - * RXCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A RX CPU model. - */ -struct RXCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - #endif diff --git a/target/rx/cpu.h b/target/rx/cpu.h index c81613770c..e931e77e85 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -112,6 +112,20 @@ struct ArchCPU { CPURXState env; }; +/* + * RXCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A RX CPU model. + */ +struct RXCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index ccf126b7a9..c59bb1eab1 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_S390_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_S390_CPU "s390x-cpu" @@ -30,38 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU) #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) -typedef struct S390CPUModel S390CPUModel; -typedef struct S390CPUDef S390CPUDef; - -typedef enum cpu_reset_type { - S390_CPU_RESET_NORMAL, - S390_CPU_RESET_INITIAL, - S390_CPU_RESET_CLEAR, -} cpu_reset_type; - -/** - * S390CPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. - * @load_normal: Performs a load normal. - * @cpu_reset: Performs a CPU reset. - * @initial_cpu_reset: Performs an initial CPU reset. - * - * An S/390 CPU model. - */ -struct S390CPUClass { - CPUClass parent_class; - - const S390CPUDef *cpu_def; - bool kvm_required; - bool is_static; - bool is_migration_safe; - const char *desc; - - DeviceRealize parent_realize; - DeviceReset parent_reset; - void (*load_normal)(CPUState *cpu); - void (*reset)(CPUState *cpu, cpu_reset_type type); -}; - #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 942589c597..fa3aac4f97 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -180,6 +180,36 @@ struct ArchCPU { uint32_t irqstate_saved_size; }; +typedef enum cpu_reset_type { + S390_CPU_RESET_NORMAL, + S390_CPU_RESET_INITIAL, + S390_CPU_RESET_CLEAR, +} cpu_reset_type; + +/** + * S390CPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * @load_normal: Performs a load normal. + * @cpu_reset: Performs a CPU reset. + * @initial_cpu_reset: Performs an initial CPU reset. + * + * An S/390 CPU model. + */ +struct S390CPUClass { + CPUClass parent_class; + + const S390CPUDef *cpu_def; + bool kvm_required; + bool is_static; + bool is_migration_safe; + const char *desc; + + DeviceRealize parent_realize; + DeviceReset parent_reset; + void (*load_normal)(CPUState *cpu); + void (*reset)(CPUState *cpu, cpu_reset_type type); +}; #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_s390_cpu; diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h index cc7305ec21..d7b8912989 100644 --- a/target/s390x/cpu_models.h +++ b/target/s390x/cpu_models.h @@ -18,7 +18,7 @@ #include "hw/core/cpu.h" /* static CPU definition */ -struct S390CPUDef { +typedef struct S390CPUDef { const char *name; /* name exposed to the user */ const char *desc; /* description exposed to the user */ uint8_t gen; /* hw generation identification */ @@ -38,10 +38,10 @@ struct S390CPUDef { S390FeatBitmap full_feat; /* used to init full_feat from generated data */ S390FeatInit full_init; -}; +} S390CPUDef; /* CPU model based on a CPU definition */ -struct S390CPUModel { +typedef struct S390CPUModel { const S390CPUDef *def; S390FeatBitmap features; /* values copied from the "host" model, can change during migration */ @@ -49,7 +49,7 @@ struct S390CPUModel { uint32_t cpu_id; /* CPU id */ uint8_t cpu_id_format; /* CPU id format bit */ uint8_t cpu_ver; /* CPU version, usually "ff" for kvm */ -}; +} S390CPUModel; /* * CPU ID diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index bd0ef49fa1..6cf5fbb074 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_SUPERH_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_SUPERH_CPU "superh-cpu" @@ -34,26 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX -/** - * SuperHCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * @pvr: Processor Version Register - * @prr: Processor Revision Register - * @cvr: Cache Version Register - * - * A SuperH CPU model. - */ -struct SuperHCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; - - uint32_t pvr; - uint32_t prr; - uint32_t cvr; -}; - - #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dbe00e29c2..360eac1fbe 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -209,6 +209,26 @@ struct ArchCPU { CPUSH4State env; }; +/** + * SuperHCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * @pvr: Processor Version Register + * @prr: Processor Revision Register + * @cvr: Cache Version Register + * + * A SuperH CPU model. + */ +struct SuperHCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; + + uint32_t pvr; + uint32_t prr; + uint32_t cvr; +}; void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index aca29415b4..a86331bd58 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -21,7 +21,6 @@ #define QEMU_SPARC_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #ifdef TARGET_SPARC64 #define TYPE_SPARC_CPU "sparc64-cpu" @@ -34,21 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX -typedef struct sparc_def_t sparc_def_t; -/** - * SPARCCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A SPARC CPU model. - */ -struct SPARCCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; - sparc_def_t *cpu_def; -}; - - #endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a808f2aff6..6999a10a40 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -249,7 +249,7 @@ typedef struct trap_state { #endif #define TARGET_INSN_START_EXTRA_WORDS 1 -struct sparc_def_t { +typedef struct sparc_def_t { const char *name; target_ulong iu_version; uint32_t fpu_version; @@ -263,7 +263,7 @@ struct sparc_def_t { uint32_t features; uint32_t nwindows; uint32_t maxtl; -}; +} sparc_def_t; #define FEATURE(X) CPU_FEATURE_BIT_##X, enum { @@ -567,6 +567,20 @@ struct ArchCPU { CPUSPARCState env; }; +/** + * SPARCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A SPARC CPU model. + */ +struct SPARCCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; + sparc_def_t *cpu_def; +}; #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_sparc_cpu; diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 2598651008..e35dc1ad2d 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -21,8 +21,6 @@ #define QEMU_TRICORE_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" - #define TYPE_TRICORE_CPU "tricore-cpu" @@ -31,12 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX -struct TriCoreCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - - #endif /* QEMU_TRICORE_CPU_QOM_H */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c537a33ee8..de3ab53a83 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -68,6 +68,12 @@ struct ArchCPU { CPUTriCoreState env; }; +struct TriCoreCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 03873ea50b..d932346b5f 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -30,7 +30,6 @@ #define QEMU_XTENSA_CPU_QOM_H #include "hw/core/cpu.h" -#include "qom/object.h" #define TYPE_XTENSA_CPU "xtensa-cpu" @@ -39,24 +38,4 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU) #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX -typedef struct XtensaConfig XtensaConfig; - -/** - * XtensaCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * @config: The CPU core configuration. - * - * An Xtensa CPU model. - */ -struct XtensaCPUClass { - CPUClass parent_class; - - DeviceRealize parent_realize; - ResettablePhases parent_phases; - - const XtensaConfig *config; -}; - - #endif diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d6d2fb1f4e..dd81729306 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -426,7 +426,7 @@ extern const XtensaOpcodeTranslators xtensa_core_opcodes; extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; extern const XtensaOpcodeTranslators xtensa_fpu_opcodes; -struct XtensaConfig { +typedef struct XtensaConfig { const char *name; uint64_t options; XtensaGdbRegmap gdb_regmap; @@ -489,7 +489,7 @@ struct XtensaConfig { const xtensa_mpu_entry *mpu_bg; bool use_first_nan; -}; +} XtensaConfig; typedef struct XtensaConfigList { const XtensaConfig *config; @@ -562,6 +562,22 @@ struct ArchCPU { Clock *clock; }; +/** + * XtensaCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * @config: The CPU core configuration. + * + * An Xtensa CPU model. + */ +struct XtensaCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; + + const XtensaConfig *config; +}; #ifndef CONFIG_USER_ONLY bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, From patchwork Tue Nov 7 12:24:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741872 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587977wrr; Tue, 7 Nov 2023 04:28:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IH2Ahi6DBlfx3d06vXWXtnaGGNToT3kmqv2kNPLzWjtCxPTLnJ/JlZOaeYfUoY9QxN9qSX3 X-Received: by 2002:a05:620a:63c7:b0:76d:89c5:78a0 with SMTP id pw7-20020a05620a63c700b0076d89c578a0mr34458567qkn.63.1699360098089; Tue, 07 Nov 2023 04:28:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360098; cv=none; d=google.com; s=arc-20160816; b=lgcPpx3RobB9FMtrgn2Xpu83/USHg58OIlfKI9angBshi9zDd1UmFgHnPxpPyq3p2J QpgsM0T3SEVcV6cZM3jaD0hRzD7uETrj2Esm6uR2TJUSy0Tq+/CDNKTcRQ6zGBUr0CJu MfjRo6PjdbJtHA/XGkMdCboPrn+jFyDj622uUycFokJyaQrN4mXQpUEsMpG3aaFL/72B tbDduOhGV2im1s8BPzx5yS9AwlqnMod+ueAYnwZ6n79KLQS8DTfZdcqPJbXG0p624sXi CfaBS9vAo4LJHo8Qc2XNp86xPzpnLU2vXYrjclRu3OADm6erXQSEN6VQ96AAljwaEvec 4qqg== ARC-Message-Signature: i=1; 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Tue, 07 Nov 2023 04:25:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , Ani Sinha , Warner Losh , Kyle Evans , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Laurent Vivier , David Hildenbrand , Ilya Leoshkevich , Thomas Huth Subject: [PULL 51/75] hw/cpu: Clean up global variable shadowing Date: Tue, 7 Nov 2023 13:24:37 +0100 Message-ID: <20231107122442.58674-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix: hw/core/machine.c:1302:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const CPUArchId *cpus = possible_cpus->cpus; ^ hw/core/numa.c:69:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] uint16List *cpus = NULL; ^ hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] CPUArchIdList *cpus = ms->possible_cpus; ^ hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] unsigned cpus = config->has_cpus ? config->cpus : 0; ^ include/hw/core/cpu.h:589:17: note: previous declaration is here extern CPUTailQ cpus; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20231010115048.11856-2-philmd@linaro.org> --- include/hw/core/cpu.h | 8 ++++---- bsd-user/main.c | 2 +- cpu-common.c | 6 +++--- linux-user/main.c | 2 +- target/s390x/cpu_models.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index eb943efb8f..77893d7b81 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -586,13 +586,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu) } typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; -extern CPUTailQ cpus; +extern CPUTailQ cpus_queue; -#define first_cpu QTAILQ_FIRST_RCU(&cpus) +#define first_cpu QTAILQ_FIRST_RCU(&cpus_queue) #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) -#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) +#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node) #define CPU_FOREACH_SAFE(cpu, next_cpu) \ - QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) + QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) extern __thread CPUState *current_cpu; diff --git a/bsd-user/main.c b/bsd-user/main.c index c402fadf46..e6014f517e 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -118,7 +118,7 @@ void fork_end(int child) */ CPU_FOREACH_SAFE(cpu, next_cpu) { if (cpu != thread_cpu) { - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); } } mmap_fork_end(child); diff --git a/cpu-common.c b/cpu-common.c index 45c745ecf6..c81fd72d16 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -73,7 +73,7 @@ static int cpu_get_free_index(void) return max_cpu_index; } -CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); +CPUTailQ cpus_queue = QTAILQ_HEAD_INITIALIZER(cpus_queue); static unsigned int cpu_list_generation_id; unsigned int cpu_list_generation_id_get(void) @@ -90,7 +90,7 @@ void cpu_list_add(CPUState *cpu) } else { assert(!cpu_index_auto_assigned); } - QTAILQ_INSERT_TAIL_RCU(&cpus, cpu, node); + QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node); cpu_list_generation_id++; } @@ -102,7 +102,7 @@ void cpu_list_remove(CPUState *cpu) return; } - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu_list_generation_id++; } diff --git a/linux-user/main.c b/linux-user/main.c index 0c23584a96..0cdaf30d34 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -156,7 +156,7 @@ void fork_end(int child) Discard information about the parent threads. */ CPU_FOREACH_SAFE(cpu, next_cpu) { if (cpu != thread_cpu) { - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); } } qemu_init_cpu_list(); diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 4dead48650..5c455d00c0 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -757,7 +757,7 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, const S390CPUDef *def = s390_find_cpu_def(type, gen, ec_ga, NULL); g_assert(def); - g_assert(QTAILQ_EMPTY_RCU(&cpus)); + g_assert(QTAILQ_EMPTY_RCU(&cpus_queue)); /* build the CPU model */ s390_qemu_cpu_model.def = def; From patchwork Tue Nov 7 12:24:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741867 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1587830wrr; Tue, 7 Nov 2023 04:27:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IFkz3SOFfb0aLHn5oADwoVrUkU63PhIECcpt5jRpegjpnJZ13tOQzbJksvrWdsA1oXJ+8/h X-Received: by 2002:a05:620a:1084:b0:775:cf5f:8a57 with SMTP id g4-20020a05620a108400b00775cf5f8a57mr32888019qkk.7.1699360074511; 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Iglesias" , Alistair Francis , Bin Meng , Tyrone Ting , Hao Wu Subject: [PULL 68/75] hw/sd: Declare QOM types using DEFINE_TYPES() macro Date: Tue, 7 Nov 2023 13:24:38 +0100 Message-ID: <20231107122442.58674-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Mechanical transformation using the following comby script: [pattern-x1] match=''' static const TypeInfo :[i1~.*_info] = { :[body] }; static void :[rt1~.*_register_type.](void) { type_register_static(&:[i2~.*_info]); } type_init(:[rt2~.*_register_type.]) ''' rewrite=''' static const TypeInfo :[i1][] = { { :[body] }, }; DEFINE_TYPES(:[i1]) ''' rule='where :[i1] == :[i2], :[rt1] == :[rt2]' [pattern-x2] match=''' static const TypeInfo :[i1a~.*_info] = { :[body1] }; ... static const TypeInfo :[i2a~.*_info] = { :[body2] }; static void :[rt1~.*_register_type.](void) { type_register_static(&:[i1b~.*_info]); type_register_static(&:[i2b~.*_info]); } type_init(:[rt2~.*_register_type.]) ''' rewrite=''' static const TypeInfo :[i1a][] = { { :[body1] }, { :[body2] }, }; DEFINE_TYPES(:[i1a]) ''' rule=''' where :[i1a] == :[i1b], :[i2a] == :[i2b], :[rt1] == :[rt2] ''' and re-indented manually. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-Id: <20231031080603.86889-2-philmd@linaro.org> --- hw/sd/aspeed_sdhci.c | 19 ++++++++----------- hw/sd/bcm2835_sdhost.c | 33 ++++++++++++++------------------- hw/sd/cadence_sdhci.c | 21 +++++++++------------ hw/sd/core.c | 19 ++++++++----------- hw/sd/npcm7xx_sdhci.c | 21 +++++++++------------ hw/sd/pl181.c | 35 +++++++++++++++-------------------- hw/sd/pxa2xx_mmci.c | 35 +++++++++++++++-------------------- hw/sd/sd.c | 37 ++++++++++++++++--------------------- hw/sd/sdhci-pci.c | 25 +++++++++++-------------- hw/sd/ssi-sd.c | 19 ++++++++----------- 10 files changed, 113 insertions(+), 151 deletions(-) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index be8cafd65f..e53206d959 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -198,16 +198,13 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) device_class_set_props(dc, aspeed_sdhci_properties); } -static const TypeInfo aspeed_sdhci_info = { - .name = TYPE_ASPEED_SDHCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AspeedSDHCIState), - .class_init = aspeed_sdhci_class_init, +static const TypeInfo aspeed_sdhci_types[] = { + { + .name = TYPE_ASPEED_SDHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedSDHCIState), + .class_init = aspeed_sdhci_class_init, + }, }; -static void aspeed_sdhci_register_types(void) -{ - type_register_static(&aspeed_sdhci_info); -} - -type_init(aspeed_sdhci_register_types) +DEFINE_TYPES(aspeed_sdhci_types) diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c index 9431c35914..a600cf39e2 100644 --- a/hw/sd/bcm2835_sdhost.c +++ b/hw/sd/bcm2835_sdhost.c @@ -436,24 +436,19 @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_sdhost; } -static const TypeInfo bcm2835_sdhost_info = { - .name = TYPE_BCM2835_SDHOST, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(BCM2835SDHostState), - .class_init = bcm2835_sdhost_class_init, - .instance_init = bcm2835_sdhost_init, +static const TypeInfo bcm2835_sdhost_types[] = { + { + .name = TYPE_BCM2835_SDHOST, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BCM2835SDHostState), + .class_init = bcm2835_sdhost_class_init, + .instance_init = bcm2835_sdhost_init, + }, + { + .name = TYPE_BCM2835_SDHOST_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + }, }; -static const TypeInfo bcm2835_sdhost_bus_info = { - .name = TYPE_BCM2835_SDHOST_BUS, - .parent = TYPE_SD_BUS, - .instance_size = sizeof(SDBus), -}; - -static void bcm2835_sdhost_register_types(void) -{ - type_register_static(&bcm2835_sdhost_info); - type_register_static(&bcm2835_sdhost_bus_info); -} - -type_init(bcm2835_sdhost_register_types) +DEFINE_TYPES(bcm2835_sdhost_types) diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c index 75db34befe..ef4e0d74e3 100644 --- a/hw/sd/cadence_sdhci.c +++ b/hw/sd/cadence_sdhci.c @@ -175,17 +175,14 @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data) dc->vmsd = &vmstate_cadence_sdhci; } -static const TypeInfo cadence_sdhci_info = { - .name = TYPE_CADENCE_SDHCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(CadenceSDHCIState), - .instance_init = cadence_sdhci_instance_init, - .class_init = cadence_sdhci_class_init, +static const TypeInfo cadence_sdhci_types[] = { + { + .name = TYPE_CADENCE_SDHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(CadenceSDHCIState), + .instance_init = cadence_sdhci_instance_init, + .class_init = cadence_sdhci_class_init, + }, }; -static void cadence_sdhci_register_types(void) -{ - type_register_static(&cadence_sdhci_info); -} - -type_init(cadence_sdhci_register_types) +DEFINE_TYPES(cadence_sdhci_types) diff --git a/hw/sd/core.c b/hw/sd/core.c index 30ee62c510..52d5d90045 100644 --- a/hw/sd/core.c +++ b/hw/sd/core.c @@ -259,16 +259,13 @@ void sdbus_reparent_card(SDBus *from, SDBus *to) sdbus_set_readonly(to, readonly); } -static const TypeInfo sd_bus_info = { - .name = TYPE_SD_BUS, - .parent = TYPE_BUS, - .instance_size = sizeof(SDBus), - .class_size = sizeof(SDBusClass), +static const TypeInfo sd_bus_types[] = { + { + .name = TYPE_SD_BUS, + .parent = TYPE_BUS, + .instance_size = sizeof(SDBus), + .class_size = sizeof(SDBusClass), + }, }; -static void sd_bus_register_types(void) -{ - type_register_static(&sd_bus_info); -} - -type_init(sd_bus_register_types) +DEFINE_TYPES(sd_bus_types) diff --git a/hw/sd/npcm7xx_sdhci.c b/hw/sd/npcm7xx_sdhci.c index b2f5b4a542..9958680090 100644 --- a/hw/sd/npcm7xx_sdhci.c +++ b/hw/sd/npcm7xx_sdhci.c @@ -166,17 +166,14 @@ static void npcm7xx_sdhci_instance_init(Object *obj) TYPE_SYSBUS_SDHCI); } -static const TypeInfo npcm7xx_sdhci_info = { - .name = TYPE_NPCM7XX_SDHCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(NPCM7xxSDHCIState), - .instance_init = npcm7xx_sdhci_instance_init, - .class_init = npcm7xx_sdhci_class_init, +static const TypeInfo npcm7xx_sdhci_types[] = { + { + .name = TYPE_NPCM7XX_SDHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxSDHCIState), + .instance_init = npcm7xx_sdhci_instance_init, + .class_init = npcm7xx_sdhci_class_init, + }, }; -static void npcm7xx_sdhci_register_types(void) -{ - type_register_static(&npcm7xx_sdhci_info); -} - -type_init(npcm7xx_sdhci_register_types) +DEFINE_TYPES(npcm7xx_sdhci_types) diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c index 5e554bd467..2b33814d83 100644 --- a/hw/sd/pl181.c +++ b/hw/sd/pl181.c @@ -519,14 +519,6 @@ static void pl181_class_init(ObjectClass *klass, void *data) k->user_creatable = false; } -static const TypeInfo pl181_info = { - .name = TYPE_PL181, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(PL181State), - .instance_init = pl181_init, - .class_init = pl181_class_init, -}; - static void pl181_bus_class_init(ObjectClass *klass, void *data) { SDBusClass *sbc = SD_BUS_CLASS(klass); @@ -535,17 +527,20 @@ static void pl181_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = pl181_set_readonly; } -static const TypeInfo pl181_bus_info = { - .name = TYPE_PL181_BUS, - .parent = TYPE_SD_BUS, - .instance_size = sizeof(SDBus), - .class_init = pl181_bus_class_init, +static const TypeInfo pl181_info[] = { + { + .name = TYPE_PL181, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PL181State), + .instance_init = pl181_init, + .class_init = pl181_class_init, + }, + { + .name = TYPE_PL181_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + .class_init = pl181_bus_class_init, + }, }; -static void pl181_register_types(void) -{ - type_register_static(&pl181_info); - type_register_static(&pl181_bus_info); -} - -type_init(pl181_register_types) +DEFINE_TYPES(pl181_info) diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index 4749e935d8..5e8ea69188 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -575,25 +575,20 @@ static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = pxa2xx_mmci_set_readonly; } -static const TypeInfo pxa2xx_mmci_info = { - .name = TYPE_PXA2XX_MMCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(PXA2xxMMCIState), - .instance_init = pxa2xx_mmci_instance_init, - .class_init = pxa2xx_mmci_class_init, +static const TypeInfo pxa2xx_mmci_types[] = { + { + .name = TYPE_PXA2XX_MMCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PXA2xxMMCIState), + .instance_init = pxa2xx_mmci_instance_init, + .class_init = pxa2xx_mmci_class_init, + }, + { + .name = TYPE_PXA2XX_MMCI_BUS, + .parent = TYPE_SD_BUS, + .instance_size = sizeof(SDBus), + .class_init = pxa2xx_mmci_bus_class_init, + }, }; -static const TypeInfo pxa2xx_mmci_bus_info = { - .name = TYPE_PXA2XX_MMCI_BUS, - .parent = TYPE_SD_BUS, - .instance_size = sizeof(SDBus), - .class_init = pxa2xx_mmci_bus_class_init, -}; - -static void pxa2xx_mmci_register_types(void) -{ - type_register_static(&pxa2xx_mmci_info); - type_register_static(&pxa2xx_mmci_bus_info); -} - -type_init(pxa2xx_mmci_register_types) +DEFINE_TYPES(pxa2xx_mmci_types) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 4823befdef..1106ff7d78 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2278,16 +2278,6 @@ static void sd_class_init(ObjectClass *klass, void *data) sc->proto = &sd_proto_sd; } -static const TypeInfo sd_info = { - .name = TYPE_SD_CARD, - .parent = TYPE_DEVICE, - .instance_size = sizeof(SDState), - .class_size = sizeof(SDCardClass), - .class_init = sd_class_init, - .instance_init = sd_instance_init, - .instance_finalize = sd_instance_finalize, -}; - /* * We do not model the chip select pin, so allow the board to select * whether card should be in SSI or MMC/SD mode. It is also up to the @@ -2303,16 +2293,21 @@ static void sd_spi_class_init(ObjectClass *klass, void *data) sc->proto = &sd_proto_spi; } -static const TypeInfo sd_spi_info = { - .name = TYPE_SD_CARD_SPI, - .parent = TYPE_SD_CARD, - .class_init = sd_spi_class_init, +static const TypeInfo sd_types[] = { + { + .name = TYPE_SD_CARD, + .parent = TYPE_DEVICE, + .instance_size = sizeof(SDState), + .class_size = sizeof(SDCardClass), + .class_init = sd_class_init, + .instance_init = sd_instance_init, + .instance_finalize = sd_instance_finalize, + }, + { + .name = TYPE_SD_CARD_SPI, + .parent = TYPE_SD_CARD, + .class_init = sd_spi_class_init, + }, }; -static void sd_register_types(void) -{ - type_register_static(&sd_info); - type_register_static(&sd_spi_info); -} - -type_init(sd_register_types) +DEFINE_TYPES(sd_types) diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c index c737c8b930..9b7bee8b3f 100644 --- a/hw/sd/sdhci-pci.c +++ b/hw/sd/sdhci-pci.c @@ -68,20 +68,17 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data) sdhci_common_class_init(klass, data); } -static const TypeInfo sdhci_pci_info = { - .name = TYPE_PCI_SDHCI, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(SDHCIState), - .class_init = sdhci_pci_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, +static const TypeInfo sdhci_pci_types[] = { + { + .name = TYPE_PCI_SDHCI, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(SDHCIState), + .class_init = sdhci_pci_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, }, }; -static void sdhci_pci_register_type(void) -{ - type_register_static(&sdhci_pci_info); -} - -type_init(sdhci_pci_register_type) +DEFINE_TYPES(sdhci_pci_types) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 167c03b780..a6cc1ad6c8 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -403,16 +403,13 @@ static void ssi_sd_class_init(ObjectClass *klass, void *data) dc->user_creatable = false; } -static const TypeInfo ssi_sd_info = { - .name = TYPE_SSI_SD, - .parent = TYPE_SSI_PERIPHERAL, - .instance_size = sizeof(ssi_sd_state), - .class_init = ssi_sd_class_init, +static const TypeInfo ssi_sd_types[] = { + { + .name = TYPE_SSI_SD, + .parent = TYPE_SSI_PERIPHERAL, + .instance_size = sizeof(ssi_sd_state), + .class_init = ssi_sd_class_init, + }, }; -static void ssi_sd_register_types(void) -{ - type_register_static(&ssi_sd_info); -} - -type_init(ssi_sd_register_types) +DEFINE_TYPES(ssi_sd_types) From patchwork Tue Nov 7 12:24:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741878 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1588428wrr; Tue, 7 Nov 2023 04:29:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IFr6kLVxnrA/1cf9KXBNKVVrM3AqC8X7IwwTSpxaR5SJFJCY/6xk515tiCkfAdge7X5zIc0 X-Received: by 2002:a05:620a:28d3:b0:778:8bfc:7a0 with SMTP id l19-20020a05620a28d300b007788bfc07a0mr33408542qkp.30.1699360160567; Tue, 07 Nov 2023 04:29:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360160; cv=none; d=google.com; s=arc-20160816; b=lQosN+KiHjkqxbPGn7QylAkxSXiZJnPK/WNCyyBJRvR3CPjHF/Og1/LcPx9jknzpGB yxPU5RPQWz8N1pA3q3bXFMpl7u0lWeCwsUlpX5VtN2n9ORYgM6s53FHSHIbzt5kd6OBq Tzr6aTc+oMTUo+LQuyHB68P2EONlXV4pyIUDFKI3zlfuoDfdxTvRCoC1/i8y4LCwtUzw +BSnNJNEe1YRiVFYhQMyxwp/GkZVsYyUT+rP0g1N2SzDw9+o3aOF8CCyAskPo5+viuA0 y7aEolG5/gnycX9fuedvAOE9kIKZJlBXR++hQ9d/RXqxjV1BA0qlhplP05Ne3V0d57cC gQeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qmG50O/2f50/2WgP2HPpZwiYXOel5yrYkpXTGRW5eAc=; fh=zXMpR0HDK0j6A1IwewknO0nLcQYT+10Y41Xt7eYFvs4=; b=NoZYoE4bwABh3VP6nByuvzCEtxkaFYfowka2u8sMIMB3uBQ0MBF0TOo04tWxXyJqfg sgJy452yJjQOEWM9g8TFnWzd+Z1U7y+1DAxE/UYCMP8usAxfqjNcE+m0se2rRgcM86rk wvoDp8eA1wl33uT9Mr8n9RluPGsA3T2PAy5KHKEeZCE1YmxYNd1dXFlIpCA76wL/L4V9 bgOkV9HRqP5/KYtZeDrrkctfC28vgLSiBpfnzkLukAe5EJdueQclaCFFVe6GtFAmnKOI R1I5oq8xVDu7L/G8F+dV0hx2oszsihmy2EDj5fIlIVAkg0Bcf0jFpMteF8lmSkkOaq2w YOXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YqDKViov; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Thomas Huth Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231107102104.14342-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2a17decd31..2a9354e695 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1861,6 +1861,7 @@ M: Max Filippov S: Maintained F: hw/xtensa/xtfpga.c F: hw/net/opencores_eth.c +F: include/hw/xtensa/mx_pic.h Devices ------- From patchwork Tue Nov 7 12:24:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741877 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1588356wrr; Tue, 7 Nov 2023 04:29:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IGoE8HxYZeMc0Bj4rTASmspxK8FVU3WumsqaMsMwLJzhyLwCQeWFdFchBbvGleNO6A6HSck X-Received: by 2002:a05:620a:d85:b0:76f:93e:4b2f with SMTP id q5-20020a05620a0d8500b0076f093e4b2fmr30356874qkl.38.1699360150456; Tue, 07 Nov 2023 04:29:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360150; cv=none; d=google.com; s=arc-20160816; b=PjZ3kr5WDZvDMCtFqk+YGYnj0PiGQULyjesvBaq+RJyolYdDwzdr2SFoH/GcDWSQKP z5aoAlQVsiUb3edgkR9pU5YFa7T6D+AxTAOXY7O3BUrTZcPveDF6leO8e3xGxo0ntmt3 10bumpqH4Qo3vtkZ8KE99FiKPMaFyxMoefV3p72LS8fZXK605IT3peghAxWa4tVJzTEk i2Eahu705r1g+ilxTZf3WoIwUvB/oBIvZODj66c9/yf9RAWbEYjPTfZXFX2wOJjOJdg/ TXxlX45BeXY5ViAnwu/KUyxZC6PLH7DShuA1PEgkxjY/c34yKGuHNTRyJU2T8CJywxZl PMsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G5jwu7f17a+yqtzy4C256uds7gVdP2jJyZeTSPjjH48=; fh=66UNbUoIwQFpj+xJ72csPrpPDRhjYRBQvwtxL44rsDU=; b=q+jNQFt+/pG1FgfSu8NxDOp9Dx8ivIfHTM2IFOWLBXDli6ksAuXx8wQ7uGzZpS3KOt xeENKSesVOQsKMeLKxLWicH6IgcU61Sm88/hN/jvOVxYcqvv2H2XUuIxkvATsHTxbVv6 3R7DjX0GH8X1ayvdz5NujIChcy6Djn4Ow3kERvnTGIJRwDzT1wZ9Dt1DS+kfYitW6I4l sd+IrtEWpxy486n4fkSL9MXB399UB1D3HCDSzgZFPfNPJpIKkqw1N79qiiVuTDS6WY/L PA9B9SheOyRwqO4XufjwYUYxk8yHCvnI5fJh13+Pg57CGWE/1JufoAKhOWVLUVmMMzu5 ARfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mzdkjLFA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Thomas Huth Reviewed-by: Konstantin Kostiuk Message-ID: <20231107101811.14189-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 2a9354e695..bc69253a25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3145,10 +3145,11 @@ M: Michael Roth M: Konstantin Kostiuk S: Maintained F: qga/ +F: contrib/systemd/qemu-guest-agent.service F: docs/interop/qemu-ga.rst F: docs/interop/qemu-ga-ref.rst F: scripts/qemu-guest-agent/ -F: tests/unit/test-qga.c +F: tests/*/test-qga* T: git https://github.com/mdroth/qemu.git qga QEMU Guest Agent Win32 From patchwork Tue Nov 7 12:24:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741876 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1588338wrr; Tue, 7 Nov 2023 04:29:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFyADF0DBpO1GSsYfdFIkwr5tlEhFpqR4OauuSlJ4lJZcKunsN0sF5+uoFDKSMORZ5OZKPn X-Received: by 2002:a05:6830:7181:b0:6b9:a926:4a12 with SMTP id el1-20020a056830718100b006b9a9264a12mr41575928otb.28.1699360147191; Tue, 07 Nov 2023 04:29:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360147; cv=none; d=google.com; s=arc-20160816; b=eKCc4ecF+m2dckKOoEtYlxNsdZaYicMyfIQLEAyrzyFijquNQ2gR+opt9fuSWQMrJ5 mdibyuEW6bwUXdHhBQD4tnTDg19haCGKOSzJxk/LCs1CIb10s72eK/81NYHzjAR8+uoT P67H32IX9llXn8hpOwuUyT62t+tAPyOwa8yPVPQIUy6k1XxINchQeej8Kk853ZdCEBkH 9jckCKG5kA6/hNBiLhqtM9/kQs8OSpx05JUGQZDwopI6NfbxVYNrvREPPN9zjvQXFgaT 2Tn4Qro7tRA1OIINSJhpFJJ3QWpEvYPrZ6tFCEgwVhynpFdhO4m1C23X231neVgC80co 0QcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bPpjDkEUgqCeZLuJ7FjDj9Qp3yXD435hoj9y2GuMgcc=; fh=cNSzr/W9J/4aJpqP86zm6hStvbeVv6h0MRvfoStHJZE=; b=MexQF4Iygt8+hsDVR05puWmRoMvER6oqC5Xxto4ip2kZl0Wzrm8bzol8e8fMzLVoh/ wBToHnzWu6/s/DRArjzYoZwc1oECIm8tK4g+hfQA0U0kJ0T6zSM0pZ9z3CGSl6wBqKID kuU7HMxmJhPVWRzDqRN3fxu5elnYTGXJAIPIbYUSADnvZ7mGDEmVMJ/KfKwEgWAOtkUS hgvybvYJghCp4LUjTfaMjFD8G5AfezeBe98mBFZh9n1ri7QCstzPGOu9/INuvTqvWKxZ hZsvPjfaRCwnO9iK/s8A3OadDf/g2C8ulpLbQDw/Q+HfFlfBS9BuhS6K7mkdZXYMNDTP GIQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V8aVhrGf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 07 Nov 2023 04:26:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Zongmin Zhou , Zongmin Zhou , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 75/75] dump: Add close fd on error return to avoid resource leak Date: Tue, 7 Nov 2023 13:24:41 +0100 Message-ID: <20231107122442.58674-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107122442.58674-1-philmd@linaro.org> References: <20231107122442.58674-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zongmin Zhou Reported-by: Coverity CID 1523842 (RESOURCE_LEAK) Fixes: e6549197f7 ("dump: Add command interface for kdump-raw formats") Signed-off-by: Zongmin Zhou Reviewed-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231107024417.585475-1-min_halo@163.com> Signed-off-by: Philippe Mathieu-Daudé --- dump/dump.c | 1 + 1 file changed, 1 insertion(+) diff --git a/dump/dump.c b/dump/dump.c index 1c304cadfd..ad5294e853 100644 --- a/dump/dump.c +++ b/dump/dump.c @@ -2160,6 +2160,7 @@ void qmp_dump_guest_memory(bool paging, const char *protocol, return; } if (kdump_raw && lseek(fd, 0, SEEK_CUR) == (off_t) -1) { + close(fd); error_setg(errp, "kdump-raw formats require a seekable file"); return; }