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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:22 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 1/7] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Date: Fri, 3 Nov 2023 09:24:10 -0300 Message-Id: <20231103122416.2724355-2-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). This is a side-effect of how we implement the GNU extension feenableexcept, where feenableexcept/fesetenv/fesetmode/feupdateenv might issue prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE) depending of the argument. And on PR_FP_EXC_PRECISE, setting a floating-point exception flag triggers a trap. To make the both functions follow the C23, fesetexcept and fesetexceptflag now fail if the argument may trigger a trap. The math tests now check for an value different than 0, instead of bail out as unsupported for EXCEPTION_SET_FORCES_TRAP. Checked on powerpc64le-linux-gnu. --- math/test-fesetexcept-traps.c | 11 ++++------- math/test-fexcept-traps.c | 11 ++++------- sysdeps/powerpc/fpu/fesetexcept.c | 5 +++++ sysdeps/powerpc/fpu/fsetexcptflg.c | 9 ++++++++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 71b6e45b33..96f6c4752f 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -39,16 +39,13 @@ do_test (void) return result; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* Verify fesetexcept does not cause exception traps. */ + /* Verify fesetexcept does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); - else + else if (!EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexcept (FE_ALL_EXCEPT) failed"); if (EXCEPTION_TESTS (float)) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9701c3c320..9b8f583ae6 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -63,14 +63,11 @@ do_test (void) result = 1; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* The test is that this does not cause exception traps. */ + /* The test is that this does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); - if (ret != 0) + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); result = 1; diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..2850156d3a 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,11 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l != u.l) { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 2b22f913c0..6517e8ea03 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (n.fenv); + { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + + fesetenv_register (n.fenv); + } /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) From patchwork Fri Nov 3 12:24:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 740659 Delivered-To: patch@linaro.org Received: by 2002:a5d:538f:0:b0:32d:baff:b0ca with SMTP id d15csp1335171wrv; Fri, 3 Nov 2023 05:25:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHipxQPj0SR6r8oK7Or/OBfTbRxa5HtDhN+sEbrNvNsZsypT26q23u+PjLGlFccRuosiSBp X-Received: by 2002:ac8:7f08:0:b0:41e:3795:8b7d with SMTP id f8-20020ac87f08000000b0041e37958b7dmr21677723qtk.61.1699014301377; Fri, 03 Nov 2023 05:25:01 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1699014301; cv=pass; d=google.com; s=arc-20160816; b=cAotVjAXfNnwbTrZCKyWn5kiDL6vWtYolEPwei/nsDMBv9iU6ERKqBiFF2hkyEJrap pHWq6ZwyfCb83AqZQ8AX1HtnYSn73Q3DyAzb1i23TeFCYVO3LX2HY+o/Rnny2yFUjT7s k0C7J/5VASiAMJwxkRpF2rK5pkmoF4c4GMolKlylfMKH7NWzCPHH+Ndmg9xkuHxYhIk+ r6+WOCEBaHG8ddZEMei8I5bnKdfM/UFc77xLmHGhZ3bUNYXRQmoNnR2aN9/JQbQCL3Mc PujOP5R1ENQh6EPXYmJSbYfSNCrDYW9tCHvIGq3C4atnsnP+vQQE6wiGovJnSfPul1XV gm3g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=8ujOWCJ4a4246lq6dUQMnVl3c7/GQti81/iYWZLRcvg=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=y3Kz21O7vJECaMRCaHsXsnAwQyEZtRaDPUbHLs0zwvAf2j++ygjFbFPYwsLJGgRXPB L5GHygR3hBuFNOo3zAjlFolDibikhkQn2St2dN7aSZnF+f9DK/LM0cACsM3fbBeuCoyC m58TKyGh4Os+3rgMk80iDt/CuZ+8v6kvddDC8kEl2zSSsvw++AdBemfUWpT4dk9ynDSB 240kfqTw4y28XM2Bs00Yzak9i6DM6Fn5yhS9L9clS23UhTVPBEGuzgCzX4uh82dN2f/y UtCevM4X4m8mb90gX/DfXrDQIGQ2eY3jlJAlzjU0pMDHFfhW7n8f+jg1tkC/mP/36/5+ vKjg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UYfAoR0R; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:24 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 2/7] i686: Do not raise exception traps on fesetexcept (BZ 30989) Date: Fri, 3 Nov 2023 09:24:11 -0300 Message-Id: <20231103122416.2724355-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. To set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Checked on i686-linux-gnu. --- math/test-fesetexcept-traps.c | 28 ++++++++++++--- sysdeps/i386/fpu/fesetexcept.c | 46 +++++++++++++++++++++--- sysdeps/i386/fpu/math-tests-trap-force.h | 29 +++++++++++++++ sysdeps/x86/fpu/test-fenv-sse-2.c | 23 +++--------- 4 files changed, 100 insertions(+), 26 deletions(-) create mode 100644 sysdeps/i386/fpu/math-tests-trap-force.h diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 96f6c4752f..8a5c0bca80 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -41,8 +42,28 @@ do_test (void) /* Verify fesetexcept does not cause exception traps. For architectures where setting the exception might result in traps the function should - return a nonzero value. */ - ret = fesetexcept (FE_ALL_EXCEPT); + return a nonzero value. + Also check if the function does not alter the exception mask. */ + { + int exc_before = fegetexcept (); + ret = fesetexcept (FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexcept (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); else if (!EXCEPTION_SET_FORCES_TRAP) @@ -61,5 +82,4 @@ do_test (void) return result; } -#define TEST_FUNCTION do_test () -#include "../test-skeleton.c" +#include diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c index 18949e982a..2e9580207c 100644 --- a/sysdeps/i386/fpu/fesetexcept.c +++ b/sysdeps/i386/fpu/fesetexcept.c @@ -17,15 +17,53 @@ . */ #include +#include int fesetexcept (int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. To set a flag, + it is sufficient to do it in the SSE unit, because that is guaranteed to + not trap. However, on i386 CPUs that have only a 387 unit, set the flags + in the 387, as long as this cannot trap. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word |= excepts & FE_ALL_EXCEPT; - __asm__ ("fldenv %0" : : "m" (*&temp)); + excepts &= FE_ALL_EXCEPT; + + if (CPU_FEATURE_USABLE (SSE)) + { + /* And now similarly for SSE. */ + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Set relevant flags. */ + mxcsr |= excepts; + + /* Put the new data in effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + fenv_t temp; + + /* Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); + + /* Set relevant flags. */ + temp.__status_word |= excepts; + + if ((~temp.__control_word) & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C23 (7.6.4.4) does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + } return 0; } diff --git a/sysdeps/i386/fpu/math-tests-trap-force.h b/sysdeps/i386/fpu/math-tests-trap-force.h new file mode 100644 index 0000000000..f41e1ffc2d --- /dev/null +++ b/sysdeps/i386/fpu/math-tests-trap-force.h @@ -0,0 +1,29 @@ +/* Configuration for math tests: support for setting exception flags + without causing enabled traps. i686 version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef I386_FPU_MATH_TESTS_TRAP_FORCE_H +#define I386_FPU_MATH_TESTS_TRAP_FORCE_H 1 + +#include + +/* Setting exception flags in FPU Status Register results in enabled traps for + those exceptions being taken. */ +#define EXCEPTION_SET_FORCES_TRAP !CPU_FEATURE_USABLE (SSE) + +#endif /* math-tests-trap-force.h. */ diff --git a/sysdeps/x86/fpu/test-fenv-sse-2.c b/sysdeps/x86/fpu/test-fenv-sse-2.c index f3e820b6ed..7a0503790f 100644 --- a/sysdeps/x86/fpu/test-fenv-sse-2.c +++ b/sysdeps/x86/fpu/test-fenv-sse-2.c @@ -22,17 +22,8 @@ #include #include #include - -static bool -have_sse2 (void) -{ - unsigned int eax, ebx, ecx, edx; - - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) - return false; - - return (edx & bit_SSE2) != 0; -} +#include +#include static uint32_t get_sse_mxcsr (void) @@ -164,13 +155,9 @@ sse_tests (void) static int do_test (void) { - if (!have_sse2 ()) - { - puts ("CPU does not support SSE2, cannot test"); - return 0; - } + if (!CPU_FEATURE_USABLE (SSE2)) + FAIL_UNSUPPORTED ("CPU does not support SSE2"); return sse_tests (); } -#define TEST_FUNCTION do_test () -#include +#include From patchwork Fri Nov 3 12:24:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 740661 Delivered-To: patch@linaro.org Received: by 2002:a5d:538f:0:b0:32d:baff:b0ca with SMTP id d15csp1335268wrv; Fri, 3 Nov 2023 05:25:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFmH/17Clg0K4Sx2vPWrh/77uG+CKwh7XFkhF0fdDTwEiYejFHdlFLFILKsMETWL70a4oTT X-Received: by 2002:a05:6214:1316:b0:65b:259f:d6a9 with SMTP id pn22-20020a056214131600b0065b259fd6a9mr23072856qvb.7.1699014315886; Fri, 03 Nov 2023 05:25:15 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1699014315; cv=pass; d=google.com; s=arc-20160816; b=Ows74JPP4WghymZ3+7pzb5xc4fDm9TndaLw+PdaUoGt//k99/4Fs9g3LZZR9S/gcPR IHqSF2Expkbz2ihIKWW8aV/lnXQuhFWMGuvz4JkwdmH4cIaseVF79NiIq/4cKttHmfFE Tmi4FBZgkWd/PwKpwTIkR8vyHOJ34XlquMh47m+TYQ7rw7R8/vRMkB2ENAWfu/GPNQb+ iMaKNDwAkQR2C/3B+GcYCm337zl1/Y0tSiW46TKyJk9ze93Yon3FdWvh2zHWo7AANcev 1PatkauuFgw2XqDszh14HhbOCogN37vavXe5t1X7t0bLLA6/z0qSnFvizFm6tLLWyTvy foFg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=eftPKld3emM/oawcIawQye0ZqEe6js4ZoXRzoUmLenU=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=rhAHA2/P9TnIFkd5FrZ6130DccoKc7sQnd41ScA1jjPtS0oWW6L37K6URd/j4o9wVm qoOG+eLTFCc2b9zOuK/rxS9pgY+VgNkV7GwiR3tN87rDOdauw5wBk4qndyoQTEKsrvnB 9FUVNgxbQeSwmvzPw5lYAVbmFILvzKBetaP8YTzvSOoyL5VovYV2b75U59sjDwQSOjey 0S8YPvx8G1TB2tQjivfW8UaDWLUSxWcpX5E4leBm4cdlp7010JBs+95AsiYnC6JTjv96 4fgMcrGRwGFU7CHWLGxbnRtOx7caNb10L6nKVq89Mo78AjziW3Ujl5T6Jk8nI8wDqXAa IcZw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ORXHbVE6; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:27 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 3/7] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Fri, 3 Nov 2023 09:24:12 -0300 Message-Id: <20231103122416.2724355-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella --- math/test-fexcept-traps.c | 22 ++++++++++- sysdeps/i386/fpu/fsetexcptflg.c | 63 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++----- 3 files changed, 77 insertions(+), 32 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..13aff229c3 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -66,7 +67,26 @@ do_test (void) /* The test is that this does not cause exception traps. For architectures where setting the exception might result in traps the function should return a nonzero value. */ - ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + { + int exc_before = fegetexcept (); + ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + int exc_after = fegetexcept (); + if (exc_before != exc_after) + { + puts ("fesetexceptflag (FE_ALL_EXCEPT) changed the exceptions mask"); + return 1; + } + } + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + volatile double a = 1.0; + volatile double b = a + a; + math_force_eval (b); + volatile long double al = 1.0L; + volatile long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..480165cff9 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,63 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. + Note: fnstenv masks all floating-point exceptions until the fldenv + or fldcw below. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + { + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + __asm__ volatile ("fldcw %0" : : "m" (*&temp.__control_word)); + return -1; + } + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */ From patchwork Fri Nov 3 12:24:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 740655 Delivered-To: patch@linaro.org Received: by 2002:a5d:538f:0:b0:32d:baff:b0ca with SMTP id d15csp1334998wrv; Fri, 3 Nov 2023 05:24:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFfLfjKTgC0xl7ToGelEYXzaPZyUgZKFLNOxPNGhM/xAD2gCIM8fKGJBbYoiEZm6idZ/USG X-Received: by 2002:a05:6871:8805:b0:1e9:b496:ce2d with SMTP id te5-20020a056871880500b001e9b496ce2dmr24705555oab.12.1699014278049; Fri, 03 Nov 2023 05:24:38 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1699014278; cv=pass; d=google.com; s=arc-20160816; b=i/BURXKLNjzVOoJUyI8nVmWIzguLfgdukIyUw1I4pQxNCJZYHlehXLR+mMpufwNjC3 1GZIF0FQ4KzAZuWXDiYm5iPli4iZHNMxNjAN6Jbiu91TJ68AR3ZAYl/+Qb/yTUk7Ulwv +7Qg7MbkJSyCCkhb3lJy+wLIy5WqhpNgvfr++HBf5i1n9BWaeX2g17fb1y5CBb9RYuk4 HVXHpBhtuZIKV6eAOxMGTFAiJeOzkQtJm9IoyywEmYbYdif1Aef220RaOndVu2lU8kyS ogVAqPbP0ioHeaGg0NkZzaeXCPU4Ueqlx38aXO6ldXN44XgpVyOm5P6BbWUoHBZF1ULV x2fw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=lk7Ud3IwIA6lCoWuWbkAHIpuAdPuSnUehSUEPHsUfL0=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=oObQm/NSM42m6Zq4TF/l3Y57IzN5S+YletTHsECt+NcLHE7TThDDHiaxIDQzcqIZaS 2mvGoOzdzCP0kw4dpNCqP+00ck6QNIRmxfVwGKXKQdb/l1HwzR4l0V6I0anJwEE4yXVj MMRMLI/vOGYplJ1/Vnc9Lpkg6W/Ex0yJHgsScwEenEQlI/Nw0z5NhKsx8PJcjuBxPrPZ WD+3lRrZjYj3xfeAeGsNap2hNOzfwIiDEDFz2vdV1cwnJrKXHsM4iiqNy5qIFjPCn2XJ jnn1J698zz4JQyIPLrvOw+enG0KXettNTAsIFgFms2JFagJVal5tNYPb9xEWG5dn56yg Gf9w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mk6nnrtl; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:29 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 4/7] manual: Clarify undefined behavior of feenableexcept (BZ 31019) Date: Fri, 3 Nov 2023 09:24:13 -0300 Message-Id: <20231103122416.2724355-5-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible * manual/arith.texi (Control Functions): Explain undefined behavior of feenableexcept in a special case. --- manual/arith.texi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/manual/arith.texi b/manual/arith.texi index fa7110e992..68c6446a5b 100644 --- a/manual/arith.texi +++ b/manual/arith.texi @@ -1176,6 +1176,12 @@ enabled, the status of the other exceptions is not changed. The function returns the previous enabled exceptions in case the operation was successful, @code{-1} otherwise. + +Note: Enabling traps for an exception for which the exception flag is +currently already set (@pxref{Status bit operations}) has undefined +consequences: it may or may not trigger a trap immediately. +@c It triggers a trap immediately on powerpc*, at the next floating- +@c instruction on i386, and not at all on the other CPUs. @end deftypefun @deftypefun int fedisableexcept (int @var{excepts}) From patchwork Fri Nov 3 12:24:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 740658 Delivered-To: patch@linaro.org Received: by 2002:a5d:538f:0:b0:32d:baff:b0ca with SMTP id d15csp1335062wrv; Fri, 3 Nov 2023 05:24:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF7b5/KDtcTcmXkARNt2jHZvOJPOSlHt9CcOnzBEh4gur1SYyh/LFFp8m9W3Sd3eX1/GVdS X-Received: by 2002:a05:6871:590:b0:1e9:8b78:899c with SMTP id u16-20020a056871059000b001e98b78899cmr25714757oan.55.1699014288231; Fri, 03 Nov 2023 05:24:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1699014288; cv=pass; d=google.com; s=arc-20160816; b=PvgfK9G5mYm7tFg9OkOIqaqLED3vqoYq3WFZuhlTiR2ARclrfsX8p/wvBPhk6E7S5T a4i1nUnkEq8RfRz+OeV/PRbA2xAnFAWF4E5cmU0DXlBnQtH4ajfrhlu7xmnSLQlau1gV D/wOICzZfpeqGiOt0ho/P0nTdkPE8gzD4f2W8TwxWSqRyGWZdRz9JiiHoVHxRAHDEAQS iWxKda1zhwP4IAiXugSv0mEbwuychkp4aO1cmMG+Uij/VVKEk6SlnwiohM9fFRfzbryp 3GrF9GyzlTuSwfRKHyBV/hdPUqvqDXL5uyfTJvi7/stUCyI6o7zlpApHarCKULgrPWb2 k+BA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=Fw8OjC8TmSkRlpBI6Ab8Qf0yVbpnIlKkitjWNn3IYh8=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=WDxSYyzZMauC/I7fo3KiSfFhPSvu94+zAXgkCb3zqDgcH2OvH62NZIM8sJAE7zX3y2 yALJse8ZMQVaqx3SrvQ5rrbtKa53wx7iAnpq1olUZz7Lgmb5fG5vv9CvgClxKErjL2/H D+5UwRjAOYnTDn24tI9/DByl7/CBJDIufQay9jifKRtc3HhFslZX2UL47Bq+W/6IZ2sB 4pFsQEYKExGL0NkgFIHnWXpLlQxf+16xq1u2BEuHJPjJjLWGLynatGDRzISWh5wqKScI Ti6Dx6JLfGRSHD6fMQmgwBbSuwm5xxbOHiFJ/DWdi4RikPX20bYFeu0C0xRrbJFxVuTY JVzw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wdvzlQVp; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:31 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 5/7] riscv: Fix feenvupdate with FE_DFL_ENV (BZ 31022) Date: Fri, 3 Nov 2023 09:24:14 -0300 Message-Id: <20231103122416.2724355-6-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org libc_feupdateenv_riscv should check for FE_DFL_ENV, similar to libc_fesetenv_riscv. Also extend the test-fenv.c to test fenvupdate. Checked on riscv under qemu-system. --- math/test-fenv.c | 132 ++++++++++++++++++++++++++++--- sysdeps/riscv/rvf/fenv_private.h | 6 +- 2 files changed, 127 insertions(+), 11 deletions(-) diff --git a/math/test-fenv.c b/math/test-fenv.c index 0af7141ba7..734e0a219d 100644 --- a/math/test-fenv.c +++ b/math/test-fenv.c @@ -196,6 +196,30 @@ set_single_exc (const char *test_name, int fe_exc, fexcept_t exception) feclearexcept (exception); test_exceptions (str, ALL_EXC ^ fe_exc, 0); } + +static void +update_single_exc (const char *test_name, const fenv_t *envp, int fe_exc, + int fe_exc_clear, fexcept_t exception) +{ + char str[200]; + /* The standard allows the inexact exception to be set together with the + underflow and overflow exceptions. So ignore the inexact flag if the + others are raised. */ + int ignore_inexact = (fe_exc & (UNDERFLOW_EXC | OVERFLOW_EXC)) != 0; + + strcpy (str, test_name); + strcat (str, ": set flag, with rest not set"); + feclearexcept (FE_ALL_EXCEPT); + feraiseexcept (exception); + feupdateenv (envp); + test_exceptions (str, fe_exc, ignore_inexact); + + strcpy (str, test_name); + strcat (str, ": clear flag, rest also unset"); + feclearexcept (exception); + feupdateenv (envp); + test_exceptions (str, fe_exc_clear, ignore_inexact); +} #endif static void @@ -233,22 +257,32 @@ fe_tests (void) } #if FE_ALL_EXCEPT +static const char * +funcname (int (*func)(const fenv_t *)) +{ + if (func == fesetenv) + return "fesetenv"; + else if (func == feupdateenv) + return "feupdateenv"; + __builtin_unreachable (); +} + /* Test that program aborts with no masked interrupts */ static void -feenv_nomask_test (const char *flag_name, int fe_exc) +feenv_nomask_test (const char *flag_name, int fe_exc, int (*func)(const fenv_t *)) { # if defined FE_NOMASK_ENV int status; pid_t pid; if (!EXCEPTION_ENABLE_SUPPORTED (FE_ALL_EXCEPT) - && fesetenv (FE_NOMASK_ENV) != 0) + && func (FE_NOMASK_ENV) != 0) { printf ("Test: not testing FE_NOMASK_ENV, it isn't implemented.\n"); return; } - printf ("Test: after fesetenv (FE_NOMASK_ENV) processes will abort\n"); + printf ("Test: after %s (FE_NOMASK_ENV) processes will abort\n", funcname (func)); printf (" when feraiseexcept (%s) is called.\n", flag_name); pid = fork (); if (pid == 0) @@ -295,12 +329,12 @@ feenv_nomask_test (const char *flag_name, int fe_exc) /* Test that program doesn't abort with default environment */ static void -feenv_mask_test (const char *flag_name, int fe_exc) +feenv_mask_test (const char *flag_name, int fe_exc, int (*func)(const fenv_t *)) { int status; pid_t pid; - printf ("Test: after fesetenv (FE_DFL_ENV) processes will not abort\n"); + printf ("Test: after %s (FE_DFL_ENV) processes will not abort\n", funcname (func)); printf (" when feraiseexcept (%s) is called.\n", flag_name); pid = fork (); if (pid == 0) @@ -313,7 +347,7 @@ feenv_mask_test (const char *flag_name, int fe_exc) setrlimit (RLIMIT_CORE, &core_limit); #endif - fesetenv (FE_DFL_ENV); + func (FE_DFL_ENV); feraiseexcept (fe_exc); exit (2); } @@ -615,10 +649,18 @@ feenable_test (const char *flag_name, int fe_exc) static void fe_single_test (const char *flag_name, int fe_exc) { - feenv_nomask_test (flag_name, fe_exc); - feenv_mask_test (flag_name, fe_exc); + feenv_nomask_test (flag_name, fe_exc, fesetenv); + feenv_mask_test (flag_name, fe_exc, fesetenv); feenable_test (flag_name, fe_exc); } + + +static void +feupdate_single_test (const char *flag_name, int fe_exc) +{ + feenv_nomask_test (flag_name, fe_exc, feupdateenv); + feenv_mask_test (flag_name, fe_exc, feupdateenv); +} #endif @@ -646,6 +688,73 @@ feenv_tests (void) fesetenv (FE_DFL_ENV); } +#if FE_ALL_EXCEPT +static void +feupdateenv_single_test (const char *test_name, int fe_exc, + fexcept_t exception) +{ + char str[100]; + fenv_t env; + int res; + + snprintf (str, sizeof str, "feupdateenv %s and FL_DFL_ENV", test_name); + update_single_exc (str, FE_DFL_ENV, fe_exc, NO_EXC, exception); + + feraiseexcept (FE_ALL_EXCEPT); + res = fegetenv (&env); + if (res != 0) + { + printf ("fegetenv failed: %d\n", res); + ++count_errors; + return; + } + + snprintf (str, sizeof str, "feupdateenv %s and FE_ALL_EXCEPT", test_name); + update_single_exc (str, &env, ALL_EXC, ALL_EXC, exception); +} +#endif + +static void +feupdateenv_tests (void) +{ + /* We might have some exceptions still set. */ + feclearexcept (FE_ALL_EXCEPT); + +#ifdef FE_DIVBYZERO + feupdate_single_test ("FE_DIVBYZERO", FE_DIVBYZERO); +#endif +#ifdef FE_INVALID + feupdate_single_test ("FE_INVALID", FE_INVALID); +#endif +#ifdef FE_INEXACT + feupdate_single_test ("FE_INEXACT", FE_INEXACT); +#endif +#ifdef FE_UNDERFLOW + feupdate_single_test ("FE_UNDERFLOW", FE_UNDERFLOW); +#endif +#ifdef FE_OVERFLOW + feupdate_single_test ("FE_OVERFLOW", FE_OVERFLOW); +#endif + +#ifdef FE_DIVBYZERO + feupdateenv_single_test ("DIVBYZERO", DIVBYZERO_EXC, FE_DIVBYZERO); +#endif +#ifdef FE_INVALID + feupdateenv_single_test ("INVALID", INVALID_EXC, FE_INVALID); +#endif +#ifdef FE_INEXACT + feupdateenv_single_test ("INEXACT", INEXACT_EXC, FE_INEXACT); +#endif +#ifdef FE_UNDERFLOW + feupdateenv_single_test ("UNDERFLOW", UNDERFLOW_EXC, FE_UNDERFLOW); +#endif +#ifdef FE_OVERFLOW + feupdateenv_single_test ("OVERFLOW", OVERFLOW_EXC, FE_OVERFLOW); +#endif + + feupdateenv (FE_DFL_ENV); +} + static void feholdexcept_tests (void) @@ -766,13 +875,14 @@ initial_tests (void) #endif } -int -main (void) +static int +do_test (void) { initial_tests (); fe_tests (); feenv_tests (); feholdexcept_tests (); + feupdateenv_tests (); if (count_errors) { @@ -782,3 +892,5 @@ main (void) printf ("\n All tests passed successfully.\n"); return 0; } + +#include diff --git a/sysdeps/riscv/rvf/fenv_private.h b/sysdeps/riscv/rvf/fenv_private.h index 40e23661b7..c91d871160 100644 --- a/sysdeps/riscv/rvf/fenv_private.h +++ b/sysdeps/riscv/rvf/fenv_private.h @@ -123,7 +123,11 @@ libc_feupdateenv_test_riscv (const fenv_t *envp, int ex) static __always_inline void libc_feupdateenv_riscv (const fenv_t *envp) { - _FPU_SETCW (*envp | riscv_getflags ()); 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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:32 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 6/7] alpha: Fix fesetexceptflag (BZ 30998) Date: Fri, 3 Nov 2023 09:24:15 -0300 Message-Id: <20231103122416.2724355-7-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible It clears some exception flags that are outside the EXCEPTS argument. It fixes math/test-fexcept on qemu-user. --- sysdeps/alpha/fpu/fsetexcptflg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/alpha/fpu/fsetexcptflg.c b/sysdeps/alpha/fpu/fsetexcptflg.c index 70f3666a6e..63eb06845d 100644 --- a/sysdeps/alpha/fpu/fsetexcptflg.c +++ b/sysdeps/alpha/fpu/fsetexcptflg.c @@ -27,7 +27,7 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) tmp = __ieee_get_fp_control (); /* Set all the bits that were called for. */ - tmp = (tmp & ~SWCR_STATUS_MASK) | (*flagp & excepts & SWCR_STATUS_MASK); + tmp ^= (tmp ^ *flagp) & excepts & SWCR_STATUS_MASK; /* And store it back. */ __ieee_set_fp_control (tmp); From patchwork Fri Nov 3 12:24:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 740660 Delivered-To: patch@linaro.org Received: by 2002:a5d:538f:0:b0:32d:baff:b0ca with SMTP id d15csp1335250wrv; Fri, 3 Nov 2023 05:25:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE/dX+4lGEJz8rRErRdh0YAWtHplso+rCMZXHGtn+3BwcdJqOEpWWYfTFRtLdChDXJy8eB9 X-Received: by 2002:a05:6870:12d0:b0:1e9:b599:1aab with SMTP id 16-20020a05687012d000b001e9b5991aabmr20671511oam.58.1699014313531; Fri, 03 Nov 2023 05:25:13 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1699014313; cv=pass; d=google.com; s=arc-20160816; b=G/VmQBVA/XijT98OAcMGWRRww/Cc3yc+i2VFb4Fa5i6GBCFYpZXDH2+hxMbh5ciL9p aYjvwmi2oY76NRWE+M9uGGfjJ/XHqZVbMTMLYtzuX5iF3Y4haGsCXVyKdEFZ90H4/V2A 1jJD0jGroT43Xw6WmVcW00KdvMi3t7SH0fqE2uG9Jr+AXxFv2ubAbGPsGk58/Jkxbfnu yBaTgePQbN5Fzv4Wipzn7Z2FbMtGwHhhyAGVNPygvmwgQC/1xXSSUTb7nokONziN7i0N qU7uIJPlC857Rvj7yeAovF+mL4gLj8+zbKz4r2rD/nhaIP9hTLnnbW/dHv5Utn0Xovjs vgog== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=6jWpJtYgU4AupWiGBpR3CkeP70iQINh300sZdk4guoA=; fh=01HD8dtuIqmy9rV/eMJuvD8dAGq4TXBqBjIxWaMzNQI=; b=HdSz9T8ktuiYpylTW0LGi9wiXIPSNoshRMHpY/YPRvrVVvLusBe/ab4poks/DbAUQU JcKq7aOXCo58vzblKCG5+xlJn2p/ywRWnvXmLjQRNG6WRhZ947vacET62fr8gf/wcv5X g90VtliRYJAr7mXYA1ZVzDewbjuGMSbpE5yAhCn4Jg2Bj6rxKzumEBHuTOUHKzuQBACk YtN2pyQmgqT4AIHMsDSWK4+OXvvb2gX9p5A7ZuwP75Y5ntGcaGRMWiiGBehf7m3xc7Mo uXTdlhCG78VyXGhI5+Z5qEgXADnSHfA7CtrnO7/Vs3jDxfH8Bkx72frfGHbhC208PHnI iAtA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Doipox+/"; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:34 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 7/7] hppa: Fix undefined behaviour in feclearexcept (BZ 30983) Date: Fri, 3 Nov 2023 09:24:16 -0300 Message-Id: <20231103122416.2724355-8-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible The expression (excepts & FE_ALL_EXCEPT) << 27 produces a signed integer overflow when 'excepts' is specified as FE_INVALID (= 0x10), because - excepts is of type 'int', - FE_ALL_EXCEPT is of type 'int', - thus (excepts & FE_ALL_EXCEPT) is (int) 0x10, - 'int' is 32 bits wide. The patched code produces the same instruction sequence as previosuly. --- sysdeps/hppa/fpu/fclrexcpt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/hppa/fpu/fclrexcpt.c b/sysdeps/hppa/fpu/fclrexcpt.c index 055fb04ccc..46caf39ec1 100644 --- a/sysdeps/hppa/fpu/fclrexcpt.c +++ b/sysdeps/hppa/fpu/fclrexcpt.c @@ -26,7 +26,7 @@ feclearexcept (int excepts) /* Get the current status word. */ __asm__ ("fstd %%fr0,0(%1)" : "=m" (s.l) : "r" (&s.l) : "%r0"); /* Clear all the relevant bits. */ - s.sw[0] &= ~((excepts & FE_ALL_EXCEPT) << 27); + s.sw[0] &= ~(((unsigned int) excepts & FE_ALL_EXCEPT) << 27); __asm__ ("fldd 0(%0),%%fr0" : : "r" (&s.l), "m" (s.l) : "%r0"); /* Success. */