From patchwork Thu Nov 2 19:37:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Wolsieffer X-Patchwork-Id: 740529 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37B01154A6 for ; Thu, 2 Nov 2023 19:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=hefring-com.20230601.gappssmtp.com header.i=@hefring-com.20230601.gappssmtp.com header.b="SyQSTv1c" Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3CE8112 for ; Thu, 2 Nov 2023 12:38:00 -0700 (PDT) Received: by mail-qv1-xf30.google.com with SMTP id 6a1803df08f44-66fbcaf03c6so8280426d6.1 for ; Thu, 02 Nov 2023 12:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hefring-com.20230601.gappssmtp.com; s=20230601; t=1698953880; x=1699558680; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SCGqKJF6SsDfNrHHzhtnH0GPRPMyo2Rte78iygg6g5o=; b=SyQSTv1cpqUZxlzsFKaAKcrDnscDpuZQY1PNfllvM1VDZaY1okXF2H2wggWlQ8jc6m wm7kVdtCgW6/rJKe9LSy2hwCpePcRf7Wtq4h7WtU4sei6PcgvEBtGZvNFHQfZPGd6TEM mxEdswX0CMvtAoK+VNNU1dyw8KkoifWft/d/WKWRrTGVfNeWNS9PQBFj02qDbxvT8WlK RplLoQog6OIGqDq26A1uQ/jvLoO8FhvKeGeDzPIhfnRuDwXi60W+kMFtNSadxHoy59Nm IeiWWvlSFf92/qiRodCrU0Hm8Pf0CqfJq9FA3JShki92BjIYw6ajcbp7BsjDb6LsPbP3 fIFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698953880; x=1699558680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SCGqKJF6SsDfNrHHzhtnH0GPRPMyo2Rte78iygg6g5o=; b=dUzagf9UStCGUIjIYvF9bu+11+L7S5o781vamXdxrybs1GL6gsVO9kwevW7T7Yhaoa mbG/qjRoBFTI3U9Tg3BKeRwoKgB8pnkc/0F3dGppENs5QQT5wIltUjozE/Wkc6fNsyEM x0/01wohk+hQ2+uiO4NZF69nf0RxwI52ygyIM/ARBlxBTbeOLmtXsQu+7yHB631Rd35h iY5RknsmINp0Zj1PgwK3fit2u0JpQ8vRbI0+MhJzCTm503mIYMUPeZPmTD+A4bRrzWuU uRv8pOUJc9GqolTQc4wj2SeJhpsyT+GTlPoYsIFMjKuQjVzLMpXe/GIHB+eWaSjX1MoY e9vg== X-Gm-Message-State: AOJu0Yxpcp/4C6m9cC/G57vRkMKOx9xjQ8vzMyzicVNoR5AvCWCEtuhD F1pwITFglEIe1QZWGKWoznYmMA== X-Google-Smtp-Source: AGHT+IEtm34TPaGi4W7uKrej4zTnLABaepScjmhEkv/rbDHqn1aFt5BdoRmSlKa4eiA5zKkmAT22Qw== X-Received: by 2002:a05:6214:76e:b0:66d:3716:4e11 with SMTP id f14-20020a056214076e00b0066d37164e11mr26916465qvz.38.1698953879859; Thu, 02 Nov 2023 12:37:59 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce90a000000b0065b260eafd9sm30654qvo.87.2023.11.02.12.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 12:37:59 -0700 (PDT) From: Ben Wolsieffer To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Alain Volmat , Erwan Leray , Fabrice Gasnier , Ben Wolsieffer Subject: [PATCH v2 2/5] spi: stm32: use callbacks for read_rx and write_tx Date: Thu, 2 Nov 2023 15:37:19 -0400 Message-ID: <20231102193722.3042245-3-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> References: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The STM32F7 will require different read and write routines, so make these functions into configurable callbacks. Signed-off-by: Ben Wolsieffer --- drivers/spi/spi-stm32.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 02d1409d7229..427788d18532 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -229,6 +229,8 @@ struct stm32_spi; * time between frames (if driver has this functionality) * @set_number_of_data: optional routine to configure registers to desired * number of data (if driver has this functionality) + * @write_tx: routine to write to transmit register/FIFO + * @read_rx: routine to read from receive register/FIFO * @transfer_one_dma_start: routine to start transfer a single spi_transfer * using DMA * @dma_rx_cb: routine to call after DMA RX channel operation is complete @@ -252,6 +254,8 @@ struct stm32_spi_cfg { int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type); void (*set_data_idleness)(struct stm32_spi *spi, u32 length); int (*set_number_of_data)(struct stm32_spi *spi, u32 length); + void (*write_tx)(struct stm32_spi *spi); + void (*read_rx)(struct stm32_spi *spi); void (*transfer_one_dma_start)(struct stm32_spi *spi); void (*dma_rx_cb)(void *data); void (*dma_tx_cb)(void *data); @@ -822,17 +826,17 @@ static irqreturn_t stm32fx_spi_irq_event(int irq, void *dev_id) if (sr & STM32FX_SPI_SR_TXE) { if (spi->tx_buf) - stm32f4_spi_write_tx(spi); + spi->cfg->write_tx(spi); if (spi->tx_len == 0) end = true; } if (sr & STM32FX_SPI_SR_RXNE) { - stm32f4_spi_read_rx(spi); + spi->cfg->read_rx(spi); if (spi->rx_len == 0) end = true; else if (spi->tx_buf)/* Load data for discontinuous mode */ - stm32f4_spi_write_tx(spi); + spi->cfg->write_tx(spi); } end_irq: @@ -1149,7 +1153,7 @@ static int stm32fx_spi_transfer_one_irq(struct stm32_spi *spi) /* starting data transfer when buffer is loaded */ if (spi->tx_buf) - stm32f4_spi_write_tx(spi); + spi->cfg->write_tx(spi); spin_unlock_irqrestore(&spi->lock, flags); @@ -1752,6 +1756,8 @@ static const struct stm32_spi_cfg stm32f4_spi_cfg = { .config = stm32fx_spi_config, .set_bpw = stm32f4_spi_set_bpw, .set_mode = stm32fx_spi_set_mode, + .write_tx = stm32f4_spi_write_tx, + .read_rx = stm32f4_spi_read_rx, .transfer_one_dma_start = stm32fx_spi_transfer_one_dma_start, .dma_tx_cb = stm32fx_spi_dma_tx_cb, .dma_rx_cb = stm32_spi_dma_rx_cb, @@ -1775,6 +1781,8 @@ static const struct stm32_spi_cfg stm32h7_spi_cfg = { .set_mode = stm32h7_spi_set_mode, .set_data_idleness = stm32h7_spi_data_idleness, .set_number_of_data = stm32h7_spi_number_of_data, + .write_tx = stm32h7_spi_write_txfifo, + .read_rx = stm32h7_spi_read_rxfifo, .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start, .dma_rx_cb = stm32_spi_dma_rx_cb, /* From patchwork Thu Nov 2 19:37:20 2023 Content-Type: text/plain; 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Thu, 02 Nov 2023 12:38:01 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce90a000000b0065b260eafd9sm30654qvo.87.2023.11.02.12.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 12:38:00 -0700 (PDT) From: Ben Wolsieffer To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Alain Volmat , Erwan Leray , Fabrice Gasnier , Ben Wolsieffer Subject: [PATCH v2 3/5] dt-bindings: spi: add stm32f7-spi compatible Date: Thu, 2 Nov 2023 15:37:20 -0400 Message-ID: <20231102193722.3042245-4-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> References: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the only significant differences being support for a wider range of word sizes and the addition of 32-bit transmit and receive FIFOs. Signed-off-by: Ben Wolsieffer Acked-by: Conor Dooley --- Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index ae0f082bd377..5754d603f34f 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - st,stm32f4-spi + - st,stm32f7-spi - st,stm32h7-spi reg: From patchwork Thu Nov 2 19:37:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Wolsieffer X-Patchwork-Id: 740527 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D91A2136C for ; Thu, 2 Nov 2023 19:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=hefring-com.20230601.gappssmtp.com header.i=@hefring-com.20230601.gappssmtp.com header.b="s+3Wx9al" Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 040F81A8 for ; Thu, 2 Nov 2023 12:38:05 -0700 (PDT) Received: by mail-qk1-x72d.google.com with SMTP id af79cd13be357-778711ee748so80229285a.2 for ; Thu, 02 Nov 2023 12:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hefring-com.20230601.gappssmtp.com; s=20230601; t=1698953884; x=1699558684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6aaUx3IM/nYfDKWStA9Ff2X3zBWfKwgpoaBzpBVRw5U=; b=s+3Wx9alGYL3B6GcYlddhun4+VOnzPxSWOLIyS4a5d+mbApD14DHl2S82/O5bKKFF2 LJrZPN+asfbs9NbxGqjaT2o1y0CDyHTqaLOtHpbZ7bhBTjIazanOUWyqQzxhDfRymnh2 uA5RbeKN/nxnYRYqr43b2SthVRGvOSySh05T14r1RmCHlvJWzo7W6n4rL8+lhF+JGXG5 WLJP6mbcupipsbwIZ96Ez4ctnk8GKEYnS8+64/jT9VKhOkKtASTxWt3H14b/YgypWCHx rgBB5+nDF2Vyw2QrQlA38MmVWNWqQPk1tyz8Ok+/c0HEAUrYxRoDqmZgiKbjYyPllP68 SRlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698953884; x=1699558684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6aaUx3IM/nYfDKWStA9Ff2X3zBWfKwgpoaBzpBVRw5U=; b=QqlKTH0lTZHzvoYkTOfEaEwUmNNbvWP0xx4mvQEcrC6rPulEhsH8MprnpBjIueB8g9 zrYMsumJaofNg4iJra6GVRTRZKmPtcx+UKcbJJmG6x5Q2fg2rj9X/NRXQZFOYuPhrePD tIKkSxkd+2vOXA0LPwXBjxipvFlaZNZFOjFa9+yxNFDEYBmslvhOEdUQYA8L+yq+Chol nYiLPtUcY8iMIozI6KiYzlt84mCTBkUaxhzs7qAPuz3vWGTD9z4+FRDxiGCosj6tFeNs SCLRKAAn8TEQcpuCvIqyaOJg9g2Bk8MEQSy5ls4/zrHVD/oTMvZ9E9ejH7A8wPRxu7Md 5WNQ== X-Gm-Message-State: AOJu0YwNHOMDxQG857NVrpZiDqg5q3BFd9fxhbfXMu1/lG9YdjBMuf8h svxXEo33RIt//6My4mVIx/zTHA== X-Google-Smtp-Source: AGHT+IGl1n2G2oeUX/4FgvKTLXfhf+P6aEP1OM//x0r4Ln54rPG+Aie8qOEQgGDLVsNuD/9Gag0UxA== X-Received: by 2002:a05:6214:2688:b0:66d:9f40:4792 with SMTP id gm8-20020a056214268800b0066d9f404792mr26366649qvb.26.1698953884213; Thu, 02 Nov 2023 12:38:04 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce90a000000b0065b260eafd9sm30654qvo.87.2023.11.02.12.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 12:38:03 -0700 (PDT) From: Ben Wolsieffer To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Alain Volmat , Erwan Leray , Fabrice Gasnier , Ben Wolsieffer Subject: [PATCH v2 5/5] ARM: dts: stm32: add SPI support on STM32F746 Date: Thu, 2 Nov 2023 15:37:22 -0400 Message-ID: <20231102193722.3042245-6-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> References: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add device tree nodes for the STM32F746 SPI controllers. Signed-off-by: Ben Wolsieffer --- arch/arm/boot/dts/st/stm32f746.dtsi | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 53a8e2dec9a4..14ba51f2a13d 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -274,6 +274,26 @@ gcan3: gcan@40003600 { clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; }; + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f7-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f7-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; @@ -491,6 +511,26 @@ sdio1: mmc@40012c00 { status = "disabled"; }; + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f7-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f7-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>; + status = "disabled"; + }; + syscfg: syscon@40013800 { compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; @@ -554,6 +594,26 @@ pwm { }; }; + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f7-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>; + status = "disabled"; + }; + + spi6: spi@40015400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f7-spi"; + reg = <0x40015400 0x400>; + interrupts = <86>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>; + status = "disabled"; + }; + ltdc: display-controller@40016800 { compatible = "st,stm32-ltdc"; reg = <0x40016800 0x200>;