From patchwork Tue Oct 31 04:41:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 740149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AFE4C00144 for ; Tue, 31 Oct 2023 04:41:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236847AbjJaElu (ORCPT ); Tue, 31 Oct 2023 00:41:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235985AbjJaElt (ORCPT ); Tue, 31 Oct 2023 00:41:49 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7852BAB; Mon, 30 Oct 2023 21:41:47 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39V3t2c0023171; Tue, 31 Oct 2023 04:41:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=TOCkHJNrOksobYLQlF9muMNfMgj/S5y18S5DUul4xvI=; b=PoepuOgrCnkyjQzIKYWrH4DxWsXyaDCx3XIpu2fX1c/cVyu4KVxckvJPc47nEyTtXMXl UI1YwEPXp4yVonsGyYWd+uzvPTkVGphS/oIKCD4+3xYz6/0VPi+SYr7GDf8rWoiG1d2s RmspWBuOBnb6Wt+zFOIN9HgJRdVfjiI8i4c3dydQpReeUDXOiK8b/43Nzk0A3wcDjLpP J4eiD/iHTm2BlB88p7JwEgMWA/CXMBXNYndBkUuMf61SYmw01RqvxG8wAI2QW4ZqwPEt /Fr3Zw2om2rBKEaDrDL/HzcvNQGsYFI8GDh1K0F48KKLYwCpfOqHNmcqz8zbF+Kf0rkK pQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u2chyhv05-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Oct 2023 04:41:16 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V4fCTu012165; Tue, 31 Oct 2023 04:41:12 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0uckttac-1; Tue, 31 Oct 2023 04:41:12 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V4fCwK012159; Tue, 31 Oct 2023 04:41:12 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V4fC9L012156; Tue, 31 Oct 2023 04:41:12 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 5951E450D; Tue, 31 Oct 2023 10:11:11 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v5 1/4] dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC Date: Tue, 31 Oct 2023 10:11:03 +0530 Message-Id: <1698727267-22131-2-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> References: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rreVNBBzGuPUzn9uiWsSkrafxmcThcob X-Proofpoint-GUID: rreVNBBzGuPUzn9uiWsSkrafxmcThcob X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 mlxlogscore=967 spamscore=0 phishscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree bindings support for SA8775P SoC. It has DMA register space and dma interrupt to support HDMA. Signed-off-by: Mrinmay Sarkar --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 64 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index a223ce0..46802f7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - qcom,sa8775p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -20,6 +21,7 @@ properties: - const: qcom,sdx55-pcie-ep reg: + minItems: 6 items: - description: Qualcomm-specific PARF configuration registers - description: DesignWare PCIe registers @@ -27,8 +29,10 @@ properties: - description: Address Translation Unit (ATU) registers - description: Memory region used to map remote RC address space - description: BAR memory region + - description: DMA register space reg-names: + minItems: 6 items: - const: parf - const: dbi @@ -36,13 +40,14 @@ properties: - const: atu - const: addr_space - const: mmio + - const: dma clocks: - minItems: 7 + minItems: 5 maxItems: 8 clock-names: - minItems: 7 + minItems: 5 maxItems: 8 qcom,perst-regs: @@ -57,14 +62,18 @@ properties: - description: Perst separation enable offset interrupts: + minItems: 2 items: - description: PCIe Global interrupt - description: PCIe Doorbell interrupt + - description: DMA interrupt interrupt-names: + minItems: 2 items: - const: global - const: doorbell + - const: dma reset-gpios: description: GPIO used as PERST# input signal @@ -125,6 +134,10 @@ allOf: - qcom,sdx55-pcie-ep then: properties: + reg: + maxItems: 6 + reg-names: + maxItems: 6 clocks: items: - description: PCIe Auxiliary clock @@ -143,6 +156,10 @@ allOf: - const: slave_q2a - const: sleep - const: ref + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 - if: properties: @@ -152,6 +169,10 @@ allOf: - qcom,sm8450-pcie-ep then: properties: + reg: + maxItems: 6 + reg-names: + maxItems: 6 clocks: items: - description: PCIe Auxiliary clock @@ -172,6 +193,45 @@ allOf: - const: ref - const: ddrss_sf_tbu - const: aggre_noc_axi + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-pcie-ep + then: + properties: + reg: + minItems: 7 + maxItems: 7 + reg-names: + minItems: 7 + maxItems: 7 + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + interrupts: + minItems: 3 + maxItems: 3 + interrupt-names: + minItems: 3 + maxItems: 3 unevaluatedProperties: false From patchwork Tue Oct 31 04:41:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 739653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FA1BC00A5A for ; Tue, 31 Oct 2023 04:41:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236864AbjJaEly (ORCPT ); Tue, 31 Oct 2023 00:41:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236853AbjJaElv (ORCPT ); Tue, 31 Oct 2023 00:41:51 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94BCD98; Mon, 30 Oct 2023 21:41:49 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39V3g4Dm008494; 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Tue, 31 Oct 2023 04:41:13 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0uckttak-1; Tue, 31 Oct 2023 04:41:13 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V4fDA2012177; Tue, 31 Oct 2023 04:41:13 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V4fD4q012170; Tue, 31 Oct 2023 04:41:13 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 738E1449C; Tue, 31 Oct 2023 10:11:12 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v5 2/4] PCI: qcom-ep: Add support for SA8775P SOC Date: Tue, 31 Oct 2023 10:11:04 +0530 Message-Id: <1698727267-22131-3-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> References: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UDrGqFzCAqJnLxj-IsDxTCrzzOT_-M08 X-Proofpoint-ORIG-GUID: UDrGqFzCAqJnLxj-IsDxTCrzzOT_-M08 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 mlxlogscore=984 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller driver. Adding new compatible string as it has different set of clocks compare to other SOCs. Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 9e58f05..3a53d97 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -875,6 +875,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) } static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,sa8775p-pcie-ep", }, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } From patchwork Tue Oct 31 04:41:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 740148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABAD6C001DB for ; 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Tue, 31 Oct 2023 04:41:18 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V4fFDZ012514; Tue, 31 Oct 2023 04:41:15 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0uckttar-1; Tue, 31 Oct 2023 04:41:15 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V4fDA4012177; Tue, 31 Oct 2023 04:41:15 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V4fD4s012170; Tue, 31 Oct 2023 04:41:15 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 974FE450D; Tue, 31 Oct 2023 10:11:13 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v5 3/4] PCI: epf-mhi: Add support for SA8775P Date: Tue, 31 Oct 2023 10:11:05 +0530 Message-Id: <1698727267-22131-4-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> References: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fykdWSbqEQWeGox37bOaKPVnVGfc-we2 X-Proofpoint-ORIG-GUID: fykdWSbqEQWeGox37bOaKPVnVGfc-we2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 mlxlogscore=653 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver. Reusing DID (0x0306) for SA8775P and it supports HDMA. Currently, it has no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". Signed-off-by: Mrinmay Sarkar --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index b7b9d3e..23ea94e 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -114,6 +114,22 @@ static const struct pci_epf_mhi_ep_info sm8450_info = { .flags = MHI_EPF_USE_DMA, }; +static struct pci_epf_header sa8775p_header = { + .vendorid = PCI_VENDOR_ID_QCOM, + .deviceid = 0x0306, /* FIXME: Update deviceid for sa8775p EP */ + .baseclass_code = PCI_CLASS_OTHERS, + .interrupt_pin = PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sa8775p_info = { + .config = &mhi_v1_config, + .epf_header = &sa8775p_header, + .bar_num = BAR_0, + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count = 32, + .mru = 0x8000, +}; + struct pci_epf_mhi { const struct pci_epc_features *epc_features; const struct pci_epf_mhi_ep_info *info; @@ -677,6 +693,7 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, } static const struct pci_epf_device_id pci_epf_mhi_ids[] = { + { .name = "sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info }, { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info }, { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info }, {}, From patchwork Tue Oct 31 04:41:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 739654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08976C001B5 for ; Tue, 31 Oct 2023 04:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjJaElv (ORCPT ); Tue, 31 Oct 2023 00:41:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235989AbjJaElu (ORCPT ); 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Tue, 31 Oct 2023 04:41:19 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V4fCTv012165; Tue, 31 Oct 2023 04:41:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0uckttaw-1; Tue, 31 Oct 2023 04:41:16 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V4fDA6012177; Tue, 31 Oct 2023 04:41:16 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V4fD4u012170; Tue, 31 Oct 2023 04:41:16 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id E7CDD449C; Tue, 31 Oct 2023 10:11:14 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v5 4/4] arm64: dts: qcom: sa8775p: Add ep pcie0 controller node Date: Tue, 31 Oct 2023 10:11:06 +0530 Message-Id: <1698727267-22131-5-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> References: <1698727267-22131-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7bjdhfygAblCPrZSj_RQ1yYrKCUA08xe X-Proofpoint-ORIG-GUID: 7bjdhfygAblCPrZSj_RQ1yYrKCUA08xe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by: Mrinmay Sarkar --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 13dd44d..7eab458 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3586,6 +3586,52 @@ status = "disabled"; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>;