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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a5d5950000000b0032f7d1e2c7csm5912914wri.95.2023.10.30.10.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 10:40:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Enable FEAT_MOPS insns in user-mode emulation Date: Mon, 30 Oct 2023 17:39:58 +0000 Message-Id: <20231030174000.3792225-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030174000.3792225-1-peter.maydell@linaro.org> References: <20231030174000.3792225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In user-mode emulation, we need to set the SCTLR_EL1.MSCEn bit to avoid all the FEAT_MOPS insns UNDEFing. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index aa4e006f21a..cdb37ce5512 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -295,6 +295,8 @@ static void arm_cpu_reset_hold(Object *obj) env->cp15.sctlr_el[1] |= SCTLR_TSCXT; /* Disable access to Debug Communication Channel (DCC). */ env->cp15.mdscr_el1 |= 1 << 12; + /* Enable FEAT_MOPS */ + env->cp15.sctlr_el[1] |= SCTLR_MSCEN; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { From patchwork Mon Oct 30 17:39:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 739270 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c47:0:b0:32d:baff:b0ca with SMTP id n7csp1251215wrt; Mon, 30 Oct 2023 10:41:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGtoPy5W8Iil40cY/2gPrnjGKyaR+2YMQOKspB7rJoUs2HjZxe8yUXuJn9oCpztgnZwgR7c X-Received: by 2002:a05:620a:1d05:b0:779:dd50:2dbd with SMTP id dl5-20020a05620a1d0500b00779dd502dbdmr10089374qkb.29.1698687701374; Mon, 30 Oct 2023 10:41:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698687701; cv=none; d=google.com; s=arc-20160816; b=uvTvoP5rZ6lxTh+xCU9nb1GYCsIbt2p+9eurkJrkTjqFBKhMQV0UA+EsdL/vbfaCxu 9oEkB2wqWBIvZcEjBjun1kLdPJbSMwHx9mORK7LPbJlczgcDCCQ2Xqgl6SNSn8TLH7sq 6BiQWT5yaS1M+Uhscx6oJMoSaUSlbe8Ih782xCE3/KJwGf7vpHNW8dw+aywqRkplTu17 EfC5w9g9NVaRsK4TpU4PbdFB0WcoES6sPPff053eknNCEN4b3qaPC7D82tsIlduId5HH S54ptlRis01CUcNOTLUb9Gt/1W9d1ZJThn/YyojiNZ7nz2XWcYKB9WJN+kx1lQ34Qv5t s+bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8ZNFOWWtLsTPgYHbvU45OdcAlg5gVb5D/Mp59sG/PFg=; fh=H2AmuqulvQE+T5zu97MCEUC3z9wF9NssS7895NhR/+c=; b=oikVbDgBQYDK22KbX+FYo1q2gSa91k3me0xzVKKXTIJftnzaNeN8JpHl7lTEJ+LSV7 BFQAN8Rhbgy5+0dWLQTAoozLqXaPKIgyZ4ebIoSPBH3x0TFjmyWFqs2F6SbKO+2Hiequ Dbk9LLUDFmCjEnbn79ZZwRqZjLTKHWdZcSahmOItIrpsEio7bFmNy9XcdOQ+Xu578Xov D6wY62uL8cbK0a8b2aZI0bKPvHOfLjYGCg7pbURW9fHeKZXzYJm+N8pzy6xpdjIFDFRQ iv3MXkLj/ii1Ex0F6bOmPkF8sdXsPwoELK91lDYZqL1s//aDYJ3l7uu5aJ085kIIDWLm mqkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=muzNiCZk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a5d5950000000b0032f7d1e2c7csm5912914wri.95.2023.10.30.10.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 10:40:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/3] linux-user: Report AArch64 hwcap2 fields above bit 31 Date: Mon, 30 Oct 2023 17:39:59 +0000 Message-Id: <20231030174000.3792225-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030174000.3792225-1-peter.maydell@linaro.org> References: <20231030174000.3792225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The AArch64 ELF hwcap2 field is 64 bits, but our get_elf_hwcap2() works with uint32_t, so it accidentally fails to report any hwcaps over bit 31. Use uint64_t here. The Arm hwcap2 is only 32 bits (because the ELF format makes these fields be the size of "long" in the ABI), but since it shares the prototype declaration for get_elf_hwcap2() it is easier to also expand it to 64 bits. The only hwcap fields we implement already that are affected by this are the HBC and MOPS ones, neither of which were implemented in a previous release, so this doesn't need backporting to older stable branches. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- linux-user/loader.h | 2 +- linux-user/elfload.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/linux-user/loader.h b/linux-user/loader.h index 324e5c872af..9be00da40a4 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -61,7 +61,7 @@ uint32_t get_elf_hwcap(void); const char *elf_hwcap_str(uint32_t bit); #endif #if defined(TARGET_AARCH64) || defined(TARGET_ARM) -uint32_t get_elf_hwcap2(void); +uint64_t get_elf_hwcap2(void); const char *elf_hwcap2_str(uint32_t bit); #endif diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2e3809f03c4..6fb44206fab 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -520,10 +520,10 @@ uint32_t get_elf_hwcap(void) return hwcaps; } -uint32_t get_elf_hwcap2(void) +uint64_t get_elf_hwcap2(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); - uint32_t hwcaps = 0; + uint64_t hwcaps = 0; GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES); GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL); @@ -784,10 +784,10 @@ uint32_t get_elf_hwcap(void) return hwcaps; } -uint32_t get_elf_hwcap2(void) +uint64_t get_elf_hwcap2(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); - uint32_t hwcaps = 0; + uint64_t hwcaps = 0; GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); From patchwork Mon Oct 30 17:40:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 739267 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c47:0:b0:32d:baff:b0ca with SMTP id n7csp1250774wrt; Mon, 30 Oct 2023 10:40:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHbIO8AM1ABy2r+nOcEYj/1QS3NgP356mMfSxWSklsGxNb2iwtMy/DkszLVG/HiHiSNPmRU X-Received: by 2002:a05:6214:19ef:b0:670:8d2d:e5ce with SMTP id q15-20020a05621419ef00b006708d2de5cemr8918766qvc.62.1698687649477; Mon, 30 Oct 2023 10:40:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698687649; cv=none; d=google.com; s=arc-20160816; b=yvEbyA6nuiYTRpJ3fBwZ6d1zoN2jM03twLOs2DeQoINoF8H8iuvvJc8I+XyTiDpPKy EYUBr6TkwVFjoTCnGOOZlk5STLe5NUQdX+ANHW58CJ0GNH/+kZSCSqlkZuiCkMSjQBph zHCqelcx8x8G8BMPEcHBTSP5GzAqV1wqBW+rNkzPvWl4MHCN53aDOoabOui15D5lik84 k04yu/Nue4rcppzqfL9ehKWxrmpUXj3ypO6rzDDfUAmFIrDqTVk+2ZXwu+NajpHi5rIL 37PCinwg4DoSCfEIEPsYtFIpx1yekCxcetqCfzNcssleTyyzzL3MiRVck/ZTnp6ABxTj fUMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WqVvp3csTiPZFAuQuKekKYsYC9+/xgQvvKPTLe74R7I=; fh=H2AmuqulvQE+T5zu97MCEUC3z9wF9NssS7895NhR/+c=; b=KBaZ3DpzfO6zUOD9GGCwtcFI+uGMPGZlR8GbRlN7bf1fbfXzS4/MYXx7VERcQNNKwR ep9Gi9NE/lOfVJAT0ANs8flzbE7I0e1lZQVEJhzIFp/obOT6HNfgQnXzLWyMvYGjfTqY ltyRLECmVgK2XQ2y5sMXWE2YvDtCi+jDxDFTOYzXjWPDNtCa0TkYwZTHkoo5aNJaU/v/ u9B9D9Rjv1viu988ZtsN9oZQxREIK2esiJyRpeeNz/0CbPPaOwSLzUGe2WdlKg4AeUiA gOSwzh1Gjq6i5xcOKexjINSKF/AhzbIo+Udnj9ojoBNeBht69jVMZduv594K1ktjeocP 914w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XlKyM7t6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a5d5950000000b0032f7d1e2c7csm5912914wri.95.2023.10.30.10.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 10:40:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Make FEAT_MOPS SET* insns handle Xs == XZR correctly Date: Mon, 30 Oct 2023 17:40:00 +0000 Message-Id: <20231030174000.3792225-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030174000.3792225-1-peter.maydell@linaro.org> References: <20231030174000.3792225-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Most of the registers used by the FEAT_MOPS instructions cannot use 31 as a register field value; this is CONSTRAINED UNPREDICTABLE to NOP or UNDEF (we UNDEF). However, it is permitted for the "source value" register for the memset insns SET* to be 31, which (as usual for most data-processing insns) means it should be the zero register XZR. We forgot to handle this case, with the effect that trying to set memory to zero with a "SET* Xd, Xn, XZR" sets the memory to the value that happens to be in the low byte of SP. Handle XZR when getting the SET* data value from the register file. Signed-off-by: Peter Maydell --- target/arm/tcg/helper-a64.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 84f54750fc2..ce4800b8d13 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1206,6 +1206,15 @@ static void check_setg_alignment(CPUARMState *env, uint64_t ptr, uint64_t size, } } +static uint64_t arm_reg_or_xzr(CPUARMState *env, int reg) +{ + /* + * Runtime equivalent of cpu_reg() -- return the CPU register value, + * for contexts when index 31 means XZR (not SP). + */ + return reg == 31 ? 0 : env->xregs[reg]; +} + /* * For the Memory Set operation, our implementation chooses * always to use "option A", where we update Xd to the final @@ -1226,7 +1235,7 @@ static void do_setp(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, int rd = mops_destreg(syndrome); int rs = mops_srcreg(syndrome); int rn = mops_sizereg(syndrome); - uint8_t data = env->xregs[rs]; + uint8_t data = arm_reg_or_xzr(env, rs); uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX); uint64_t toaddr = env->xregs[rd]; uint64_t setsize = env->xregs[rn]; @@ -1286,7 +1295,7 @@ static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, int rd = mops_destreg(syndrome); int rs = mops_srcreg(syndrome); int rn = mops_sizereg(syndrome); - uint8_t data = env->xregs[rs]; + uint8_t data = arm_reg_or_xzr(env, rs); uint64_t toaddr = env->xregs[rd] + env->xregs[rn]; uint64_t setsize = -env->xregs[rn]; uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX); @@ -1349,7 +1358,7 @@ static void do_sete(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, int rd = mops_destreg(syndrome); int rs = mops_srcreg(syndrome); int rn = mops_sizereg(syndrome); - uint8_t data = env->xregs[rs]; + uint8_t data = arm_reg_or_xzr(env, rs); uint64_t toaddr = env->xregs[rd] + env->xregs[rn]; uint64_t setsize = -env->xregs[rn]; uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);