From patchwork Fri Oct 27 14:54:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 738782 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F4543716B for ; Fri, 27 Oct 2023 14:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.b="g35Hu48E"; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.b="QE2O+xAw" Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FA831BD for ; Fri, 27 Oct 2023 07:56:50 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2c5210a1515so32581331fa.0 for ; Fri, 27 Oct 2023 07:56:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698418608; x=1699023408; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VByCdrnxfHtWnoG6F/mfiuk5IYGo5RVATzD6olInWaI=; b=l1omvt0RfG/JRXacYspJWsd3wrl4VZhoSMS80dsSKqPWKkq0M3zM5+Ta9344ubwiNp /sAQQPQuSm+J/rg1sjV5TZx1st525+73fG5rJl8dYoCje7K+wLZ5CXWH9ES+YYqNCmF6 w4LS3Iu8FhT1FLFL0rL+i0eJCJP3gRHkvwRDaDc9PgqFHA0nYkWYMbfc0zjf6iT5pz8e +Z0zj5/teYzdDt0G+MvbAjHrvVly2kIl27uhfgFzIdl7wFdElSW20j4FePXz0ppspIBc AEcX1vwgIUieIgrD8rwOqDopASAsFvuobPTyX7zhC8E390KmwNDXtWaKnvwJp02BApmd bGeA== X-Gm-Message-State: AOJu0YwVgmnmCRjKjx4jQC2Zd3qYsbalmTrN3OoVpmpPi6allYxqMrjr JCFFUhq6TDW2AaP9tYVg/jWJ2DqtOnY2AQ== X-Google-Smtp-Source: AGHT+IHkYaeH+G4ozwGDpQeIrNPuakWzE6x3raj5dJAeoMXbCjqlHP3Z0+LQ+8X7u5jfOIDxK+2Ong== X-Received: by 2002:a2e:9246:0:b0:2c5:724:fd64 with SMTP id v6-20020a2e9246000000b002c50724fd64mr2241684ljg.46.1698418608440; Fri, 27 Oct 2023 07:56:48 -0700 (PDT) Received: from flawful.org (c-f5f0e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.240.245]) by smtp.gmail.com with ESMTPSA id h13-20020a2ea48d000000b002c032e54948sm306735lji.117.2023.10.27.07.56.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:56:48 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 4B7AA19B4; Fri, 27 Oct 2023 16:56:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698418607; bh=Rp7KWQac6gUFe8TYFMn8pC3WDmrRdjX9taxMlR96q6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g35Hu48EANXABrZ6M3Nrttjk35lDoq2prmZppXbPVLC3AUqgq+wHMTolDKgS4ZVeJ sxqbqLIQxXJlZgv3tRHShzgmH626mI3eYeDUdlenk/S90QzNi6CvJHjCBvWpmohdQe 9yObDj4LEWHCkBXl+N4DBldb8OJ7G2OLgEyiGI9Y= X-Spam-Level: Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 8BBA51AC3; Fri, 27 Oct 2023 16:54:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698418484; bh=Rp7KWQac6gUFe8TYFMn8pC3WDmrRdjX9taxMlR96q6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QE2O+xAw/sU/KIAlzREn9Ucmw8e//JD2iog+F+brPVEGRyFdg7ejPCMIZz3OEJid6 cz/UE55hyEvDV7nEkik6pIIVRImNWvygAy+scIO/n6IqaK1UKgZTj1Ci2RR9wwpTni Pc4+6VcxJiOkFhhHYdE0d3FAkZ8NyvjFxaIvdbf0= From: Niklas Cassel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Damien Le Moal , Sebastian Reichel , Rob Herring , Serge Semin , Niklas Cassel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 3/6] arm64: dts: rockchip: drop unused properties num-{ib,ob}-windows Date: Fri, 27 Oct 2023 16:54:15 +0200 Message-ID: <20231027145422.40265-4-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231027145422.40265-1-nks@flawful.org> References: <20231027145422.40265-1-nks@flawful.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Niklas Cassel The properties num-ib-windows and num-ob-windows have been deprecated for a long time, and since commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows"), these properties are no longer used by the driver. The correct number of inbound and outbound iATUs are now detected at runtime. Thus, drop these unused properties. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 2 -- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ---- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 -- 3 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index b6ad8328c7eb..da4927a35142 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -102,8 +102,6 @@ &pcie3x1 { &pcie3x2 { num-lanes = <1>; - num-ib-windows = <8>; - num-ob-windows = <8>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index f1be76a54ceb..4487754065b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -84,8 +84,6 @@ pcie3x1: pcie@fe270000 { <0 0 0 3 &pcie3x1_intc 2>, <0 0 0 4 &pcie3x1_intc 3>; linux,pci-domain = <1>; - num-ib-windows = <6>; - num-ob-windows = <2>; max-link-speed = <3>; msi-map = <0x0 &gic 0x1000 0x1000>; num-lanes = <1>; @@ -137,8 +135,6 @@ pcie3x2: pcie@fe280000 { <0 0 0 3 &pcie3x2_intc 2>, <0 0 0 4 &pcie3x2_intc 3>; linux,pci-domain = <2>; - num-ib-windows = <6>; - num-ob-windows = <2>; max-link-speed = <3>; msi-map = <0x0 &gic 0x2000 0x1000>; num-lanes = <2>; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index abee88911982..e2d99613109b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -985,8 +985,6 @@ pcie2x1: pcie@fe260000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; linux,pci-domain = <0>; - num-ib-windows = <6>; - num-ob-windows = <2>; max-link-speed = <2>; msi-map = <0x0 &gic 0x0 0x1000>; num-lanes = <1>; From patchwork Fri Oct 27 14:54:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 738781 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C87E37167 for ; Fri, 27 Oct 2023 14:58:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.b="OY7hFvWC"; dkim=pass (1024-bit key) header.d=flawful.org header.i=@flawful.org header.b="bg4Rw4kF" Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 231DB106 for ; Fri, 27 Oct 2023 07:58:07 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-507be298d2aso3172091e87.1 for ; Fri, 27 Oct 2023 07:58:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698418685; x=1699023485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=siUZJrbtt4CbUUZitfpYvjgu5IMoaEGSfOVSP4bYDnk=; b=Pgm0L7tRJhbH/LvX5AVP0q7rfMeWn2UAqr1fb0rbRAGGEns0fLKajGpPF4wnAuhWN7 53Ukqpvrrsr5vaTKiXADbNpVXXKGpFJMTAl9z5ngXIUf0nXP9mxUc7EugwWPKtZFw4ZP X0pvUI5vUkMGvpR1L+zwCAzjshJ1lJwLdGKKAWu88d+OvkHXdwhwpCt6NVLgss2sC4Pq /SckYtVzJ+FyWkaYZ3g6Ah8BQcsCD5gdhwNeizxCAANf2+b8jm13z3IF1Ac8E7yoC7XI ZzrQW6i+XqDhiLRlLNglGKVy90rXFi4OVeML2yWaR4KCUxACgmD9EXD5Z/TcoCbJuzY6 TTEA== X-Gm-Message-State: AOJu0YwSL8WN5xVvMH1pPUKujo1UQizblOifEYlQdY24cISJxRAWBO6Y Dt1Dmav8NvEjm+CZcNLKBDsgaqtkuL9DLg== X-Google-Smtp-Source: AGHT+IFAIgKLGk6VH7vnoi5Hr0iBqalaRIIv5ECs8J9bMOUYd1qQwk/xb9BKaP3grYi9LUhhR7OSDw== X-Received: by 2002:ac2:488e:0:b0:500:7cab:efc3 with SMTP id x14-20020ac2488e000000b005007cabefc3mr2050848lfc.11.1698418685247; Fri, 27 Oct 2023 07:58:05 -0700 (PDT) Received: from flawful.org (c-f5f0e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.240.245]) by smtp.gmail.com with ESMTPSA id e14-20020a05651236ce00b00505a5ea726asm302219lfs.309.2023.10.27.07.58.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:58:04 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id C46E919B4; Fri, 27 Oct 2023 16:58:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698418683; bh=miupRV8RhYMaqOSEpy6WK8qgDcQilcrGFUgzpsHq5Qk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OY7hFvWCEkQEP6EDnAwC555vF5UQD7Fg4bKlMPoQR5xrymYeEKawK5ycMBQz/4aQ+ kZ/ookYYpHKtrR0pL7YB1JUkAEaMF8Qsw77luc49/s503y19KtnFe87oFup38DPysj QAlwTGrTubtyl/yjPb5IrUtD/VhD6LJoUCfR1k4w= X-Spam-Level: Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 373911ADE; Fri, 27 Oct 2023 16:54:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698418488; bh=miupRV8RhYMaqOSEpy6WK8qgDcQilcrGFUgzpsHq5Qk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bg4Rw4kFarSLAcR/28UZBplA1yW3SaJXCGFBIJJw7D181V2/gtLHKwe8ans8XE/AR hDAP5d90UyeWAqii9AGWHsVNfnRAer7Beoz4QIidOnavnu8NdTvilb+WLE7efYrCyv TiFMDDnDPjw8HDoZoNnNmcDHf2Rz5E4JrIHs4RxU= From: Niklas Cassel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Damien Le Moal , Sebastian Reichel , Rob Herring , Serge Semin , Niklas Cassel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 6/6] arm64: dts: rockchip: add missing rk3588 PCIe eDMA interrupts Date: Fri, 27 Oct 2023 16:54:18 +0200 Message-ID: <20231027145422.40265-7-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231027145422.40265-1-nks@flawful.org> References: <20231027145422.40265-1-nks@flawful.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Niklas Cassel The rk3588 has 5 PCIe controllers, however, according the the rk3588 TRM (Technical Reference Manual), only pcie3x4 has dedicated interrupts wired to embedded DMA controller (eDMA) on the DWC PCIe controller. The eDMA on pcie3x4 has two DMA read channels and two DMA write channels, and according to snps,dw-pcie.yaml, the IRQs for the write channels have to be specified before the IRQs for the read channels in "interrupts". On the rk3588 based rock-5b board, when building with CONFIG_DW_EDMA=y: Before this patch, only the iATUs are detected: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G After this patch, both the iATUs and the eDMA channels are detected: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G rockchip-dw-pcie a40000000.pcie: eDMA: unroll T, 2 wr, 2 rd Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 28955acda9f2..9b042f97f8c8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -101,8 +101,13 @@ pcie3x4: pcie@fe150000 { , , , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,