From patchwork Thu Oct 26 12:44:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EDA8C25B48 for ; Thu, 26 Oct 2023 12:46:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344974AbjJZMqm (ORCPT ); Thu, 26 Oct 2023 08:46:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344969AbjJZMql (ORCPT ); Thu, 26 Oct 2023 08:46:41 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4611710E; Thu, 26 Oct 2023 05:46:39 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30B8CC433C8; Thu, 26 Oct 2023 12:46:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324398; bh=/C6uYsNf+k2NYJmRn5HC5d00qPbiUk6gpp6lP4Wus70=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EUJ9b4fHPp3NmHoLuIb88u3yL123ulXXTz8mujws9Nvs7FXm0ek73iIlGFF8lh4Nr e/whfA+AvR4Fp2ezXzfdeJLxQBgqoF+WSGQAP2IaLud+oswU7x4Leg0IL+wVCg/Shc 8I8c6bRC7FqrdU17LGJeTP1gt8NJFBMAGjvd3Q/bnuLCVo0RX0O1UGUIplQFxgUBK2 j6qSr4pOp9he+ibX1SENsyure3AZqr8I262GKRrDehY1CUv7gFTYFjjT+owxn7lENW uBo5NLBHAPUNj1VpBVdYB4igB67u355AjMXRoJr313OhSkRkaiPNVEcBr+xEJTtuBG /7UraLii886ow== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:16 +0100 Subject: [PATCH 02/21] arm64/sysreg: Update ID_AA64ISAR2_EL1 defintion for DDI0601 2023-09 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-2-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1340; i=broonie@kernel.org; h=from:subject:message-id; bh=/C6uYsNf+k2NYJmRn5HC5d00qPbiUk6gpp6lP4Wus70=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+V17IIomDsq6mCMkzj7i309UYGqYyGh1zX2T6k nCRjH1aJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpflQAKCRAk1otyXVSH0AOkB/ 43X75EYFjRwcuVXX39Xv05Sa90HaJ801YZGPlMrODCNF59tx26HSQ8zz/8ttHJRSN++ro0N3DoRhwi SN4BgwpET5XQYtZ+GKA0nkJXntCc7MEWki9fnkR7j0zCnlsEMukScx9/spVWVc4Sk/pRbVh9TdjMkk IX6mg9pHgvRuRsicEkGGTLDjblxL8INuv2ERRxmaviQeTrW8CzFfCZyYAyEWehBMS27xSm7gZYA46k GScd4LXFgaxzDFeWNVmS3+UntLG5MlokoB9/7y9IokOtjqRkjxRBiehitDE9CIZvRHtSnIhY40d+Sz /9L3Yt1nsp3ZYE+yWsgFdBng60vJwU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org DDI0601 2023-09 defines some new fields in previously RES0 space in ID_AA64ISAR2_EL1, together with one new enum value. Update the system register definition to reflect this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0ea93d166f48..fcca3a3714b0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1359,7 +1359,14 @@ EndEnum EndSysreg Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 -Res0 63:56 +UnsignedEnum 63:60 ATS1A + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 59:56 LUT + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 55:52 CSSC 0b0000 NI 0b0001 IMP @@ -1368,7 +1375,19 @@ UnsignedEnum 51:48 RPRFM 0b0000 NI 0b0001 IMP EndEnum -Res0 47:32 +Res0 47:44 +UnsignedEnum 43:40 PRFMSLC + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 39:36 SYSINSTR_128 + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 35:32 SYSREG_128 + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 31:28 CLRBHB 0b0000 NI 0b0001 IMP @@ -1392,6 +1411,7 @@ UnsignedEnum 15:12 APA3 0b0011 PAuth2 0b0100 FPAC 0b0101 FPACCOMBINE + 0b0110 PAUTH_LR EndEnum UnsignedEnum 11:8 GPA3 0b0000 NI From patchwork Thu Oct 26 12:44:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2FE0C25B67 for ; Thu, 26 Oct 2023 12:46:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231216AbjJZMqw (ORCPT ); Thu, 26 Oct 2023 08:46:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345005AbjJZMqu (ORCPT ); Thu, 26 Oct 2023 08:46:50 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8F8C194; Thu, 26 Oct 2023 05:46:45 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91771C433C9; Thu, 26 Oct 2023 12:46:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324405; bh=l+HCexWWxMeo4+X882PpIsnRc1YU/TuuwGZRa34ZAVo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HxSkc5zcim4fIsz1of6Y5as+8CAZs7GFuQ5+xfycnsE/b/2Is+MZ0XHH/+pA2B+/W mee0IXbfkhsfej9CSwpQ7eYjTGIdqZkGhP6KqcvEIBkU78CmpAsrNhflVoTcqiR2Wj VPJrybUSoaqp56l6aaITq9xi0eQVFvCKURnJVtZlQS8/Gek11tUj7Vj0xMN5CFJlsN 1llfJiMql9H2UUo/ZsF+4bdzNI0LvtJ77O/O6yTvAxuS0TJhqdKmmy+MOvcYae1X2O KX+F+VLJNuPluO3KRh4m5nzAtWP+tk6lWk+QkHsZ73z7moI0bAYDJxwF2+VI9MOH1Y CoIxE9K75HHEw== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:18 +0100 Subject: [PATCH 04/21] arm64/sysreg: Add definition for ID_AA64FPFR0_EL1 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-4-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1020; i=broonie@kernel.org; h=from:subject:message-id; bh=l+HCexWWxMeo4+X882PpIsnRc1YU/TuuwGZRa34ZAVo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+XUuTBqlPY3g709lZjkwYwp+1ZdUE3hY0gt7IQ GpOYfLuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpflwAKCRAk1otyXVSH0K7jB/ 9ICx2WqKsW1ClXsnohdgTF3SOkdLDKnjHNlSqc9Ur0gJ5NCfS6kccYZzLwgEjzoAR5DThfGIZSDJt+ OXOHBgGCBfzN5Ivlaf0WdFkUDQdu+vkrIY0RyNk+2DmE1tUalkkUjydPHS3C6C+ytF3AdgmQNTOGII DS2WsRlR+ll3gC98gzI3fJQXrmiGv3Fni6LVhsUAx+GLfnQIMRIwpFPHauUEAmgTOjR2e2VpiDLhsQ SsIbOH1zVwcZ3vTidZnJxL98YtD9Xqu4iIeF+xPer5Qp7ak4V1fcJMplcR5NKQMOxrYpBYZOBoy/5K Hlgm1bZgqd3CGwsYvIR/0qZHTUCWGz X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org DDI0601 2023-09 defines a new feature register ID_AA64FPFR0_EL1 which enumerates a number of FP8 related features. Add a definition for it. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0515006a7292..057cd85d8c2c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1127,6 +1127,35 @@ EndEnum Res0 31:0 EndSysreg +Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 +Res0 63:32 +UnsignedEnum 31 F8CVT + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 30 F8FMA + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 29 F8DP4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 28 F8DP2 + 0b0 NI + 0b1 IMP +EndEnum +Res0 27:2 +UnsignedEnum 1 F8E4M3 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 0 F8E5M2 + 0b0 NI + 0b1 IMP +EndEnum +EndSysreg + Sysreg ID_AA64DFR0_EL1 3 0 0 5 0 Enum 63:60 HPMN0 0b0000 UNPREDICTABLE From patchwork Thu Oct 26 12:44:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50B65C25B6E for ; Thu, 26 Oct 2023 12:47:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345051AbjJZMrE (ORCPT ); Thu, 26 Oct 2023 08:47:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345012AbjJZMqz (ORCPT ); Thu, 26 Oct 2023 08:46:55 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5612E1BC; Thu, 26 Oct 2023 05:46:52 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0F50C433C8; Thu, 26 Oct 2023 12:46:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324411; bh=oFpKguHAi/AFRsar5DM/a5DMfjfPrq4L3XQpoObPzvM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ri2qxKBQJNvGpLo9SqHrlKTLrhUlyEBtfOw6XZFetGY83LgK6khVhyFNkAlNaPGgM EuzgIJ6+Q5RyFCqeRjHY2hSlz3CnuWvAnQhX2OMPSA/ZhYTSVr6Fnlirmv4P6tKzWF uV61jkJaN9oE/cr74ZDZksfThi3iOFFDA1lWRkvSo3c3YE9RsPFW76U8qiKISn29+4 FwmVtH5mfvG2AaO/Ot4XHNpfymGAr62Sz0TluE4XF4z83AGUQ710L4FpikaHVt6Mzr sOIK0Cue47t3T8tG1ZFJTZC9Cq5EFPhzBXF1Y5Dlnkis6FY/Q4SgIxzkQW8KHbHcDF VH1TFGa1dkgVg== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:20 +0100 Subject: [PATCH 06/21] arm64/sysreg: Update SCTLR_EL1 for DDI0601 2023-09 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-6-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=817; i=broonie@kernel.org; h=from:subject:message-id; bh=oFpKguHAi/AFRsar5DM/a5DMfjfPrq4L3XQpoObPzvM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+YSxS2zmLvWTnTnwZBvqOKxHpSW7yOQbtpETEr 08wWXiKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmAAKCRAk1otyXVSH0I7lB/ 4z2aZ2Oe6EpVndXZu3zbSqXy0VedKb+jf6LBimIDci4OA8eeoK2j8sPM7CL+pQ+4UAN50o2mLUJFoX yN9zE697Mv86xaeiE6hIxHV76tlbt/chlS6ZSXE5AQdzosMhqF7GOY5fG2CFjv97Pj30v4P0RPEFjy 7MvXYvW6E9zSxnFlD88mq3qETlhqQuf7ewxi/GCZvNJrfc9HjimY6fUSnQgIDg2SV0xuuzQeXJkmXq gh9YzM/ua14nORpoTlfAIJC5SXeH6XOwsgZu9ya9np79UZtppI12RMSsFpDTj1pkkwXiYAT8aN0M0e HCqzbIruuXhWNjZjGqlutm4x6WBgwU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org DDI0601 2023-09 defines some new fields in SCTLR_EL1 controlling new MTE and floating point features. Update our sysreg definition to reflect these. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 91dd564ee4d3..97d0da472328 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1785,7 +1785,8 @@ Field 63 TIDCP Field 62 SPINTMASK Field 61 NMI Field 60 EnTP2 -Res0 59:58 +Field 59 TCSO +Field 58 TCSO0 Field 57 EPAN Field 56 EnALS Field 55 EnAS0 @@ -1814,7 +1815,7 @@ EndEnum Field 37 ITFSB Field 36 BT1 Field 35 BT0 -Res0 34 +Field 34 EnFPM Field 33 MSCEn Field 32 CMOW Field 31 EnIA From patchwork Thu Oct 26 12:44:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 927E1C25B67 for ; Thu, 26 Oct 2023 12:47:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233035AbjJZMrP (ORCPT ); Thu, 26 Oct 2023 08:47:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231195AbjJZMrE (ORCPT ); Thu, 26 Oct 2023 08:47:04 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D26A10E9; Thu, 26 Oct 2023 05:46:58 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 633C8C433C8; Thu, 26 Oct 2023 12:46:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324418; bh=DS16tWYR3F7VpcQzgtoFB6E5W9YGpDiaNegIk+jm1dk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LFswMmZqU3SzIsT4cDG0KmUSUwDlbWwrxhX5PJgZ76t/gzl/H9OuDg+KCVRqbz8S8 3dBxf3Sw8PH2n/lwpTtukIXGmtJ6Vq7SCY6qg0+90az5UpTO66C48FmMZ7VfgDOF9c Y/43EyWbAbTRctzt67JWPUOlwwG+fBb6rnkNIt2EhfiAqor4bXuEcddu7Zy3PSriXK HKAg4RLURZ34VaKoz2hcmB+yZrkbfbuUkv/CtxsxxCVD/UYNd5PSAVhAgA1kL4noB4 DcUWivDZHqfeyHKMYAcRQowXt25Icjak+WE2pisnvfRqsga2lXWgpiZKulnMpv/10U 0h04t+SWD1KrQ== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:22 +0100 Subject: [PATCH 08/21] arm64/sysreg: Add definition for FPMR MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-8-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=975; i=broonie@kernel.org; h=from:subject:message-id; bh=DS16tWYR3F7VpcQzgtoFB6E5W9YGpDiaNegIk+jm1dk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+aQjFzMSMDRU1ddpFtQzfW3+/loKKykxvkfyGR SfYVEO2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmgAKCRAk1otyXVSH0CL+B/ 9EHMME7iyfi+AdW55w4cbU/CSm5218COZm2ZFudBp8G1VQTEoMapJ4r2xkOgLU31sDfxfTf9zw5N3i bydjU5couA1UxqAF9L+JihcjIuIrqjVshBTVvz5vo+fe1ax8L0E8PasQ5RXcxlS8DUV3XcHf1mxJNq PbHDR4EZxkmkLQlgk2EntSgAPBnPSO6Aof9/VEDxU580hwGYrIFuIHcJDsIF96EUILFb85uyqZkwAb Egf87T3GGZ0LXpNyKGlufyVaL+nc6KP1ur80vptObIn3ctJh7bW6luxf6BPhhETNCCL/Egaur41yCg LRaPlzmBREdX+kwW/nUB6RrYvREUO/ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org DDI0601 2023-09 defines a new sysrem register FPMR (Floating Point Mode Register) which configures the new FP8 features. Add a definition of this register. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e603a6153527..3e4cb8a141a3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2132,6 +2132,29 @@ Field 1 ZA Field 0 SM EndSysreg +Sysreg FPMR 3 3 4 4 2 +Res0 63:38 +Field 37:32 LSCALE2 +Field 31:24 NSCALE +Res0 23 +Field 22:16 LSCALE +Field 15 OSC +Field 14 OSM +Res0 13:9 +UnsignedEnum 8:6 F8D + 0b000 E5M2 + 0b001 E4M3 +EndEnum +UnsignedEnum 5:3 F8S2 + 0b000 E5M2 + 0b001 E4M3 +EndEnum +UnsignedEnum 2:0 F8S1 + 0b000 E5M2 + 0b001 E4M3 +EndEnum +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 From patchwork Thu Oct 26 12:44:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F6FBC25B48 for ; Thu, 26 Oct 2023 12:47:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235109AbjJZMrb (ORCPT ); Thu, 26 Oct 2023 08:47:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234789AbjJZMrS (ORCPT ); Thu, 26 Oct 2023 08:47:18 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F248D6C; Thu, 26 Oct 2023 05:47:07 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B61B9C4339A; Thu, 26 Oct 2023 12:47:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324426; bh=Es1HQrf2Y34+Fy2pSDeaIOdQfdboYR0FuIcMBXlX4+E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rg50LsreK3vPIQnUFmO4QXkUaZiJ5uu+B1PwlgA+dWT2+hvnlSu8CfejYBS0jIOqN jm6KPhs9etVVGyPwD3sEzY3TZwQh4hptv7k4MGp1X3G2IAOJCp8HeuBqF06vbriFgk qkvDIr/xldrQYb3bFlPSKifIR7Ir8baQSuxKCxS5NzHbK8kdC1UL56z2OD12o++szv 49aiBP6I8e31ZVskSWCtYq99rxIkhvDT+DXwDeGPZZHsSsOzONPW24DPqcCjsUSwCJ NIVKhB47bS7xGcEF7iJPEc5Gd6gWtvf6uboipUivt8bN0CryYGLbDCMPUqCXLu3DRZ jT1jdbWsALl0A== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:24 +0100 Subject: [PATCH 10/21] arm64/fpsimd: Enable host kernel access to FPMR MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-10-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1028; i=broonie@kernel.org; h=from:subject:message-id; bh=Es1HQrf2Y34+Fy2pSDeaIOdQfdboYR0FuIcMBXlX4+E=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+cDio3fVDOG6FkTnDOEe/llr5xX9J3YDZxYQ5e 4EBVfGqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfnAAKCRAk1otyXVSH0KuWB/ 4v50sXhUz0JQ6Df8E+uf8uNMaUfxkYmtpSyW2zLhk5PHHVGCQsyVHKygDY+oINIJP1Am//8A0dhZ5o 1RCYO7dDqCw+olrIQO8LKLKOFNn+tL1rkaIAJVSWu5+qhUkV3m0Tfaux/6l93zI3ginnkp8ohyaucZ wQt5hoE35RQPa/3xJvassbTstV9c02LKJ/mLw2J0zTBtHzJFf0WttobhzE7Ej+i2tqIT/SLAzVshlq jQrdtUDqraR9V4BddiTiGc77Wb4Dxav58X25YbyXOvf20gm0ZAIjOrz8E9cLDXp4MVUvLZTDt+7FeH lWSYXaEk3FeQwEanSBHA3FPQScEbHx X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org FEAT_FPMR provides a new generally accessible architectural register FPMR. This is only accessible to EL0 and EL1 when HCRX_EL2.EnFPM is set to 1, do this when the host is running. The guest part will be done along with context switching the new register and exposing it via guest management. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 1095c6647e96..ef033c6c745c 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -103,7 +103,7 @@ #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) #define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En) -#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En) +#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) /* TCR_EL2 Registers bits */ #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) From patchwork Thu Oct 26 12:44:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4853C25B6E for ; Thu, 26 Oct 2023 12:47:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235053AbjJZMrn (ORCPT ); Thu, 26 Oct 2023 08:47:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235160AbjJZMr0 (ORCPT ); Thu, 26 Oct 2023 08:47:26 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18C2010EF; Thu, 26 Oct 2023 05:47:13 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FE3AC433CA; Thu, 26 Oct 2023 12:47:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324433; bh=qb52W/FnN/1SulYmCofB+kYw3kMDdBBbntUr0aosnTs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZrNfCl1/bl7Dw8ATVLKX3hSzMdpCuDkyfGPm1s6Prn3GMokNNRfjlBD1o0LRHD0DI Gph6e0BlfyssVsxdu1ayodPMxz7TAtb53sS2rp+Vg6BOY8+zBRQlfW+/DWq0ocOdWw IWQTcjwXJXpVu8ZW32xlwKsJo5ITD/Iw1h45Nirj9L3PzQk2Fw8OQGgMqR/mhVrizL CiPR+sGSEwjc0DOoYxGSiHC4waIL7CLTTT3B347MzQG99zOA8rKI/Ry8yN6QcqyMOB PdEBqOnSZjPI4iK/kE5Zh9lfKFRBlVJimaD/cpBmHSJBJl3yQCVy45lupOb/aX05EG kxm8dVU4lxofg== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:26 +0100 Subject: [PATCH 12/21] arm64/signal: Add FPMR signal handling MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-12-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=4170; i=broonie@kernel.org; h=from:subject:message-id; bh=qb52W/FnN/1SulYmCofB+kYw3kMDdBBbntUr0aosnTs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+dtRDImwIBFnMpAxfDCPPH5HNwneLMpNDGTRSR DPy3hQ2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfnQAKCRAk1otyXVSH0GkoB/ 9pPH4k8PLyBH5X4ES02nO3SZvxFJasGzc40jJ9n2AG7F2inbB3oAQVR9/czqVnsmw5J0PNX5C8CT5l TaY8nFERmVyof1Q8yXZ91ON2Gl+DltqmZFoW+WMgLpWo0J3V4DGygrKe4/mbBl1Xjtt+uSVbHPDz91 KZikp4SGOhjjMupzuJaUzeRFpI/FjAu6mIPNNGmI3zRRZM+9E84Atx+iDbrMVK0U8OH1i7E13vui4G aRh9k5RurGbb/7wqKsxchUxRucCg+4Hq0KE6o62cy10WChqrVi9U0kVz0KeB2ZAHz4tQo34SIYaGkw 45a7h4a2SVokXZz7BzafBtG1Q4UwN3 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Expose FPMR in the signal context on systems where it is supported. The kernel validates the exact size of the FPSIMD registers so we can't readily add it to fpsimd_context without disruption. Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/sigcontext.h | 8 +++++ arch/arm64/kernel/signal.c | 59 ++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index f23c1dc3f002..8a45b7a411e0 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -152,6 +152,14 @@ struct tpidr2_context { __u64 tpidr2; }; +/* FPMR context */ +#define FPMR_MAGIC 0x46504d52 + +struct fpmr_context { + struct _aarch64_ctx head; + __u64 fpmr; +}; + #define ZA_MAGIC 0x54366345 struct za_context { diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 0e8beb3349ea..e8c808afcc8a 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -60,6 +60,7 @@ struct rt_sigframe_user_layout { unsigned long tpidr2_offset; unsigned long za_offset; unsigned long zt_offset; + unsigned long fpmr_offset; unsigned long extra_offset; unsigned long end_offset; }; @@ -182,6 +183,8 @@ struct user_ctxs { u32 za_size; struct zt_context __user *zt; u32 zt_size; + struct fpmr_context __user *fpmr; + u32 fpmr_size; }; static int preserve_fpsimd_context(struct fpsimd_context __user *ctx) @@ -227,6 +230,33 @@ static int restore_fpsimd_context(struct user_ctxs *user) return err ? -EFAULT : 0; } +static int preserve_fpmr_context(struct fpmr_context __user *ctx) +{ + int err = 0; + + current->thread.fpmr = read_sysreg_s(SYS_FPMR); + + __put_user_error(FPMR_MAGIC, &ctx->head.magic, err); + __put_user_error(sizeof(*ctx), &ctx->head.size, err); + __put_user_error(current->thread.fpmr, &ctx->fpmr, err); + + return err; +} + +static int restore_fpmr_context(struct user_ctxs *user) +{ + u64 fpmr; + int err = 0; + + if (user->fpmr_size != sizeof(*user->fpmr)) + return -EINVAL; + + __get_user_error(fpmr, &user->fpmr->fpmr, err); + if (!err) + write_sysreg_s(fpmr, SYS_FPMR); + + return err; +} #ifdef CONFIG_ARM64_SVE @@ -590,6 +620,7 @@ static int parse_user_sigframe(struct user_ctxs *user, user->tpidr2 = NULL; user->za = NULL; user->zt = NULL; + user->fpmr = NULL; if (!IS_ALIGNED((unsigned long)base, 16)) goto invalid; @@ -684,6 +715,17 @@ static int parse_user_sigframe(struct user_ctxs *user, user->zt_size = size; break; + case FPMR_MAGIC: + if (!system_supports_fpmr()) + goto invalid; + + if (user->fpmr) + goto invalid; + + user->fpmr = (struct fpmr_context __user *)head; + user->fpmr_size = size; + break; + case EXTRA_MAGIC: if (have_extra_context) goto invalid; @@ -806,6 +848,9 @@ static int restore_sigframe(struct pt_regs *regs, if (err == 0 && system_supports_tpidr2() && user.tpidr2) err = restore_tpidr2_context(&user); + if (err == 0 && system_supports_fpmr() && user.fpmr) + err = restore_fpmr_context(&user); + if (err == 0 && system_supports_sme() && user.za) err = restore_za_context(&user); @@ -928,6 +973,13 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, } } + if (system_supports_fpmr()) { + err = sigframe_alloc(user, &user->fpmr_offset, + sizeof(struct fpmr_context)); + if (err) + return err; + } + return sigframe_alloc_end(user); } @@ -983,6 +1035,13 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user, err |= preserve_tpidr2_context(tpidr2_ctx); } + /* FPMR if supported */ + if (system_supports_fpmr() && err == 0) { + struct fpmr_context __user *fpmr_ctx = + apply_user_offset(user, user->fpmr_offset); + err |= preserve_fpmr_context(fpmr_ctx); + } + /* ZA state if present */ if (system_supports_sme() && err == 0 && user->za_offset) { struct za_context __user *za_ctx = From patchwork Thu Oct 26 12:44:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA6F7C25B48 for ; Thu, 26 Oct 2023 12:48:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345017AbjJZMsA (ORCPT ); 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a=openpgp-sha256; l=1320; i=broonie@kernel.org; h=from:subject:message-id; bh=DIIfc135uXljK74SaVIpbtbdhvdA87NEj6R4ylFiBfM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+fLC49gT8E/5ElSMU1keDsOAH7G7wRO3eRIqUw jcC6j+aJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfnwAKCRAk1otyXVSH0OHIB/ 0Y4/qd1COrtBKzNMOa9pDRrW9iNmHoVOXZe0+lpK+0j86HfeV7ixEQgl7vc+TH9ILcN42vUMgat3v9 CR7cS0IC8pm03yoRLMo4scLHKGJNapAMnko1em2IIkVXfZDXjhCMUTsKNxDb6WONtDjw3C3I8gVftz NzVjzc3zm8Ro5hAEcpd9cyIDUeLjay0jvUbCPGVJlrgJX9Ok98fHpQVDhufKjb/vtoupE6+46DD2Sx ExSemBLCZBXMvuiJGLa36c2vhpwL0h65gxrIwk0KF9y3R4CaxFI2VRorw0oJYAdeAb3Cn7zb7S1ysK d5CbaxW4uVA2UjYiIOzYvLF5OyGfXd X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The 2023 architecture extensions have allocated some new ID registers, add them to the KVM system register descriptions so that they are visible to guests. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0afd6136e275..99cdaa594b06 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2016,12 +2016,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { .reset = read_sanitised_id_aa64pfr0_el1, .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, ID_SANITISED(ID_AA64PFR1_EL1), - ID_UNALLOCATED(4,2), + ID_SANITISED(ID_AA64PFR2_EL1), ID_UNALLOCATED(4,3), ID_SANITISED(ID_AA64ZFR0_EL1), ID_HIDDEN(ID_AA64SMFR0_EL1), ID_UNALLOCATED(4,6), - ID_UNALLOCATED(4,7), + ID_SANITISED(ID_AA64FPFR0_EL1), /* CRm=5 */ { SYS_DESC(SYS_ID_AA64DFR0_EL1), @@ -2042,7 +2042,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_SANITISED(ID_AA64ISAR0_EL1), ID_SANITISED(ID_AA64ISAR1_EL1), ID_SANITISED(ID_AA64ISAR2_EL1), - ID_UNALLOCATED(6,3), + ID_SANITISED(ID_AA64ISAR3_EL1), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), ID_UNALLOCATED(6,6), From patchwork Thu Oct 26 12:44:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6B68C25B67 for ; Thu, 26 Oct 2023 12:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345135AbjJZMsH (ORCPT ); Thu, 26 Oct 2023 08:48:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235029AbjJZMrn (ORCPT ); Thu, 26 Oct 2023 08:47:43 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43068D4D; Thu, 26 Oct 2023 05:47:26 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 169DCC433C9; Thu, 26 Oct 2023 12:47:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324445; bh=4OXDOFakN2kGeGyBUbfy2pFYD4qDL67ZeSXZ8Z9LAmA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gk9ihdiGGV3KC1p2YzsPscPeHTn8J0JTqJG/cZ1rAhV2detVB0thWf3bSlpZt2LMD y7ShSDegeMFN/DgJNTSu+Bb6Dbv4bLRJoahHs06BE8d6AT20oDLoZ5JOS4y3IFf3Bh H8wGhArBm6igko4WihWjN+tF6GVOxZktgELX9VmKKE2mfbPKips0o7Z1Jitxwpuvyc 5rQk2bKOi9D7oRclFQUdseBUWjAE7fJ6DNMlYdc808Zni/PPEFA62rjT4fVZmiUpOa ag+Zx7rIthCk9hfN9l16ELs8Rh5clsS8rrbLaLcC1di5VHC1rHdYv9UASb4bz4ezrf /pd+mQhFdlR9A== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:30 +0100 Subject: [PATCH 16/21] arm64/hwcap: Define hwcaps for 2023 DPISA features MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-16-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=12791; i=broonie@kernel.org; h=from:subject:message-id; bh=4OXDOFakN2kGeGyBUbfy2pFYD4qDL67ZeSXZ8Z9LAmA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+gtbgo+cGG4P4PmvpcGxxA5j1nYbpjslXq2Tjr CGkljGOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfoAAKCRAk1otyXVSH0P1JB/ 9U8bkUm8lJD5GRHO3INoQInYh8KdGuaSYUkzl/LdxsTRZKVVlClrJHqRXOEbacKewVcfud/y2oB/sc 4NMFahxfzpv15VmFjdFwYW2CdGxJQu2/BNSgk2E0VULyS06YOdfEVCCa0d5355L0QNzS2as4JKJhKp tGC51WidN6o3gu9oozYQz86Z78j7bx8XCX2AYhEyEnD35V5lYpHJ6m7NAbZpEmkuhfLqUaaVN1vpF4 xV5pJlO5GRHTvQYL8dOF0TyfBHswVRBkYI2fjZdbDizCDJdT6DiG/eq+bru0IqD608b3BMnVNVNzU2 hA1VJ9XIA2DxlNCjeURQ9CI05BgUI5 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The 2023 architecture extensions include a large number of floating point features, most of which simply add new instructions. Add hwcaps so that userspace can enumerate these features. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 49 +++++++++++++++++++++++++++++++++ arch/arm64/include/asm/hwcap.h | 15 ++++++++++ arch/arm64/include/uapi/asm/hwcap.h | 15 ++++++++++ arch/arm64/kernel/cpufeature.c | 35 +++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 15 ++++++++++ 5 files changed, 129 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 76ff9d7398fd..777d8b868f98 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -308,6 +308,55 @@ HWCAP2_MOPS HWCAP2_HBC Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001. +HWCAP2_FPMR + Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001. + +HWCAP2_LUT + Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001. + +HWCAP2_FAMINMAX + Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001. + +HWCAP2_F8CVT + Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1. + +HWCAP2_F8FMA + Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1. + +HWCAP2_F8DP4 + Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1. + +HWCAP2_F8DP2 + Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1. + +HWCAP2_F8E4M3 + Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1. + +HWCAP2_F8E5M2 + Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1. + +HWCAP2_SME_LUTV2 + Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1. + +HWCAP2_SME_F8F16 + Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1. + +HWCAP2_SME_F8F32 + Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1. + +HWCAP2_SME_SF8FMA + Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1. + +HWCAP2_SME_SF8DP4 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. + +HWCAP2_SME_SF8DP2 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1. + +HWCAP2_SME_SF8DP4 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. + + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 521267478d18..046978936d25 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -139,6 +139,21 @@ #define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16) #define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS) #define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) +#define KERNEL_HWCAP_FPMR __khwcap2_feature(FPMR) +#define KERNEL_HWCAP_LUT __khwcap2_feature(LUT) +#define KERNEL_HWCAP_FAMINMAX __khwcap2_feature(FAMINMAX) +#define KERNEL_HWCAP_F8CVT __khwcap2_feature(F8CVT) +#define KERNEL_HWCAP_F8FMA __khwcap2_feature(F8FMA) +#define KERNEL_HWCAP_F8DP4 __khwcap2_feature(F8DP4) +#define KERNEL_HWCAP_F8DP2 __khwcap2_feature(F8DP2) +#define KERNEL_HWCAP_F8E4M3 __khwcap2_feature(F8E4M3) +#define KERNEL_HWCAP_F8E5M2 __khwcap2_feature(F8E5M2) +#define KERNEL_HWCAP_SME_LUTV2 __khwcap2_feature(SME_LUTV2) +#define KERNEL_HWCAP_SME_F8F16 __khwcap2_feature(SME_F8F16) +#define KERNEL_HWCAP_SME_F8F32 __khwcap2_feature(SME_F8F32) +#define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) +#define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) +#define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 53026f45a509..0f0aa9006cef 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -104,5 +104,20 @@ #define HWCAP2_SME_F16F16 (1UL << 42) #define HWCAP2_MOPS (1UL << 43) #define HWCAP2_HBC (1UL << 44) +#define HWCAP2_FPMR (1UL << 45) +#define HWCAP2_LUT (1UL << 46) +#define HWCAP2_FAMINMAX (1UL << 47) +#define HWCAP2_F8CVT (1UL << 48) +#define HWCAP2_F8FMA (1UL << 49) +#define HWCAP2_F8DP4 (1UL << 50) +#define HWCAP2_F8DP2 (1UL << 51) +#define HWCAP2_F8E4M3 (1UL << 52) +#define HWCAP2_F8E5M2 (1UL << 53) +#define HWCAP2_SME_LUTV2 (1UL << 54) +#define HWCAP2_SME_F8F16 (1UL << 55) +#define HWCAP2_SME_F8F32 (1UL << 56) +#define HWCAP2_SME_SF8FMA (1UL << 57) +#define HWCAP2_SME_SF8DP4 (1UL << 58) +#define HWCAP2_SME_SF8DP2 (1UL << 59) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 8e8cd411d1a2..2c85bc9e644c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -220,6 +220,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), @@ -235,6 +236,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -301,6 +303,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -313,6 +317,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -323,10 +331,22 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), ARM64_FTR_END, }; static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), ARM64_FTR_END, }; @@ -2838,6 +2858,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), + HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), @@ -2850,6 +2871,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), + HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), + HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), @@ -2889,6 +2912,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #ifdef CONFIG_ARM64_SME HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), @@ -2896,12 +2920,23 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), + HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), + HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), #endif /* CONFIG_ARM64_SME */ + HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index e153c6d2b3fd..9ff497ca70b4 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -127,6 +127,21 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_F16F16] = "smef16f16", [KERNEL_HWCAP_MOPS] = "mops", [KERNEL_HWCAP_HBC] = "hbc", + [KERNEL_HWCAP_FPMR] = "fpmr", + [KERNEL_HWCAP_LUT] = "lut", + [KERNEL_HWCAP_FAMINMAX] = "faminmax", + [KERNEL_HWCAP_F8CVT] = "f8cvt", + [KERNEL_HWCAP_F8FMA] = "f8fma", + [KERNEL_HWCAP_F8DP4] = "f8dp4", + [KERNEL_HWCAP_F8DP2] = "f8dp2", + [KERNEL_HWCAP_F8E4M3] = "f8e4m3", + [KERNEL_HWCAP_F8E5M2] = "f8e5m2", + [KERNEL_HWCAP_SME_LUTV2] = "smelutv2", + [KERNEL_HWCAP_SME_F8F16] = "smef8f16", + [KERNEL_HWCAP_SME_F8F32] = "smef8f32", + [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", + [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", + [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", }; #ifdef CONFIG_COMPAT From patchwork Thu Oct 26 12:44:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56C2EC25B67 for ; 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a=openpgp-sha256; l=2813; i=broonie@kernel.org; h=from:subject:message-id; bh=irtBwegYB+DXpSWW34B5isPMLTYQBsVR3AqcPDPAR5U=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+iCJdeV2fsyrb2Goi5LFUKDp5cDy2hkYV1hTmP NxdgV+qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfogAKCRAk1otyXVSH0G9uB/ 9Uk6ue6AiOXc9U24n6Z1wmQoT6SRGNy0Sw6uyrZBwn8z/osMnkYzrq6zTxCgXlkcFeK9A+saCjA+qf Yo8GH1Hzhm8Ca1Jry/vNstZVkyQ2MYQtn4fc6B4zxYyeJ/G9BiQnctdjJYMLxfl4cIUr+t0KghbqIB ya59WP3L0gCeBnXe2PGC2uWZoOUJl8+krxUeDaWmvOjgSqbGkIk6VWrqk/rm/scVjAc+gFTn+e/KdC xCPNkJa/ttYorYFaFnjCtRQ91ww7BShiiCxRZqFiaSVhm7jUMsUxz2BZORzA0e5WeFBosKyVtYogmU JLQrK2cV9JJoSpjaqeMFfmBEH40Fpc X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Verify that a FPMR frame is generated on systems that support FPMR and not generated otherwise. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/signal/.gitignore | 1 + .../arm64/signal/testcases/fpmr_siginfo.c | 82 ++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/.gitignore b/tools/testing/selftests/arm64/signal/.gitignore index 839e3a252629..1ce5b5eac386 100644 --- a/tools/testing/selftests/arm64/signal/.gitignore +++ b/tools/testing/selftests/arm64/signal/.gitignore @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only mangle_* fake_sigreturn_* +fpmr_* sme_* ssve_* sve_* diff --git a/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c b/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c new file mode 100644 index 000000000000..e9d24685e741 --- /dev/null +++ b/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 ARM Limited + * + * Verify that the FPMR register context in signal frames is set up as + * expected. + */ + +#include +#include +#include +#include +#include +#include + +#include "test_signals_utils.h" +#include "testcases.h" + +static union { + ucontext_t uc; + char buf[1024 * 128]; +} context; + +#define SYS_FPMR "S3_3_C4_C4_2" + +static uint64_t get_fpmr(void) +{ + uint64_t val; + + asm volatile ( + "mrs %0, " SYS_FPMR "\n" + : "=r"(val) + : + : "cc"); + + return val; +} + +int fpmr_present(struct tdescr *td, siginfo_t *si, ucontext_t *uc) +{ + struct _aarch64_ctx *head = GET_BUF_RESV_HEAD(context); + struct fpmr_context *fpmr_ctx; + size_t offset; + bool in_sigframe; + bool have_fpmr; + __u64 orig_fpmr; + + have_fpmr = getauxval(AT_HWCAP2) & HWCAP2_FPMR; + if (have_fpmr) + orig_fpmr = get_fpmr(); + + if (!get_current_context(td, &context.uc, sizeof(context))) + return 1; + + fpmr_ctx = (struct fpmr_context *) + get_header(head, FPMR_MAGIC, td->live_sz, &offset); + + in_sigframe = fpmr_ctx != NULL; + + fprintf(stderr, "FPMR sigframe %s on system %s FPMR\n", + in_sigframe ? "present" : "absent", + have_fpmr ? "with" : "without"); + + td->pass = (in_sigframe == have_fpmr); + + if (have_fpmr && fpmr_ctx) { + if (fpmr_ctx->fpmr != orig_fpmr) { + fprintf(stderr, "FPMR in frame is %llx, was %llx\n", + fpmr_ctx->fpmr, orig_fpmr); + td->pass = false; + } + } + + return 0; +} + +struct tdescr tde = { + .name = "FPMR", + .descr = "Validate that FPMR is present as expected", + .timeout = 3, + .run = fpmr_present, +}; From patchwork Thu Oct 26 12:44:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 738540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A67F9C25B72 for ; Thu, 26 Oct 2023 12:48:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345040AbjJZMsi (ORCPT ); Thu, 26 Oct 2023 08:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345020AbjJZMsD (ORCPT ); Thu, 26 Oct 2023 08:48:03 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E37331BD1; Thu, 26 Oct 2023 05:47:38 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E3799C433C8; Thu, 26 Oct 2023 12:47:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324458; bh=RtrbRWeplo/J+dSChm3CUN1rkk7mxJJmNnU3ySYX5lo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JwavNWQ7Qw92WJ9PaGFEOjbAckxxdipb5X3kcuitU6FhySsU0xjhk4HSxtN6h21O5 91aWAqZiNQknMOXNqZ9gAgIuVKiPLQQgg70DAR85CjFcIHiPgjAkpYgEcTaoyCeTRA jTwTcjIaO+RK/gVZFYCi69E/pfMpMDdentwpOqgzEL0mIgkJca+6bnn4Y3C1hNEAEh iZXWJdtsrASdl7JIhFUKzB+bEip1ETlQo7cQ4yeUuonHp/nAJa+r7A6v71SS6/a8Ma 7O6PfoHqkQsVb7e32Vix/OCbJvaSfw6bl7AHkOjCp3fT12AwzbSey2KoEBH8g2i4gQ jBvGMw55JuvdA== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:34 +0100 Subject: [PATCH 20/21] KVM: arm64: selftests: Document feature registers added in 2023 extensions MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-20-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1469; i=broonie@kernel.org; h=from:subject:message-id; bh=RtrbRWeplo/J+dSChm3CUN1rkk7mxJJmNnU3ySYX5lo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+jqft2YUkLQI/MEIY8LsCKvoGxDY1hXrWu8EsK SE9K94iJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfowAKCRAk1otyXVSH0OTPB/ sF9p1R8jj6bjpG3QesJ8SB2O8D51f0dDJutFMcOLKbk0QFhKh8/7t+9NjWxNSSyaDjiJQY4+pEg3dg UtHPf1IaWZ4Aa1h+YgaSMmrpZrmS7quTWEERxUZeGl4MsyI34bCke+AIZXv4Niq0elLuHS6YnPDv5z aPh8LxzXWQXQNqkNF7CjpAUAwABqvf/wvIgGQ9BldTga0KvRb4bwx2xz03Np7KQE2x2jF8xuH2Hxy+ MhC55De1aGWRPrWV4nxEB+WkLDITM7gmeA5QxC6DJTDz0ZjG4RqyY1VbDtSwaJB1ChoNlnFFMt9avh efbpskKDkEuopq0V6dry7QdwWRSbiS X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The 2023 architecture extensions allocated some previously usused feature registers, add comments mapping the names in get-reg-list as we do for the other allocated registers. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 709d7d721760..71ea6ecec7ce 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -428,7 +428,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 4, 4), /* ID_AA64ZFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 5), /* ID_AA64SMFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 6), - ARM64_SYS_REG(3, 0, 0, 4, 7), + ARM64_SYS_REG(3, 0, 0, 4, 7), /* ID_AA64FPFR_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 0), /* ID_AA64DFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 1), /* ID_AA64DFR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 2), @@ -440,7 +440,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 6, 0), /* ID_AA64ISAR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 1), /* ID_AA64ISAR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 2), /* ID_AA64ISAR2_EL1 */ - ARM64_SYS_REG(3, 0, 0, 6, 3), + ARM64_SYS_REG(3, 0, 0, 6, 3), /* ID_AA64ISAR3_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 4), ARM64_SYS_REG(3, 0, 0, 6, 5), ARM64_SYS_REG(3, 0, 0, 6, 6),