From patchwork Mon Oct 23 03:06:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 737446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D28A9CDB474 for ; Mon, 23 Oct 2023 03:07:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233215AbjJWDHB (ORCPT ); Sun, 22 Oct 2023 23:07:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjJWDG7 (ORCPT ); Sun, 22 Oct 2023 23:06:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7589ED41; Sun, 22 Oct 2023 20:06:52 -0700 (PDT) X-UUID: 3346eb74715111eea33bb35ae8d461a2-20231023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=9YVIRwmFT8KYFj002+Q2SJxtVfpVydhliFb7K5MsQ7g=; b=hhbaAD2XJKypAxOiqyWZys8xaAfeCfI6aP2PdKr0R49UO3rY6LetZrK0/7r89Z+sQfpNdp5drfpZUvvJKskQIqOqFbmO5MB9kSlNqXlrozpDMvnz6PKkhAh36E6efYpdcwtvBA6Vy3H5ir9FwkLWoBJXEmWaMeJmALXVx4tvlL0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32, REQID:fb96c431-51e0-4244-b699-d79254134414, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9, CLOUDID:5a95067d-ccd9-4df5-91ce-9df5fea3ae01, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 3346eb74715111eea33bb35ae8d461a2-20231023 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1702391185; Mon, 23 Oct 2023 11:06:46 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 11:06:44 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 11:06:43 +0800 From: Yunfei Dong To: Sebastian Fricke , =?utf-8?q?N=C3=ADcola?= =?utf-8?q?s_F_=2E_R_=2E_A_=2E_Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH v2, 2/7] media: mediatek: vcodec: Set the supported h264 level for each platform Date: Mon, 23 Oct 2023 11:06:35 +0800 Message-ID: <20231023030640.16393-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231023030640.16393-1-yunfei.dong@mediatek.com> References: <20231023030640.16393-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Set the maximum H264 codec level for each platform. The various mediatek platforms support different levels for decoding, the level of the codec limits among others the maximum resolution, bit rate and frame rate for the decoder. Signed-off-by: Yunfei Dong Reviewed-by: Sebastian Fricke --- .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index e29c9c58f3da..7aaf0db13a76 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -56,6 +56,15 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { }, .codec_type = V4L2_PIX_FMT_H264_SLICE, }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, + .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .def = V4L2_MPEG_VIDEO_H264_LEVEL_4_1, + .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + }, + .codec_type = V4L2_PIX_FMT_H264_SLICE, + }, { .cfg = { .id = V4L2_CID_STATELESS_H264_DECODE_MODE, @@ -519,6 +528,40 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = { .s_ctrl = mtk_vdec_s_ctrl, }; +static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8192: + case MTK_VDEC_MT8188: + cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2; + break; + case MTK_VDEC_MT8195: + cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0; + break; + case MTK_VDEC_MT8183: + case MTK_VDEC_MT8186: + cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2; + break; + default: + cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1; + break; + }; +} + +static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (cfg->id) { + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: + mtk_vcodec_dec_fill_h264_level(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def); + break; + default: + break; + }; +} + static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx) { unsigned int i; @@ -532,6 +575,8 @@ static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx) for (i = 0; i < NUM_CTRLS; i++) { struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg; cfg.ops = &mtk_vcodec_dec_ctrl_ops; + + mtk_vcodec_dec_reset_controls(&cfg, ctx); v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL); if (ctx->ctrl_hdl.error) { mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i, From patchwork Mon Oct 23 03:06:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 737445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC4A3C07545 for ; Mon, 23 Oct 2023 03:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233235AbjJWDHD (ORCPT ); Sun, 22 Oct 2023 23:07:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233129AbjJWDG7 (ORCPT ); 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Mon, 23 Oct 2023 11:06:47 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 11:06:45 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 11:06:44 +0800 From: Yunfei Dong To: Sebastian Fricke , =?utf-8?q?N=C3=ADcola?= =?utf-8?q?s_F_=2E_R_=2E_A_=2E_Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , "Steve Cho" , Yunfei Dong , , , , , , Subject: [PATCH v2, 3/7] media: mediatek: vcodec: Set the supported h265 level for each platform Date: Mon, 23 Oct 2023 11:06:36 +0800 Message-ID: <20231023030640.16393-4-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231023030640.16393-1-yunfei.dong@mediatek.com> References: <20231023030640.16393-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.086800-8.000000 X-TMASE-MatchedRID: AGyNPhznEz/nWmH8Qoh70pyBsp6+TmyGjiWciALpTNMx3z93vsEFGtvM SB0gigG5ThbvLLI8RvNELJsmoli+adAjTMr/wDJy7spMO3HwKCDaoFJAcCHymC8zQZ2rR/Op8bf 335SL+11yLoBTJinK3+uLFZZYlisfHxPMjOKY7A8LbigRnpKlKZvjAepGmdoO4aFwAALy/uKyKQ DJPZx2Hu+zvpLmmWkv/rGGU8AhgWiSEv7qwpBbmFM7o8d4416lSwv4nSP4/VL1yE6GKuGBsClAL GFiDaFp8jae4OD13tAV7Mc+rowcVKtX/F0pBwVJjSV5hDFby7ZnIxZyJs78kg== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.086800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: C9D0983908FB3F416092D1C7DDD89FE71C8C5EE95D5EDE13A6ACA2322155D1882000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Set the maximum H265 codec level for each platform. The various mediatek platforms support different levels for decoding, the level of the codec limits among others the maximum resolution, bit rate and frame rate for the decoder. Signed-off-by: Yunfei Dong Reviewed-by: Sebastian Fricke --- .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index 7aaf0db13a76..f68518ba57c5 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -147,6 +147,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { }, .codec_type = V4L2_PIX_FMT_HEVC_SLICE, }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { .cfg = { .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, @@ -549,6 +559,22 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, }; } +static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8188: + cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; + break; + case MTK_VDEC_MT8195: + cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; + break; + default: + cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; + break; + }; +} + static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { @@ -557,6 +583,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, mtk_vcodec_dec_fill_h264_level(cfg, ctx); mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def); break; + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: + mtk_vcodec_dec_fill_h265_level(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def); + break; default: break; }; From patchwork Mon Oct 23 03:06:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 737444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA2E2C07545 for ; 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Mon, 23 Oct 2023 11:06:46 +0800 From: Yunfei Dong To: Sebastian Fricke , =?utf-8?q?N=C3=ADcola?= =?utf-8?q?s_F_=2E_R_=2E_A_=2E_Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH v2,5/7] media: mediatek: vcodec: Set the supported h265 profile for each platform Date: Mon, 23 Oct 2023 11:06:38 +0800 Message-ID: <20231023030640.16393-6-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231023030640.16393-1-yunfei.dong@mediatek.com> References: <20231023030640.16393-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Set the maximum H265 codec profile for each platform. The various mediatek platforms support different profiles for decoding, the profile of the codec limits the capabilities for decoding. Signed-off-by: Yunfei Dong Reviewed-by: Sebastian Fricke --- .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index a93098b3a390..816709fe0f18 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -589,6 +589,20 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, }; } +static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8188: + case MTK_VDEC_MT8195: + cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; + break; + default: + cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE; + break; + }; +} + static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { @@ -606,6 +620,11 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, mtk_v4l2_vdec_dbg(3, ctx, "h264 supported profile: %lld %lld", cfg->max, cfg->menu_skip_mask); break; + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: + mtk_vcodec_dec_fill_h265_profile(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "h265 supported profile: %lld %lld", cfg->max, + cfg->menu_skip_mask); + break; default: break; };