From patchwork Mon Oct 23 16:15:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 737260 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1613628wrl; Mon, 23 Oct 2023 09:16:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFOFFEL7o5GKcmry+6tceAc4lSZGd0AD1imbqQ4Wat8T42nlPg32r+j8zGNOgWxRBJFlySH X-Received: by 2002:a05:6214:628:b0:65d:4840:6eb4 with SMTP id a8-20020a056214062800b0065d48406eb4mr13866191qvx.6.1698077803575; Mon, 23 Oct 2023 09:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698077803; cv=none; d=google.com; s=arc-20160816; b=BcZzIpZySpfGE9iRsFKJhqOG1rWYY+HMAtWFnQgCga3mXhBbmKMVuWDRssG8k/80n8 W/nVTzh9/GZVoKaDPnQvUC6EUp7TQ8SnBWUjjagbFti4UHyyJB7QHKtp4T6Rm3H8+MMI XQr+7V4Sf1F3T3vQQg7bpvMioe5MnLif8DRx53hvdZUeDZ8izyl6YOezra3AmKgbfZVu eO2Gr/oBmjnpECKuNn8SDuMQmF4Q5quZ0CHRo2sgQL5WgkINVJw55ljWVxJ+PZilst1r 3DS5jcQtg7HEcTBXjUGs34QyOriGZJ+wQ4JmpBbgZVO2kHH8L8OlFtskc0+/LVFqctTz 3rXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NpxMMC0Od/uz08PSmYxq/ROkgKU67AYMrN/Jii7P8Qg=; fh=55V10LP5MT2YC3CMmeD8ox5TQv4iI1rYZzQqEc55Dnw=; b=0jL5kYMfs35I1QoOmJvMB/C2122Sq1+9waeD+CLA5hcKvIZfpslhH714khe01BrM05 qoGTv1RHQJF6Ld+QAbAUYQ4yKPRb0swT/PYNuOykKuraK4UG55Q+WMoA7OlXrpeYiMb5 QK+0SnayPVTFyHsBRZm8HNg4MlGixfAgpeYyCjRUZrDJ8I82YpYy9pQMa4QpZubwSY9A Se1bg/0oPwvksHiqDuYqe0mvXbRZSLn/VarYx2pQ+8SvpSEgEO9D1SLo9GKoCm1ICTru hMWNhtLSQ68FiuFAtrhCP1jZwVtCPWrFS8vq+RXWstLvFKE5BcpNDEGbu+FSzheA4aYe qgUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JEpH9h3h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020a05600c2e4c00b0040648217f4fsm14460597wmf.39.2023.10.23.09.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 09:15:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Axel Heider , Laszlo Ersek , Ard Biesheuvel , Shannon Zhao , Igor Mammedov , Ani Sinha , "Michael S. Tsirkin" Subject: [PATCH 1/3] hw/arm/virt: Add serial aliases in DTB Date: Mon, 23 Oct 2023 17:15:30 +0100 Message-Id: <20231023161532.2729084-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023161532.2729084-1-peter.maydell@linaro.org> References: <20231023161532.2729084-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If there is more than one UART in the DTB, then there is no guarantee on which order a guest is supposed to initialise them. The standard solution to this is "serialN" entries in the "/aliases" node of the dtb which give the nodename of the UARTs. At the moment we only have two UARTs in the DTB when one is for the Secure world and one for the Non-Secure world, so this isn't really a problem. However if we want to add a second NS UART we'll need the aliases to ensure guests pick the right one. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 529f1c089c0..b714ff1c03d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -280,6 +280,8 @@ static void create_fdt(VirtMachineState *vms) } } + qemu_fdt_add_subnode(fdt, "/aliases"); + /* Clock node, for the benefit of the UART. The kernel device tree * binding documentation claims the PL011 node clock properties are * optional but in practice if you omit them the kernel refuses to @@ -889,7 +891,9 @@ static void create_uart(const VirtMachineState *vms, int uart, if (uart == VIRT_UART) { qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); } else { + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); /* Mark as not usable by the normal world */ qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); From patchwork Mon Oct 23 16:15:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 737258 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1613180wrl; Mon, 23 Oct 2023 09:15:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGgEDLVewEuo44WIrYOZKJ8iJ+p5ufLuoBQhjTN+ZnqR3EPqOYfZXbgzAAnbWcc9kFWw3Ip X-Received: by 2002:a1f:23d0:0:b0:49d:94a3:dd5 with SMTP id j199-20020a1f23d0000000b0049d94a30dd5mr7687870vkj.9.1698077754228; Mon, 23 Oct 2023 09:15:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698077754; cv=none; d=google.com; s=arc-20160816; b=GvgePLSiHsKpN2Sy91Qp+4JXG1fytaYXwj2b51UlkdjKL7SfmDX8LpxBAxSdH1KVwf D35tJ705oWPiRmtPQMtOAIK5wBz8Qe7bgguTBMahMRsWkquruDLUcM9FPeKwNT6QCCkR 6dYCE0caKI1AuQCmlKc+lch1TORzMOiIIsnoLJO4qM3toEQnSh3JTJydSo3SiaLSUW8C tQ/xbQ67cbaL0ZGdg0PdKcHNVQX+HwokKAfyPypFkNGPB3PqWSzqDnVm+pX7VBQCD9C7 zHMklJ1S7H4o3p6EW4Ow5dDPqlchIuDeqd1UXWqxXzCUkfN0Yrcu7i+KKtrCoAcnBhSr exxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=m34DNNtpMvzZtPYxZvH42oGWZoTO6oa4Hph6YDxvg6A=; fh=55V10LP5MT2YC3CMmeD8ox5TQv4iI1rYZzQqEc55Dnw=; b=nhrcpK7lnbOVlvdOTeWb0Qcc2rR0H6PUJGjrr1oCUncOD0NLugWt4Zn4fnrfgE0QeQ SE23TOpFgGjQMQWrRUxz/UEuGWamD489wwT4NNraPzsd6tUhkWqEM+bBj/9rfGqVbnfh ecJt+RA/P7f4NOHQDlqOjqDrGbAj5AZW92+rVXlh9ZhMYm8thO88B4VBADJjK+qFc6Cn Y0iWbIed7POx62B5iwTO4CjAL1m5+lq0hkz4A8ls19TAtnoethi2Qz/81IKxpMFH9Zgh YxDEaAiOt8HIu5flgmms77Ed+eFzvAlSwj0iDwoaSy7LXBjdKV1MlSXCjP00mmam1Le6 zB3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MUt1n+Fz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020a05600c2e4c00b0040648217f4fsm14460597wmf.39.2023.10.23.09.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 09:15:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Axel Heider , Laszlo Ersek , Ard Biesheuvel , Shannon Zhao , Igor Mammedov , Ani Sinha , "Michael S. Tsirkin" Subject: [PATCH 2/3] hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01] Date: Mon, 23 Oct 2023 17:15:31 +0100 Message-Id: <20231023161532.2729084-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023161532.2729084-1-peter.maydell@linaro.org> References: <20231023161532.2729084-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We're going to make the second UART not always a secure-only device. Rename the constants VIRT_UART and VIRT_SECURE_UART to VIRT_UART0 and VIRT_UART1 accordingly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/hw/arm/virt.h | 4 ++-- hw/arm/virt-acpi-build.c | 12 ++++++------ hw/arm/virt.c | 14 +++++++------- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index f69239850e6..0de58328b2f 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -59,7 +59,7 @@ enum { VIRT_GIC_ITS, VIRT_GIC_REDIST, VIRT_SMMU, - VIRT_UART, + VIRT_UART0, VIRT_MMIO, VIRT_RTC, VIRT_FW_CFG, @@ -69,7 +69,7 @@ enum { VIRT_PCIE_ECAM, VIRT_PLATFORM_BUS, VIRT_GPIO, - VIRT_SECURE_UART, + VIRT_UART1, VIRT_SECURE_MEM, VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9ce136cd88c..54f26640982 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -483,14 +483,14 @@ build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ /* Base Address */ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, - vms->memmap[VIRT_UART].base); + vms->memmap[VIRT_UART0].base); /* Interrupt Type */ build_append_int_noprefix(table_data, (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); build_append_int_noprefix(table_data, 0, 1); /* IRQ */ /* Global System Interrupt */ build_append_int_noprefix(table_data, - vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); + vms->irqmap[VIRT_UART0] + ARM_SPI_BASE, 4); build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */ /* Stop Bits */ @@ -674,11 +674,11 @@ build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) /* BaseAddressRegister[] */ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, - vms->memmap[VIRT_UART].base); + vms->memmap[VIRT_UART0].base); /* AddressSize[] */ build_append_int_noprefix(table_data, - vms->memmap[VIRT_UART].size, 4); + vms->memmap[VIRT_UART0].size, 4); /* NamespaceString[] */ g_array_append_vals(table_data, name, namespace_length); @@ -859,8 +859,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) */ scope = aml_scope("\\_SB"); acpi_dsdt_add_cpus(scope, vms); - acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], - (irqmap[VIRT_UART] + ARM_SPI_BASE)); + acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], + (irqmap[VIRT_UART0] + ARM_SPI_BASE)); if (vmc->acpi_expose_flash) { acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b714ff1c03d..fd524aed6b6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -144,11 +144,11 @@ static const MemMapEntry base_memmap[] = { [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, /* This redistributor space allows up to 2*64kB*123 CPUs */ [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, - [VIRT_UART] = { 0x09000000, 0x00001000 }, + [VIRT_UART0] = { 0x09000000, 0x00001000 }, [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, - [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, + [VIRT_UART1] = { 0x09040000, 0x00001000 }, [VIRT_SMMU] = { 0x09050000, 0x00020000 }, [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, @@ -191,11 +191,11 @@ static MemMapEntry extended_memmap[] = { }; static const int a15irqmap[] = { - [VIRT_UART] = 1, + [VIRT_UART0] = 1, [VIRT_RTC] = 2, [VIRT_PCIE] = 3, /* ... to 6 */ [VIRT_GPIO] = 7, - [VIRT_SECURE_UART] = 8, + [VIRT_UART1] = 8, [VIRT_ACPI_GED] = 9, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ @@ -889,7 +889,7 @@ static void create_uart(const VirtMachineState *vms, int uart, qemu_fdt_setprop(ms->fdt, nodename, "clock-names", clocknames, sizeof(clocknames)); - if (uart == VIRT_UART) { + if (uart == VIRT_UART0) { qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); } else { @@ -2269,11 +2269,11 @@ static void machvirt_init(MachineState *machine) fdt_add_pmu_nodes(vms); - create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); + create_uart(vms, VIRT_UART0, sysmem, serial_hd(0)); if (vms->secure) { create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); - create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q12-20020a05600c2e4c00b0040648217f4fsm14460597wmf.39.2023.10.23.09.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 09:15:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Axel Heider , Laszlo Ersek , Ard Biesheuvel , Shannon Zhao , Igor Mammedov , Ani Sinha , "Michael S. Tsirkin" Subject: [PATCH 3/3] hw/arm/virt: allow creation of a second NonSecure UART Date: Mon, 23 Oct 2023 17:15:32 +0100 Message-Id: <20231023161532.2729084-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023161532.2729084-1-peter.maydell@linaro.org> References: <20231023161532.2729084-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For some use-cases, it is helpful to have more than one UART available to the guest. If the second UART slot is not already used for a TrustZone Secure-World-only UART, create it as a NonSecure UART only when the user provides a serial backend (e.g. via a second -serial command line option). This avoids problems where existing guest software only expects a single UART, and gets confused by the second UART in the DTB. The major example of this is older EDK2 firmware, which will send the GRUB bootloader output to UART1 and the guest serial output to UART0. Users who want to use both UARTs with a guest setup including EDK2 are advised to update to a newer EDK2. TODO: give specifics of which EDK2 version has this fix, once the patches which fix EDK2 are upstream. Inspired-by: Axel Heider Signed-off-by: Peter Maydell Tested-by: Laszlo Ersek --- This patch was originally based on the one from Axel Heider that aimed to do the same thing: https://lore.kernel.org/qemu-devel/166990501232.22022.16582561244534011083-1@git.sr.ht/ but by the time I had added the ACPI support and dealt with the EDK2 compatibility awkwardness, I found I had pretty much rewritten it. So this combination of author and tags seemed to me the most appropriate, but I'm happy to adjust if people (esp. Axel!) would prefer otherwise. It is in theory possible to slightly work around the incorrect behaviour of old EDK2 binaries by listing the two UARTs in the opposite order in the DTB. However since old EDK2 ends up using the two UARTs in different orders depending on which phase of boot it is in (and in particular with EDK2 debug builds debug messages go to a mix of both UARTs) this doesn't seem worthwhile. I think most users who are interested in the second UART are likely to be using a bare-metal or direct Linux boot anyway. --- docs/system/arm/virt.rst | 6 +++++- include/hw/arm/virt.h | 1 + hw/arm/virt-acpi-build.c | 12 ++++++++---- hw/arm/virt.c | 38 +++++++++++++++++++++++++++++++++++--- 4 files changed, 49 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e1697ac8f48..028d2416d5b 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -26,7 +26,7 @@ The virt board supports: - PCI/PCIe devices - Flash memory -- One PL011 UART +- Either one or two PL011 UARTs for the NonSecure World - An RTC - The fw_cfg device that allows a guest to obtain data from QEMU - A PL061 GPIO controller @@ -48,6 +48,10 @@ The virt board supports: - A secure flash memory - 16MB of secure RAM +The second NonSecure UART only exists if a backend is configured +explicitly (e.g. with a second -serial command line option) and +TrustZone emulation is not enabled. + Supported guest CPU types: - ``cortex-a7`` (32-bit) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 0de58328b2f..da15eb342bd 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -150,6 +150,7 @@ struct VirtMachineState { bool ras; bool mte; bool dtb_randomness; + bool second_ns_uart_present; OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 54f26640982..b812f33c929 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -77,11 +77,11 @@ static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) } static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, - uint32_t uart_irq) + uint32_t uart_irq, int uartidx) { - Aml *dev = aml_device("COM0"); + Aml *dev = aml_device("COM%d", uartidx); aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(uartidx))); Aml *crs = aml_resource_template(); aml_append(crs, aml_memory32_fixed(uart_memmap->base, @@ -860,7 +860,11 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) scope = aml_scope("\\_SB"); acpi_dsdt_add_cpus(scope, vms); acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], - (irqmap[VIRT_UART0] + ARM_SPI_BASE)); + (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0); + if (vms->second_ns_uart_present) { + acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1], + (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1); + } if (vmc->acpi_expose_flash) { acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index fd524aed6b6..7f60df7d7b2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -856,7 +856,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) } static void create_uart(const VirtMachineState *vms, int uart, - MemoryRegion *mem, Chardev *chr) + MemoryRegion *mem, Chardev *chr, bool secure) { char *nodename; hwaddr base = vms->memmap[uart].base; @@ -894,6 +894,8 @@ static void create_uart(const VirtMachineState *vms, int uart, qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); } else { qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); + } + if (secure) { /* Mark as not usable by the normal world */ qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); @@ -2269,11 +2271,41 @@ static void machvirt_init(MachineState *machine) fdt_add_pmu_nodes(vms); - create_uart(vms, VIRT_UART0, sysmem, serial_hd(0)); + /* + * The first UART always exists. If the security extensions are + * enabled, the second UART also always exists. Otherwise, it only exists + * if a backend is configured explicitly via '-serial '. + * This avoids potentially breaking existing user setups that expect + * only one NonSecure UART to be present (for instance, older EDK2 + * binaries). + * + * The nodes end up in the DTB in reverse order of creation, so we must + * create UART0 last to ensure it appears as the first node in the DTB, + * for compatibility with guest software that just iterates through the + * DTB to find the first UART, as older versions of EDK2 do. + * DTB readers that follow the spec, as Linux does, should honour the + * aliases node information and /chosen/stdout-path regardless of + * the order that nodes appear in the DTB. + * + * For similar back-compatibility reasons, if UART1 is the secure UART + * we create it second (and so it appears first in the DTB), because + * that's what QEMU has always done. + */ + if (!vms->secure) { + Chardev *serial1 = serial_hd(1); + + if (serial1) { + vms->second_ns_uart_present = true; + create_uart(vms, VIRT_UART1, sysmem, serial1, false); + } + } + create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false); + if (vms->secure) { + create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true); + } if (vms->secure) { create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); - create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1)); } if (tag_sysmem) {