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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/24] hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder Date: Thu, 19 Oct 2023 14:35:14 +0100 Message-Id: <20231019133537.2114929-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth The file is obviously related to the raspberrypi machine, so it should reside in hw/arm/ instead of hw/misc/. And while we're at it, also adjust the wildcard in MAINTAINERS so that it covers this file, too. Signed-off-by: Thomas Huth Reviewed-by: Alex Bennée Acked-by: Philippe Mathieu-Daudé Message-id: 20231012073458.860187-1-thuth@redhat.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 +- include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0 hw/misc/bcm2835_property.c | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 9bd4fe378d4..9282b4b0f55 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -885,7 +885,7 @@ S: Odd Fixes F: hw/arm/raspi.c F: hw/arm/raspi_platform.h F: hw/*/bcm283* -F: include/hw/arm/raspi* +F: include/hw/arm/rasp* F: include/hw/*/bcm283* F: docs/system/arm/raspi.rst diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/arm/raspberrypi-fw-defs.h similarity index 100% rename from include/hw/misc/raspberrypi-fw-defs.h rename to include/hw/arm/raspberrypi-fw-defs.h diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 4ed9faa54a1..ff55a4e2cd2 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -12,7 +12,7 @@ #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/misc/bcm2835_mbox_defs.h" -#include "hw/misc/raspberrypi-fw-defs.h" +#include "hw/arm/raspberrypi-fw-defs.h" #include "sysemu/dma.h" #include "qemu/log.h" #include "qemu/module.h" From patchwork Thu Oct 19 13:35:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735564 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519447wro; Thu, 19 Oct 2023 06:36:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGv+oWR+29aJXKjq2SoCysI6i47zEdvJHKuihDE5uyFH+dZOR4vD+wvxRvVGm637FzK5Vbf X-Received: by 2002:a25:8b08:0:b0:d9a:c204:9cf2 with SMTP id i8-20020a258b08000000b00d9ac2049cf2mr2083694ybl.5.1697722593501; Thu, 19 Oct 2023 06:36:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722593; cv=none; d=google.com; s=arc-20160816; b=tf70WEjzCE9CLoXwoPmivcIMOT2rC0vTmc0Q/SHoUnauaItbCF/tnAo1nS6/3g2Vyy oWjvJlnIbj3kssP3EDDefWZkBBdQopS0lXzElZh74lb0Pv1sYObbkft+x9C3vTEe3zPd 0itJmTZS1LyGMtSSgeCVP9g1kk/QDdD7WL0t0BojF05SFJRhrEG0//WwdaynH3STBsbF K3UbK18BEQQSq2wXQXz2olDrOBqa81Fd+cKZZkocStTyMkRPs7TQrTgJcfroh2qy9nde ovaSWPWT3x9vwTy/adaRpdxDETdYFAhrx5WkCaiZRvlVOavRhcygV4/jI4IrM4Wo6x4k 5W1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J9OnLBnDoo/08QPEMHukIoyH0/rkRW/kfDrQtjUrlpQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=gCFc+B3ZsCUJdlEUEEF/sMYn56l8tCwfdrMNJnCpSDcxdBE+6d9UJL8/a6BeQ01GfB uTvrkLohnd3oHe4Kh4T3AoJo4QoYqG/6XMn+9VHIRyLtH0dYlRyBiL3s7JuqdVpRkQU9 LptIDZ1x3R1sJ0ljVCOWPOUjrFEw+yE4vnBb/ogdJDw2ky0G27kpy91mP4OM/FKo34rE h6AUYbVRi86OZhhW2pgrzRJtowVd3CL6h9HafnMyVWh7hQ+KxgjcqX+EAK43R4HBCn0X CsVBn3CLmgcms9Ww1snBslGR05UNkXnGgjNvCAlphunHfXXgMDZpfvi76Rj7g1Xtu68A uRyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ntw4t4pe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/24] hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h' Date: Thu, 19 Oct 2023 14:35:15 +0100 Message-Id: <20231019133537.2114929-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé struct arm_boot_info is declared in "hw/arm/boot.h". By including the correct header we don't need to declare it again in "target/arm/cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231013130214.95742-1-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/exynos4210.h | 2 +- target/arm/cpu-qom.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 68db19f0cb7..d33fe385865 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -30,7 +30,7 @@ #include "hw/intc/exynos4210_gic.h" #include "hw/intc/exynos4210_combiner.h" #include "hw/core/split-irq.h" -#include "target/arm/cpu-qom.h" +#include "hw/arm/boot.h" #include "qom/object.h" #define EXYNOS4210_NCPUS 2 diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 514c22ced9b..d06c08a734e 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -23,8 +23,6 @@ #include "hw/core/cpu.h" #include "qom/object.h" -struct arm_boot_info; - #define TYPE_ARM_CPU "arm-cpu" OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) From patchwork Thu Oct 19 13:35:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735571 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519977wro; Thu, 19 Oct 2023 06:37:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHn+MdH7AU9fnaA8WJDdUFasA3DyioxT3N9e3+xBv0HGiuUrsDLAjcYZkFCUNFovuMrakx1 X-Received: by 2002:a05:6808:a81:b0:3b2:bc91:cbc3 with SMTP id q1-20020a0568080a8100b003b2bc91cbc3mr2023072oij.50.1697722658023; Thu, 19 Oct 2023 06:37:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722657; cv=none; d=google.com; s=arc-20160816; b=apSSTpVIb5/P5jx/LeJKZreRhPNoyO/NKwTFEfC0sT8OqPrZFVAQwF2N1nXFeZET1a eCWi4oK8dXptSX2vKXjAOR/MH70EvPrjWkT6HgVArxT1kZDqncaPa1B4lG8n0iIXEz1t bCSLEevgiuSZoczYnZ06IruOO/eO55fl8lgZ3PV/OTAJtm7UvUWrwq3dqKDVyZspfii9 SOs+JTQtcGkxJnJtHMukB/Yb27JbwSM0Du8R315p3FmYTT1byyhidQUBwqVIXpgrc2Eq mDuTbaGxcfvpkpwUXThjKIVgox1OeQUl82uJIeh19HxGVgpjqCdBgQZ++4DZ8Kw7RIvf 2ebQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IBNdIJqab6Bc866cHoB7OouTeU7VDOxNyDZhbOToj3g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=C7dpYHMYoSrnvRnDhoq5BavkofmmXVJez6pTPBNal0K/2/WGYIQUNRr5ajxQMdtRzS 3qSo8NJyxXP+zue71NGiwAUXgPys7xogcIPWGff2nl2h1mp9IF6nLOC7XSVnN3UvbUTB 3xNkTk/ZiI7ZXjJRZ9+yDYIjaYC9ChD/p7mb6UYE+EkigSQ1RnOOAgDlfXFPjgT/akk8 bIk6EVDkeTdayRA8iyDlGx5Bgrv5aeRUU9pRCt4XBwp9lT/e0NtmL828CBvS6V9UGHR1 c2WD5QgMG/DNqQxmtjODtuwZGJTcepJrU2gKwDIkmyCuaJHUJsmCqPRutanTK8SQrqzz tfHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P2eb2tv4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/24] xlnx-bbram: hw/nvram: Remove deprecated device reset Date: Thu, 19 Oct 2023 14:35:16 +0100 Message-Id: <20231019133537.2114929-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Tong Ho This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231003052345.199725-1-tong.ho@amd.com Signed-off-by: Peter Maydell --- hw/nvram/xlnx-bbram.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c index c6b484cc85b..e18e7770e1e 100644 --- a/hw/nvram/xlnx-bbram.c +++ b/hw/nvram/xlnx-bbram.c @@ -2,6 +2,7 @@ * QEMU model of the Xilinx BBRAM Battery Backed RAM * * Copyright (c) 2014-2021 Xilinx Inc. + * Copyright (c) 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -416,9 +417,9 @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = { } }; -static void bbram_ctrl_reset(DeviceState *dev) +static void bbram_ctrl_reset_hold(Object *obj) { - XlnxBBRam *s = XLNX_BBRAM(dev); + XlnxBBRam *s = XLNX_BBRAM(obj); unsigned int i; for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { @@ -522,8 +523,9 @@ static Property bbram_ctrl_props[] = { static void bbram_ctrl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - dc->reset = bbram_ctrl_reset; + rc->phases.hold = bbram_ctrl_reset_hold; dc->realize = bbram_ctrl_realize; dc->vmsd = &vmstate_bbram_ctrl; device_class_set_props(dc, bbram_ctrl_props); From patchwork Thu Oct 19 13:35:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735580 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1521336wro; Thu, 19 Oct 2023 06:40:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGa4IBj6E7DXkg/b2Zw4HTGb/uaz3A5DrQJlabc7toGOOe0ClHWiQhUXE5uCfCsCs1Hn1sF X-Received: by 2002:a05:6808:30a4:b0:3af:709c:1b2b with SMTP id bl36-20020a05680830a400b003af709c1b2bmr2563386oib.32.1697722836145; Thu, 19 Oct 2023 06:40:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722836; cv=none; d=google.com; s=arc-20160816; b=C2+hlSiSf5t9uFK+0jXQzmaRMuuenPooFXGRkr2AXnv4GcXIYGd+kwLuQWCRoazyG7 uul06t73lpSQF31lO4Ba9SSRpFsmbcQJPN8H/XLGGv6L5h1XNSarKDCZtoqOYexNly5z i4u9zbOQdUtHCZup26ZKJDZ5EyOM8RDt/k13M1mWMMGSKEPkx2G9rhUIG3bvxAE1Hbk0 54wVx5xBDFtw2V3wAKRs9UeqKYKG568R3tCbzFhpdVLMltW24yL0cjdVg1z6wRPCOod3 s77be6P4tkdWdNG6Zqj/HqMFngK1lRAOD3M4agcMRHCFJf317xY+nzMS+c0S0NQ/sXP0 ythA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ICHuBkhBDHp2nAsvOB6Lae37rGAGJ+oc5E/gIMwOSBg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=nW/flD4c4JS57ntWaQjKIjancx1DAaMDE0cHwbzsupPDt2RnZJSWL+spWYm9WKZqKj iIsGlB78WkQcsDgrLcGnaFORzJGmCW58m/QiRIqv2+jJrXjluGHFYcErkYKxRJ2CnbuW c/6DOtMPZnXfXnUzc8IKVK729W+Rj606lJ5eqWU0FIJv2bLwa9SzNVTsYVgFGW3dvecW O8CUQTBAFVtCiX6Kqrpb0M1RWDRu2GIQIvmYqFaEvpim8moaHUvpsJA2LNRgvW/czBIS c1bLTWOKnxVtk9IYZwIA6pKsICwjN6oeniTjTwTNA24pIjOI2Te7WlnvZiNGY3sfCVyK 5bZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="i27D//zs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/24] xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset Date: Thu, 19 Oct 2023 14:35:17 +0100 Message-Id: <20231019133537.2114929-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Tong Ho This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho Reviewed-by: Francisco Iglesias Message-id: 20231004055713.324009-1-tong.ho@amd.com Signed-off-by: Peter Maydell --- hw/nvram/xlnx-zynqmp-efuse.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c index 228ba0bbfaf..3db5f98ec1a 100644 --- a/hw/nvram/xlnx-zynqmp-efuse.c +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -2,6 +2,7 @@ * QEMU model of the ZynqMP eFuse * * Copyright (c) 2015 Xilinx Inc. + * Copyright (c) 2023 Advanced Micro Devices, Inc. * * Written by Edgar E. Iglesias * @@ -769,9 +770,9 @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg) register_reset(reg); } -static void zynqmp_efuse_reset(DeviceState *dev) +static void zynqmp_efuse_reset_hold(Object *obj) { - XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev); + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj); unsigned int i; for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { @@ -837,8 +838,9 @@ static Property zynqmp_efuse_props[] = { static void zynqmp_efuse_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - dc->reset = zynqmp_efuse_reset; + rc->phases.hold = zynqmp_efuse_reset_hold; dc->realize = zynqmp_efuse_realize; dc->vmsd = &vmstate_efuse; device_class_set_props(dc, zynqmp_efuse_props); From patchwork Thu Oct 19 13:35:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735574 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1520264wro; Thu, 19 Oct 2023 06:38:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IELczCgnoVg0oK2u+dDrB0y7Lo+yH9ccHW1u+sMT4468zlaHaSNe/bqZD4q/bWC8vKkqgS1 X-Received: by 2002:a05:6122:1da6:b0:495:c10c:ec39 with SMTP id gg38-20020a0561221da600b00495c10cec39mr2379474vkb.2.1697722692175; Thu, 19 Oct 2023 06:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722692; cv=none; d=google.com; s=arc-20160816; b=aOShzy2nQDA42+OqCwQPRd7oHEiAtCbOHWznQTmqxdJoCtbvUowrBe/ZVEuzV5uypQ E30wS10Kp/qpyf9rn7pzqsqNSq+U/pqGhhwDzMFjofC9qD7Cb8xVAIwZW+3P/CV0O4S6 M11KQNQI4bIMqO6Nz45Sie0fSgjP4nvuxKsCtn52m90BoRofzJ90+S44qrYh2rRzyVzf ZJbCPE5p/16nsCtSkVYizjNHVcc2USVfuFW4A8wuvfJ2+tt0dZIcN8KI/xn0L902Ey8S cAUgifQEL0nhQCQ7MNT/tuOl/cWsTy6VrrWyjZN8HbHjbS0wdZbdMjHGxO+kSspFyjG5 jwjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wgV06AYPc/Ma/kmEzls3TmWz3gALsYetmR08HC+n1XI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UJPvw2OkJ4cshQ9F773sYmv3wwm1XBYTRMiJ6DRHGV/BVY8BpyHGqovtuEdQDgI6cp dDs1l1eA+U4NM5DqigXj+qi3lg5Ndi/DvHVMYZ1pgfV4ozfl20cz0Veothl8bXclmdpq ROd1EMTG78uojfcXyChVwGoh2/B4HvhVpyiY1HwPaAWtXx3TgXL51p6yyht3iIPp4Avx fQ4pBiC3B8jK+IGfYBm/nKwJUKoeYvpfYwO01ZmwdN3t8b0xorbusKN+b8y4vsruakzn q/7agmWFE3mLmyeMbbHIoCJwKpJDLhA9QghBjH/3vDGjLWYrAE1HBO1GJrL+ql92rE5m m95g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XtrOpMPI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/24] xlnx-versal-efuse: hw/nvram: Remove deprecated device reset Date: Thu, 19 Oct 2023 14:35:18 +0100 Message-Id: <20231019133537.2114929-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Tong Ho This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho Reviewed-by: Francisco Iglesias Message-id: 20231004055339.323833-1-tong.ho@amd.com Signed-off-by: Peter Maydell --- hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c index b35ba65ab57..beb5661c35f 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -2,6 +2,7 @@ * QEMU model of the Versal eFuse controller * * Copyright (c) 2020 Xilinx Inc. + * Copyright (c) 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -657,9 +658,9 @@ static void efuse_ctrl_register_reset(RegisterInfo *reg) register_reset(reg); } -static void efuse_ctrl_reset(DeviceState *dev) +static void efuse_ctrl_reset_hold(Object *obj) { - XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev); + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); unsigned int i; for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { @@ -749,8 +750,9 @@ static Property efuse_ctrl_props[] = { static void efuse_ctrl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - dc->reset = efuse_ctrl_reset; + rc->phases.hold = efuse_ctrl_reset_hold; dc->realize = efuse_ctrl_realize; dc->vmsd = &vmstate_efuse_ctrl; device_class_set_props(dc, efuse_ctrl_props); From patchwork Thu Oct 19 13:35:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735581 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1521348wro; Thu, 19 Oct 2023 06:40:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEhaosNV7pPGPp4XrkXUJNlOxwV2bZuJe4j2iQIYDw4m/hw9Vj58AUZi4lPMD5kR4buK9bA X-Received: by 2002:a05:6122:308e:b0:48d:b7c:56c8 with SMTP id cd14-20020a056122308e00b0048d0b7c56c8mr2285506vkb.0.1697722837275; Thu, 19 Oct 2023 06:40:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722837; cv=none; d=google.com; s=arc-20160816; b=Ax9c/d5H4bSFqH1qLPWkHJYWVD004MLourXwLRrRO5IqjialBGBv31Y/GEeL/CXVZ+ r6lu95UdSk2EoHd5k3fePTyrWcGAg+ahW+A8o8yGeSsGtYl15t2UhNPZbf89EaMlqu2B qWyyolgP8TkarTgvFql7JulAG5DqFVOrnVPp559+fBf3A8qn0K0OLeilzkDDvhlbsKpw 9gV6lRWCtFPoAJw3jcXrntkgAC0qXgabF2ZkDsLTuXc73TzlQkqwHrfNd7K6QewRIA8n kq5CG+5VXJVSSAHT+Ozvn6PlcMSFK+zb3B89D8Fi69XI6ZkBq2VhnPw0+9/UWLwA8BDt R9WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=980RYNOEtgl+U05wTxrGNkJ8Z29zZamfuIhgBMTwwfM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=v1PcI8XnDLhFm8h1jbCjN5wvK63fEj2YB/O1a3s/toab+ZT4F7jY8zjepNIMz+VSdi w+z2LWw84k9QJ5bhp82Vvn8c7qNC8yarralPHUox5eX6172Frd5qFfP1wCdQUofFDq0C pS4227n+Y+N+hF/+jI5DhywjCFznZmmMbb5K6538mU26mK//tfqDP0UFPVjHv3GzfXR/ BcXuaQUeUBgSzxhE4FlffGtEZB3x7uVUWNY1+ySeSD6vLrvorF0yV0Na2kgHiIas5Tnx zR0U75WIyNsV2hcwsbqGeRpEgD91WFaNG2In4hRt09Sd6jhYUosWBeOdE510NFqzsZ5R 6P+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gR1FPoc4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/24] xlnx-bbram: hw/nvram: Use dot in device type name Date: Thu, 19 Oct 2023 14:35:19 +0100 Message-Id: <20231019133537.2114929-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Tong Ho This replaces the comma (,) to dot (.) in the device type name so the name can be used with the 'driver=' command line option. Signed-off-by: Tong Ho Reviewed-by: Francisco Iglesias Message-id: 20231003052139.199665-1-tong.ho@amd.com Signed-off-by: Peter Maydell --- include/hw/nvram/xlnx-bbram.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h index 87d59ef3c0c..6fc13f8cc17 100644 --- a/include/hw/nvram/xlnx-bbram.h +++ b/include/hw/nvram/xlnx-bbram.h @@ -34,7 +34,7 @@ #define RMAX_XLNX_BBRAM ((0x4c / 4) + 1) -#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl" +#define TYPE_XLNX_BBRAM "xlnx.bbram-ctrl" OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM); struct XlnxBBRam { From patchwork Thu Oct 19 13:35:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735573 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1520243wro; Thu, 19 Oct 2023 06:38:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWt76P+j8l7y/XsvtL+bkO5C8ONCLiM4iV2PeI8F2DvuSbqM7/sH520AJZedvctjp4XN2b X-Received: by 2002:a05:622a:1209:b0:41b:7738:a8cf with SMTP id y9-20020a05622a120900b0041b7738a8cfmr2529195qtx.17.1697722689461; Thu, 19 Oct 2023 06:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722689; cv=none; d=google.com; s=arc-20160816; b=fBDZvZaAoZfE6s8QhoREyaTsILBj1Rk3DrWxie1oGBclB5rFyeT122NgjBQtCI+pVn g1o5wjASU8OpLxsjdyDK8yfFcWe7PllXHrwwyOQQ/vSyA+z94CSWN9O2DfU8q228O2OJ RWbUy+aSlp6UQYRPDnMsuPJHeMXEJibCm6KNtN6MzuOov8fAosFnV/Cfq9NAM1ADvRtB R+Q7hvRTHwP4RIdBNM1OmN0O56c1Dbhu5FF/6lv1cxFkF1rwrJtFVzzCetBuJiJy2XHx UxtSC1m/lsqFKBiyFWN18kckUPpsfM9CMliYIbCHKhkElDwlGucJyvUGaeTLm692iG45 peeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g9r6zIkMYz7JcnSG+rRRxCK1RkPWO1zbCKf8oqt+HSA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=hlD8TIh0PF38vgcE50r10ucxL4QKqBSfRDS2tQCDZtEAsvDfynSPeTFRUOLniUXrB+ 8tOg/GKCtHeX6/sEceChxzGDJtzqJw78GGGsQ7949qipciA0QxKeoE8onO2WA5SIz122 tt+QhxsiO0/YBlevQfh6H40wC2Ys+z41Eq3Ygy4NTVu32qp6BJonrGnrgN8HBo9Q56ea Ld7VQYnZEQimlSdlwahkZYF0Wv3CNQfkULowt1kqOtmSX6fxiUpO5EeRu952Wr6ffTY7 kgorTdv9nCXeRkro2uNAU9ti77m0sCEq4P+O6chFAKgodi6GqLNt9kYrUbGmjeoJXhoV pNZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FyPoHSuY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/24] elf2dmp: limit print length for sign_rsds Date: Thu, 19 Oct 2023 14:35:20 +0100 Message-Id: <20231019133537.2114929-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Viktor Prutyanov String sign_rsds isn't terminated, so the print length must be limited. Fixes: Coverity CID 1521598 Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Message-id: 20230930235317.11469-2-viktor@daynix.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c index 5db163bdbe8..6de5c9808ef 100644 --- a/contrib/elf2dmp/main.c +++ b/contrib/elf2dmp/main.c @@ -478,7 +478,7 @@ static bool pe_check_pdb_name(uint64_t base, void *start_addr, } if (memcmp(&rsds->Signature, sign_rsds, sizeof(sign_rsds))) { - eprintf("CodeView signature is \'%.4s\', \'%s\' expected\n", + eprintf("CodeView signature is \'%.4s\', \'%.4s\' expected\n", rsds->Signature, sign_rsds); return false; } From patchwork Thu Oct 19 13:35:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735565 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519462wro; Thu, 19 Oct 2023 06:36:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLRmdM6/ULIkz7UpZ3FcdZL7ByNwKmHgrN5Bj8ZSnyx8FLghkdwyDxnq1B+Ptrwr1h6KnB X-Received: by 2002:a54:4495:0:b0:3ae:156f:d325 with SMTP id v21-20020a544495000000b003ae156fd325mr1788740oiv.58.1697722595175; Thu, 19 Oct 2023 06:36:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722595; cv=none; d=google.com; s=arc-20160816; b=CQDnnba5pn1rbjpBfbjsupf1MgDwAw5Nyx0+EihfyW3ZyaxjzbPTqDeZq6Fm52g5Q5 5z54jsrXDBHiwdkLgl3doGEhhDiCREfnFNWTr2bANazJ/ciou0vqYU6Wx1g9MTQTTkLu BmEG7odM0neQKlTY5FNoBsf+PlSHij7tt+bztcWnbm/Vk7bGX+UuritvW6vWtewKrXQp qjsohLZTaAskGQdBWaEO28dKSywVqPV7HIBsUYBg6pN2Kq7x9TOc78S/tyaHTDAorLw/ GKMUs8UOXohUfyDYV16nYTzWgTktXRXRU0IhtC41lgni8fEAEKmFSFHOJKASLakUko48 q0rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XDLwNQSP4GKAO/ZxD0EOo3uqYEUKkTNSdvXAsFN5ifk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=lSbLEzVgWZKa3XgE2N+0PKjgYolAzqX5dnX8f+MwrogYb/stNioFex5U4q4j0WvOd8 u9pBXE+U8ER5LgBN6rZH6NjVCmrkj9fJlfFFnC3ZNvIinD2hB3p91B05VuIipUFWUAQd qaeQ4cQ+DeOCtZDQhHiRYBRZ10PE2fFE2JlaWxyjzgZXHIVhXkL58R+Y7tRSNpIwsTDk AOOf8UV/vqVAM23MHV2kkzIMVLWCbNabF6ZP1ggQT0Zbu70WGfUJXTZGAm9jEDEGXM5b zbmiLMYOuwzUrPdruERVSqfV0/0NYEtvs1Nyehn7hEHhP4lG/7cs3b+2ThHtLyDAQFoC HeKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E58V+jJi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/24] elf2dmp: check array bounds in pdb_get_file_size Date: Thu, 19 Oct 2023 14:35:21 +0100 Message-Id: <20231019133537.2114929-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Viktor Prutyanov Index in file_size array must be checked against num_files, because the entries we are looking for may be absent in the PDB. Fixes: Coverity CID 1521597 Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230930235317.11469-3-viktor@daynix.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/pdb.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c index 6ca5086f02e..8e3c18c82f7 100644 --- a/contrib/elf2dmp/pdb.c +++ b/contrib/elf2dmp/pdb.c @@ -25,6 +25,10 @@ static uint32_t pdb_get_file_size(const struct pdb_reader *r, unsigned idx) { + if (idx >= r->ds.toc->num_files) { + return 0; + } + return r->ds.toc->file_size[idx]; } @@ -159,16 +163,17 @@ static void *pdb_ds_read_file(struct pdb_reader* r, uint32_t file_number) static int pdb_init_segments(struct pdb_reader *r) { - char *segs; unsigned stream_idx = r->segments; - segs = pdb_ds_read_file(r, stream_idx); - if (!segs) { + r->segs = pdb_ds_read_file(r, stream_idx); + if (!r->segs) { return 1; } - r->segs = segs; r->segs_size = pdb_get_file_size(r, stream_idx); + if (!r->segs_size) { + return 1; + } return 0; } From patchwork Thu Oct 19 13:35:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735579 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1520762wro; Thu, 19 Oct 2023 06:39:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGtBiPEinlSxehXSXGzgTM0W8B9GvK0taNPlBIhGbsFfhLwqiXtxBAb0HFh7K8zfJXSysz2 X-Received: by 2002:a25:dc54:0:b0:d9a:ea20:7eb6 with SMTP id y81-20020a25dc54000000b00d9aea207eb6mr2502403ybe.38.1697722759574; Thu, 19 Oct 2023 06:39:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722759; cv=none; d=google.com; s=arc-20160816; b=R/3TUgOdjP8Q05GQkM1E+qejpE+ywlrtroxkvZqMscB6R6f0505EoEugGZ0ojFmqDU MBfSh+9ixoA6VNdY2jbhIgoREzXtTYX+Bh9qIQCd1+LEbvu4nLr6qkNKUlu793qeZZyV ACZRfTMfbNe/RIxUIj69pa1CgRN3SjtZ5l6MXvMb2cDAKSfwtM178HDd1gBuekFFNyyZ 9ztPDWDc8+6PFhNdQYehQo+ftQmX9293GB2qbnygY1CKoJi2liWqmt3clRlGRkRXHMX6 3RkTLHX4VUVRt7H701UEXcLv9+NMZgSagVZAXhShrvXUmDlraGLPmFvB1/e6CrGVjIRD bfvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=43lpcz9vl3gP1eW9caBPH21GU6XgpA6looK2xil7svA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LrTWA0ESKVntoZ15XZr2C88TZKErvOCroQv/Xldd7hxjIEA6eFZ2xZ1LXu6AYqYrQA vBlhL3V8CT5OB3Jyz1quyA3SsxI4M9SEfIWS1f5hOUD4smtqrqGoJfqUrceIJLto34vO BYg30HHV0M1sTse/KkZGJSiHh9zUo8bQfYUTufL0PC/Lu28KO3WjCK0nIUfzKlmFNFc5 lGfyOhXdtxZsTRY7DmbIR86MzrUMeIU5pZqimQU3OzBbSYghy/Y/df9LUpKODrg4jslR C2Lqu8Pe+iA82QHNA78dqOrbcwdyCxMn+KICsfiuOGSe7ioqzL22O9MyoQfPDhgT18FR Gv/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WV2D/6kQ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/24] target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0 Date: Thu, 19 Oct 2023 14:35:22 +0100 Message-Id: <20231019133537.2114929-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Michal Orzel On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top of Xen, a trap from EL2 was observed which is something not reproducible on HW (also, Xen does not trap accesses to physical counter). This is because gt_counter_access() checks for an incorrect bit (1 instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2: When HCR_EL2.E2H is 0: - EL1PCTEN, bit [0]: refers to physical counter - EL1PCEN, bit [1]: refers to physical timer registers Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case and fall through to EL1 case, given that after fixing checking for the correct bit, the handling is the same. Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE") Signed-off-by: Michal Orzel Tested-by: Oleksandr Tyshchenko Message-id: 20230928094404.20802-1-michal.orzel@amd.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 74fbb6e1d78..01cd1474565 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2475,22 +2475,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { return CP_ACCESS_TRAP; } - - /* If HCR_EL2. == '10': check CNTHCTL_EL2.EL1PCTEN. */ - if (hcr & HCR_E2H) { - if (timeridx == GTIMER_PHYS && - !extract32(env->cp15.cnthctl_el2, 10, 1)) { - return CP_ACCESS_TRAP_EL2; - } - } else { - /* If HCR_EL2. == 0: check CNTHCTL_EL2.EL1PCEN. */ - if (has_el2 && timeridx == GTIMER_PHYS && - !extract32(env->cp15.cnthctl_el2, 1, 1)) { - return CP_ACCESS_TRAP_EL2; - } - } - break; - + /* fall through */ case 1: /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ if (has_el2 && timeridx == GTIMER_PHYS && From patchwork Thu Oct 19 13:35:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735587 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1522621wro; Thu, 19 Oct 2023 06:42:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEtoKK9WgJBzEVvDWrFVUhBw1oftrkyOO/G7/rbkMpUaXozYUjELj2RyvQKt+AT14L9IVCY X-Received: by 2002:a05:6808:b28:b0:3b2:ec66:d868 with SMTP id t8-20020a0568080b2800b003b2ec66d868mr2029430oij.41.1697722976616; Thu, 19 Oct 2023 06:42:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722976; cv=none; d=google.com; s=arc-20160816; b=FvdIpIWchlvxV+0rEX4kimMaCQpLetty0BSB5L/QvTgrB5nU7Ar/Tt4n3N3oXwW93/ QO5Jq6E/+pRm4A2CUUdjkzOGil5YEGvUP/UavwkgH3CK3opFpnaw8lO7A5crApiwt1ga beh/hQUuUcdyJ3wYFE5G3G+TGCE03OMHmt83G/8L2er45O/6XNArJA9kFbxvyX4nClHT bNiiULdIPUHHTzvG9LsmjEZdOr8RZVTR3mOjMBjhRjii0IHY55FadnFNnHDZg7GnRaJA Z7eswrzBddBGI5PNtHCr4okmedI9fjnqbmGukObXOlTyW12ZuOrvvmG1Cceiz4eGXqbz wZ1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VLzkzH17g3g4aCNQ6TJgXCK/i2o/eb5PrBjVD/MgSis=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Nwzx/hA5AT+i96Hki2Y3SQCIR+UxiMLfS5gqwVbNZlXb8BzWy+LXwjuCpBFeXB5rJK n0edUYL/DHY+Jc6447mRgy3g1UBmcuEkcpoWBAjCaniGmrQPKLc5DcE4jRCH50PPJqt2 3m3xqmo6RkBgPNfsw814QiIQxP8QmeuP+E3aTGJnJPdvzD2+PmDWNhgkJQZ1q3E6jWx3 Hwu/e1mz6jCgjyDcBEkW61hrVtx7VMXhAEC1UhfrUVtb5KHiwUlVQt4Qo92nL/xcvzaJ KwdbTdomSIhY8nQWSwfLpXxWW1fnSyOxcgzxCcwNkygvEdruG/aJ9nkdrxuVbvu5HsfJ p+DQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CQMGVvje; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/24] {include/}hw/arm: refactor virt PPI logic Date: Thu, 19 Oct 2023 14:35:23 +0100 Message-Id: <20231019133537.2114929-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Leif Lindholm GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. As in, PPI0 is INTID16 .. PPI15 is INTID31. Arm's Base System Architecture specification (BSA) lists the mandated and recommended private interrupt IDs by INTID, not by PPI index. But current definitions in virt define them by PPI index, complicating cross referencing. Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value, converting a PPI index to an INTID. Resolve this by redefining the BSA-allocated PPIs by their INTIDs, and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required. Signed-off-by: Leif Lindholm Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 14 +++++++------- hw/arm/virt-acpi-build.c | 12 ++++++------ hw/arm/virt.c | 24 ++++++++++++++---------- 3 files changed, 27 insertions(+), 23 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e1ddbea96be..5704d95736d 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -43,16 +43,16 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 -#define ARCH_GIC_MAINT_IRQ 9 +#define ARCH_GIC_MAINT_IRQ 25 -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 +#define ARCH_TIMER_VIRT_IRQ 27 +#define ARCH_TIMER_S_EL1_IRQ 29 +#define ARCH_TIMER_NS_EL1_IRQ 30 +#define ARCH_TIMER_NS_EL2_IRQ 26 -#define VIRTUAL_PMU_IRQ 7 +#define VIRTUAL_PMU_IRQ 23 -#define PPI(irq) ((irq) + 16) +#define INTID_TO_PPI(irq) ((irq) - 16) /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ #define PVTIME_SIZE_PER_CPU 64 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6b674231c27..9ce136cd88c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -601,21 +601,21 @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) * The interrupt values are the same with the device tree when adding 16 */ /* Secure EL1 timer GSIV */ - build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4); + build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); /* Secure EL1 timer Flags */ build_append_int_noprefix(table_data, irqflags, 4); /* Non-Secure EL1 timer GSIV */ - build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4); + build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); /* Non-Secure EL1 timer Flags */ build_append_int_noprefix(table_data, irqflags | 1UL << 2, /* Always-on Capability */ 4); /* Virtual timer GSIV */ - build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4); + build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); /* Virtual Timer Flags */ build_append_int_noprefix(table_data, irqflags, 4); /* Non-Secure EL2 timer GSIV */ - build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4); + build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); /* Non-Secure EL2 timer Flags */ build_append_int_noprefix(table_data, irqflags, 4); /* CntReadBase Physical address */ @@ -729,9 +729,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); uint64_t physical_base_address = 0, gich = 0, gicv = 0; - uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0; + uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? - PPI(VIRTUAL_PMU_IRQ) : 0; + VIRTUAL_PMU_IRQ : 0; if (vms->gic_version == VIRT_GIC_VERSION_2) { physical_base_address = memmap[VIRT_GIC_CPU].base; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 15e74249f9d..ebc9f3fdb1d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -366,10 +366,14 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) } qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); } static void fdt_add_cpu_nodes(const VirtMachineState *vms) @@ -800,7 +804,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) */ for (i = 0; i < smp_cpus; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); - int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int intidbase = NUM_IRQS + i * GIC_INTERNAL; /* Mapping from the output timer irq lines from the CPU to the * GIC PPI inputs we use for the virt board. */ @@ -814,22 +818,22 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(vms->gic, - ppibase + timer_irq[irq])); + intidbase + timer_irq[irq])); } if (vms->gic_version != VIRT_GIC_VERSION_2) { qemu_irq irq = qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); + intidbase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, irq); } else if (vms->virt) { qemu_irq irq = qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); + intidbase + ARCH_GIC_MAINT_IRQ); sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(vms->gic, ppibase + qdev_get_gpio_in(vms->gic, intidbase + VIRTUAL_PMU_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); @@ -1989,7 +1993,7 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) if (pmu) { assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); if (kvm_irqchip_in_kernel()) { - kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); + kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); } kvm_arm_pmu_init(cpu); } From patchwork Thu Oct 19 13:35:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735568 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519690wro; Thu, 19 Oct 2023 06:37:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH/YgstrAjNxvpreA49REi4GnBWpaCSprXdAGbE0r8EX7cbLaKUtqILUQcJTK8M85alGpP1 X-Received: by 2002:a81:8341:0:b0:5a8:62f2:b602 with SMTP id t62-20020a818341000000b005a862f2b602mr2485100ywf.13.1697722623239; Thu, 19 Oct 2023 06:37:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722623; cv=none; d=google.com; s=arc-20160816; b=LRcdGRP9z93S3YnH/cN2H2Zcf36qpcFLxkN5HeNZ3VnI7tQYV8luqccv+HhF8IYzLg RXagPpjg3cn2c/T+HWhVu1Zp6uk0izW/TbKnauVsqZ3UmxGV/15T0nMACZv0P3A6R4O/ uppOMlHn3wHkHLrKheoksmcokqsXeDyD585Cj0/2X8jed8x4QYuZrz/g4DVDAGjFPrs9 zpISigiry4J0p0YSdDehzIp9/9zlKOazPJyrCgq/9+iA1GO9PvJ11or4c50WCIobTjIk T5IdTo4FvzPRWE0+vSbd6TbHvavlWazg4gW7HJEvJ3T2rJv+bwZ5IanikX3lFsO4QORC VsXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jaJPkRC2677TxNapfidJhq+3vwfk7C6h2dsSgCQaNac=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jnEaqgZyGk+3jdfIGGeaVgP4Rws1kIxOZHAMqj+Kw6kCqdb0oYn3km91Phu1SMXAUJ IRyXRTjGELvKghCvb3ZwOYGSOw9+P5DP7gOeM1crer1FxWDJNZqlRzCno8NPFGAr0itJ b99RFBtrLERDg2cdvdZnMymiYb3QkPXw8HrOw6xiMKxMyUFtp1PVWK5Va198AOmyVuKD 55ZmhapXXQ5KeU7Veq1ixueiWtzVL9tfqyHX88CdS5PyrVtgCcJxTmyIRF4lE2rJ8RCt /DOVaf9Fbt8osGk7M7w79ifR2soFVvs5Iq/5MYQm/AB+NSlvDldNnedZkAExAYI+UHp6 WplA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YNuqeiwV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/24] include/hw/arm: move BSA definitions to bsa.h Date: Thu, 19 Oct 2023 14:35:24 +0100 Message-Id: <20231019133537.2114929-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Leif Lindholm virt.h defines a number of IRQs that are ultimately described by Arm's Base System Architecture specification. Move these to a dedicated header so that they can be reused by other platforms that do the same. Include that header from virt.h to minimise churn. While we're moving the definitions, sort them into numerical order, and add the ARCH_TIMER_NS_EL2_VIRT_IRQ definition used by sbsa-ref and which will eventually be needed by virt also. Signed-off-by: Leif Lindholm Message-id: 20230919090229.188092-3-quic_llindhol@quicinc.com [PMM: Remove unused PPI_TO_INTID macro; sort numerically; add ARCH_TIMER_NS_EL2_VIRT_IRQ] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/bsa.h | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 12 +----------- 2 files changed, 36 insertions(+), 11 deletions(-) create mode 100644 include/hw/arm/bsa.h diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h new file mode 100644 index 00000000000..8eaab603c03 --- /dev/null +++ b/include/hw/arm/bsa.h @@ -0,0 +1,35 @@ +/* + * Common definitions for Arm Base System Architecture (BSA) platforms. + * + * Copyright (c) 2015 Linaro Limited + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + */ + +#ifndef QEMU_ARM_BSA_H +#define QEMU_ARM_BSA_H + +/* These are architectural INTID values */ +#define VIRTUAL_PMU_IRQ 23 +#define ARCH_GIC_MAINT_IRQ 25 +#define ARCH_TIMER_NS_EL2_IRQ 26 +#define ARCH_TIMER_VIRT_IRQ 27 +#define ARCH_TIMER_NS_EL2_VIRT_IRQ 28 +#define ARCH_TIMER_S_EL1_IRQ 29 +#define ARCH_TIMER_NS_EL1_IRQ 30 + +#define INTID_TO_PPI(irq) ((irq) - 16) + +#endif /* QEMU_ARM_BSA_H */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5704d95736d..f69239850e6 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -34,6 +34,7 @@ #include "qemu/notify.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/bsa.h" #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" @@ -43,17 +44,6 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 -#define ARCH_GIC_MAINT_IRQ 25 - -#define ARCH_TIMER_VIRT_IRQ 27 -#define ARCH_TIMER_S_EL1_IRQ 29 -#define ARCH_TIMER_NS_EL1_IRQ 30 -#define ARCH_TIMER_NS_EL2_IRQ 26 - -#define VIRTUAL_PMU_IRQ 23 - -#define INTID_TO_PPI(irq) ((irq) - 16) - /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ #define PVTIME_SIZE_PER_CPU 64 From patchwork Thu Oct 19 13:35:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735577 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1520727wro; Thu, 19 Oct 2023 06:39:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4Vouc0E0/9dkTPkWLkbGM1KxOA5RdjZNr2nXt0MoFB1k7CW51guowP6CFjigHLgiDH5Cq X-Received: by 2002:a05:622a:589:b0:41c:bf1b:3527 with SMTP id c9-20020a05622a058900b0041cbf1b3527mr1980647qtb.51.1697722756598; Thu, 19 Oct 2023 06:39:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722756; cv=none; d=google.com; s=arc-20160816; b=umoYP7Mk7vfmFuemD9k17wOpGfDNtVR+7GzcUBOGgDWXwP0hLAo6qfi3XWjmDt4gik XwnzjtlJEmg5LcoFU2mfeOMTMSkG8xCTEc1S9D2YX3UF1qJTukt9ZogMDwnpm+XoIe2T sdBGn8S9LeyFvRbZQtCuGaEC6MLX4wvvmZhSWPNVG/xA1eBhigNNE6q037Cy9O2BzjSg zMxkmvH5EjIBpACJabnn9ulVlK20ceeoefngzDS4XPe3tIdvwJU/KqqWMX/DHxEigq4h YEsLyUJidjWVNjaMB5bcIjsRQSJUBpdhrfVCFVnOw8K35c4bw9cFQitT5zXPIIIHlP0w v0dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NdZbt+1sSHwtsO7gY0q3tnj/BPqK0sWsSu3jh1jJfxY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=WrfJxt6Ohaj+P1MDmyy8hDhbVX+iKHJsBG/3KwENzdZJZd+vrjtxxKd8rN77rMkmw+ H25K5Ank2Gfc8M2e5JN8UUD5fVpMfxGIn0fZZkVDRTWHympa8DhKeGiHuJvUlw2Mfkzz DBRXmy6vlWXH/dBmt6JRrJXwmBrkLc+Lrz10MLa5ShZUJOS/+UR5ZJZrwk/VfswylfT+ nEg5g4blYt+aAedsjypYIdbBYIPZLEVlHJWzx59Eg5BFNysnxitgkgoo7+ATFnqWXyFc ItAO3A8nHGg/zkCu3m9HS9AsFJM0ML/7SiTao+xU3MW81pVj71cczuGeMRNa+NG8+ISc NIng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qz557kmh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/24] hw/arm/sbsa-ref: use bsa.h for PPI definitions Date: Thu, 19 Oct 2023 14:35:25 +0100 Message-Id: <20231019133537.2114929-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Leif Lindholm Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use the INTIDs defined there instead of the PPI# used previously. Signed-off-by: Leif Lindholm Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 3c7dfcd6dc5..e8a82618f0a 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -2,6 +2,7 @@ * ARM SBSA Reference Platform emulation * * Copyright (c) 2018 Linaro Limited + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Written by Hongbo Zhang * * This program is free software; you can redistribute it and/or modify it @@ -30,6 +31,7 @@ #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" +#include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" #include "hw/block/flash.h" @@ -55,14 +57,6 @@ #define NUM_SMMU_IRQS 4 #define NUM_SATA_PORTS 6 -#define VIRTUAL_PMU_IRQ 7 -#define ARCH_GIC_MAINT_IRQ 9 -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 -#define ARCH_TIMER_NS_EL2_VIRT_IRQ 12 - enum { SBSA_FLASH, SBSA_MEM, @@ -479,7 +473,7 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) */ for (i = 0; i < smp_cpus; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); - int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int intidbase = NUM_IRQS + i * GIC_INTERNAL; int irq; /* * Mapping from the output timer irq lines from the CPU to the @@ -496,14 +490,17 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(sms->gic, - ppibase + timer_irq[irq])); + intidbase + timer_irq[irq])); } qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, - qdev_get_gpio_in(sms->gic, ppibase + qdev_get_gpio_in(sms->gic, + intidbase + ARCH_GIC_MAINT_IRQ)); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(sms->gic, ppibase + qdev_get_gpio_in(sms->gic, + intidbase + VIRTUAL_PMU_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); From patchwork Thu Oct 19 13:35:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735582 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1521356wro; Thu, 19 Oct 2023 06:40:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGyNH8UCz10yKBZcEQ8PPdDHtHzISHWj0c+dQtv+AzmXJV/ne7QTR/Kbg7iDko1joC9//x7 X-Received: by 2002:a67:e01a:0:b0:457:82be:6782 with SMTP id c26-20020a67e01a000000b0045782be6782mr1833939vsl.9.1697722838713; Thu, 19 Oct 2023 06:40:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722838; cv=none; d=google.com; s=arc-20160816; b=H0xC5UXkIwNl9EbkqQ4UjY/W6R37ZTA7v09tdwjnyYngUkBD4IrgY24+BEJIOPJan6 IGUy2p98XARBQSsRqlUEBJlnbq7AMKck4YvLn4alokBAZwhPOnkQ6iw5t4xqQe151qkX /ZqWKYYFl66j9KG2jrtTdwzrpphkIdGtVRcTZHpZt2/CttvaMEWAEhibv8u9eoxDvpwl JPJ0xOM/7NTNfJ3yOPp56RxgxIt9jcga7I40Xy37ufjajNKE8qwlkhplZGyaJTMDsaCP 98KjtNxSaLz1NpKOd8iI6JPHsJj2PCjMfzixrARa0xmEBozb9bQjaof72rnkMB9/kfro k8iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JjwEGCnWRdnzpw2/wu0zwaRKL9Af9lEaMljStQ4GHxU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LmTSeAHBF88J4ZrLLOv+iJuRFbB5195DDKGe3z0aRVdkbRtEvcgtaF/YjXiJVLzhYc Pv+XEVVSBAvgvokLvOgugbjCzmRykU+5HDjDDoUmRuhRzs/OiX2py4texKZzOEWKHfqd wCq42lB5t7I1mTEuRkjm2AVgJTDeekCousky5Tn5OsLbI5QsppZE4frrfZQ/coax6xcY S+5fmWn6deFlDaod28/XHXPStb8TSV+QfEV0/bCNqSSy48ptwZH+goKeDCmmIHcLEFoO F70eDk12qhscZb/RTn09TeT74ZfNymWFSA1VGazVe4OaZ4RHL8cMnIP3lVqXy6xFRfcJ h4Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VOPlsts7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/24] arm/kvm: convert to kvm_set_one_reg Date: Thu, 19 Oct 2023 14:35:26 +0100 Message-Id: <20231019133537.2114929-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Cornelia Huck We can neaten the code by switching to the kvm_set_one_reg function. Reviewed-by: Gavin Shan Signed-off-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231010142453.224369-2-cohuck@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm.c | 13 +++------ target/arm/kvm64.c | 66 +++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b66b936a958..1a8084c4601 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -589,7 +589,6 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) bool ok = true; for (i = 0; i < cpu->cpreg_array_len; i++) { - struct kvm_one_reg r; uint64_t regidx = cpu->cpreg_indexes[i]; uint32_t v32; int ret; @@ -598,19 +597,17 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) continue; } - r.id = regidx; switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: v32 = cpu->cpreg_values[i]; - r.addr = (uintptr_t)&v32; + ret = kvm_set_one_reg(cs, regidx, &v32); break; case KVM_REG_SIZE_U64: - r.addr = (uintptr_t)(cpu->cpreg_values + i); + ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); break; default: g_assert_not_reached(); } - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { /* We might fail for "unknown register" and also for * "you tried to set a register which is constant with @@ -731,17 +728,13 @@ void kvm_arm_get_virtual_time(CPUState *cs) void kvm_arm_put_virtual_time(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); - struct kvm_one_reg reg = { - .id = KVM_REG_ARM_TIMER_CNT, - .addr = (uintptr_t)&cpu->kvm_vtime, - }; int ret; if (!cpu->kvm_vtime_dirty) { return; } - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); abort(); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5e95c496bb9..047b269a791 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -540,14 +540,10 @@ static int kvm_arm_sve_set_vls(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; - struct kvm_one_reg reg = { - .id = KVM_REG_ARM64_SVE_VLS, - .addr = (uint64_t)&vls[0], - }; assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); } #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 @@ -726,19 +722,17 @@ static void kvm_inject_arm_sea(CPUState *c) static int kvm_arch_put_fpsimd(CPUState *cs) { CPUARMState *env = &ARM_CPU(cs)->env; - struct kvm_one_reg reg; int i, ret; for (i = 0; i < 32; i++) { uint64_t *q = aa64_vfp_qreg(env, i); #if HOST_BIG_ENDIAN uint64_t fp_val[2] = { q[1], q[0] }; - reg.addr = (uintptr_t)fp_val; + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), + fp_val); #else - reg.addr = (uintptr_t)q; + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); #endif - reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; } @@ -759,14 +753,11 @@ static int kvm_arch_put_sve(CPUState *cs) CPUARMState *env = &cpu->env; uint64_t tmp[ARM_MAX_VQ * 2]; uint64_t *r; - struct kvm_one_reg reg; int n, ret; for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); - reg.addr = (uintptr_t)r; - reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0); - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); if (ret) { return ret; } @@ -775,9 +766,7 @@ static int kvm_arch_put_sve(CPUState *cs) for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - reg.addr = (uintptr_t)r; - reg.id = KVM_REG_ARM64_SVE_PREG(n, 0); - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); if (ret) { return ret; } @@ -785,9 +774,7 @@ static int kvm_arch_put_sve(CPUState *cs) r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - reg.addr = (uintptr_t)r; - reg.id = KVM_REG_ARM64_SVE_FFR(0); - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); if (ret) { return ret; } @@ -797,7 +784,6 @@ static int kvm_arch_put_sve(CPUState *cs) int kvm_arch_put_registers(CPUState *cs, int level) { - struct kvm_one_reg reg; uint64_t val; uint32_t fpr; int i, ret; @@ -814,9 +800,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) } for (i = 0; i < 31; i++) { - reg.id = AARCH64_CORE_REG(regs.regs[i]); - reg.addr = (uintptr_t) &env->xregs[i]; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); if (ret) { return ret; } @@ -827,16 +812,12 @@ int kvm_arch_put_registers(CPUState *cs, int level) */ aarch64_save_sp(env, 1); - reg.id = AARCH64_CORE_REG(regs.sp); - reg.addr = (uintptr_t) &env->sp_el[0]; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); if (ret) { return ret; } - reg.id = AARCH64_CORE_REG(sp_el1); - reg.addr = (uintptr_t) &env->sp_el[1]; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); if (ret) { return ret; } @@ -847,23 +828,17 @@ int kvm_arch_put_registers(CPUState *cs, int level) } else { val = cpsr_read(env); } - reg.id = AARCH64_CORE_REG(regs.pstate); - reg.addr = (uintptr_t) &val; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); if (ret) { return ret; } - reg.id = AARCH64_CORE_REG(regs.pc); - reg.addr = (uintptr_t) &env->pc; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); if (ret) { return ret; } - reg.id = AARCH64_CORE_REG(elr_el1); - reg.addr = (uintptr_t) &env->elr_el[1]; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); if (ret) { return ret; } @@ -882,9 +857,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) /* KVM 0-4 map to QEMU banks 1-5 */ for (i = 0; i < KVM_NR_SPSR; i++) { - reg.id = AARCH64_CORE_REG(spsr[i]); - reg.addr = (uintptr_t) &env->banked_spsr[i + 1]; - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); if (ret) { return ret; } @@ -899,18 +873,14 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - reg.addr = (uintptr_t)(&fpr); fpr = vfp_get_fpsr(env); - reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; } - reg.addr = (uintptr_t)(&fpr); fpr = vfp_get_fpcr(env); - reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); if (ret) { return ret; } From patchwork Thu Oct 19 13:35:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735569 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519798wro; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/24] arm/kvm: convert to kvm_get_one_reg Date: Thu, 19 Oct 2023 14:35:27 +0100 Message-Id: <20231019133537.2114929-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Cornelia Huck We can neaten the code by switching the callers that work on a CPUstate to the kvm_get_one_reg function. Reviewed-by: Gavin Shan Signed-off-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231010142453.224369-3-cohuck@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm.c | 15 +++--------- target/arm/kvm64.c | 57 ++++++++++++---------------------------------- 2 files changed, 18 insertions(+), 54 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1a8084c4601..7903e2ddde1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -553,24 +553,19 @@ bool write_kvmstate_to_list(ARMCPU *cpu) bool ok = true; for (i = 0; i < cpu->cpreg_array_len; i++) { - struct kvm_one_reg r; uint64_t regidx = cpu->cpreg_indexes[i]; uint32_t v32; int ret; - r.id = regidx; - switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: - r.addr = (uintptr_t)&v32; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + ret = kvm_get_one_reg(cs, regidx, &v32); if (!ret) { cpu->cpreg_values[i] = v32; } break; case KVM_REG_SIZE_U64: - r.addr = (uintptr_t)(cpu->cpreg_values + i); - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); break; default: g_assert_not_reached(); @@ -706,17 +701,13 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) void kvm_arm_get_virtual_time(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); - struct kvm_one_reg reg = { - .id = KVM_REG_ARM_TIMER_CNT, - .addr = (uintptr_t)&cpu->kvm_vtime, - }; int ret; if (cpu->kvm_vtime_dirty) { return; } - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); abort(); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 047b269a791..558c0b88dd6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -909,14 +909,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) static int kvm_arch_get_fpsimd(CPUState *cs) { CPUARMState *env = &ARM_CPU(cs)->env; - struct kvm_one_reg reg; int i, ret; for (i = 0; i < 32; i++) { uint64_t *q = aa64_vfp_qreg(env, i); - reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr = (uintptr_t)q; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); if (ret) { return ret; } else { @@ -940,15 +937,12 @@ static int kvm_arch_get_sve(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - struct kvm_one_reg reg; uint64_t *r; int n, ret; for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { r = &env->vfp.zregs[n].d[0]; - reg.addr = (uintptr_t)r; - reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0); - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); if (ret) { return ret; } @@ -957,9 +951,7 @@ static int kvm_arch_get_sve(CPUState *cs) for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { r = &env->vfp.pregs[n].p[0]; - reg.addr = (uintptr_t)r; - reg.id = KVM_REG_ARM64_SVE_PREG(n, 0); - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); if (ret) { return ret; } @@ -967,9 +959,7 @@ static int kvm_arch_get_sve(CPUState *cs) } r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; - reg.addr = (uintptr_t)r; - reg.id = KVM_REG_ARM64_SVE_FFR(0); - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); if (ret) { return ret; } @@ -980,7 +970,6 @@ static int kvm_arch_get_sve(CPUState *cs) int kvm_arch_get_registers(CPUState *cs) { - struct kvm_one_reg reg; uint64_t val; unsigned int el; uint32_t fpr; @@ -990,31 +979,24 @@ int kvm_arch_get_registers(CPUState *cs) CPUARMState *env = &cpu->env; for (i = 0; i < 31; i++) { - reg.id = AARCH64_CORE_REG(regs.regs[i]); - reg.addr = (uintptr_t) &env->xregs[i]; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); if (ret) { return ret; } } - reg.id = AARCH64_CORE_REG(regs.sp); - reg.addr = (uintptr_t) &env->sp_el[0]; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); if (ret) { return ret; } - reg.id = AARCH64_CORE_REG(sp_el1); - reg.addr = (uintptr_t) &env->sp_el[1]; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); if (ret) { return ret; } - reg.id = AARCH64_CORE_REG(regs.pstate); - reg.addr = (uintptr_t) &val; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); if (ret) { return ret; } @@ -1031,9 +1013,7 @@ int kvm_arch_get_registers(CPUState *cs) */ aarch64_restore_sp(env, 1); - reg.id = AARCH64_CORE_REG(regs.pc); - reg.addr = (uintptr_t) &env->pc; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); if (ret) { return ret; } @@ -1047,9 +1027,7 @@ int kvm_arch_get_registers(CPUState *cs) aarch64_sync_64_to_32(env); } - reg.id = AARCH64_CORE_REG(elr_el1); - reg.addr = (uintptr_t) &env->elr_el[1]; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); if (ret) { return ret; } @@ -1059,9 +1037,8 @@ int kvm_arch_get_registers(CPUState *cs) * KVM SPSRs 0-4 map to QEMU banks 1-5 */ for (i = 0; i < KVM_NR_SPSR; i++) { - reg.id = AARCH64_CORE_REG(spsr[i]); - reg.addr = (uintptr_t) &env->banked_spsr[i + 1]; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); if (ret) { return ret; } @@ -1082,17 +1059,13 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } - reg.addr = (uintptr_t)(&fpr); - reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; } vfp_set_fpsr(env, fpr); - reg.addr = (uintptr_t)(&fpr); - reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); if (ret) { return ret; } From patchwork Thu Oct 19 13:35:28 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/24] target/arm: Permit T32 LDM with single register Date: Thu, 19 Oct 2023 14:35:28 +0100 Message-Id: <20231019133537.2114929-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For the Thumb T32 encoding of LDM, if only a single register is specified in the register list this instruction is UNPREDICTABLE, with the following choices: * instruction UNDEFs * instruction is a NOP * instruction loads a single register * instruction loads an unspecified set of registers Currently we choose to UNDEF (a behaviour chosen in commit 4b222545dbf30 in 2019; previously we treated it as "load the specified single register"). Unfortunately there is real world code out there (which shipped in at least Android 11, 12 and 13) which incorrectly uses this UNPREDICTABLE insn on the assumption that it does a single register load, which is (presumably) what it happens to do on real hardware, and is also what it does on the equivalent A32 encoding. Revert to the pre-4b222545dbf30 behaviour of not UNDEFing for this T32 encoding. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799 Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20230927101853.39288-1-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 48927fbb8ce..b3660173d1d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7882,7 +7882,7 @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, } } -static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) +static bool op_stm(DisasContext *s, arg_ldst_block *a) { int i, j, n, list, mem_idx; bool user = a->u; @@ -7899,7 +7899,14 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) list = a->list; n = ctpop16(list); - if (n < min_n || a->rn == 15) { + /* + * This is UNPREDICTABLE for n < 1 in all encodings, and we choose + * to UNDEF. In the T32 STM encoding n == 1 is also UNPREDICTABLE, + * but hardware treats it like the A32 version and implements the + * single-register-store, and some in-the-wild (buggy) software + * assumes that, so we don't UNDEF on that case. + */ + if (n < 1 || a->rn == 15) { unallocated_encoding(s); return true; } @@ -7935,8 +7942,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - /* BitCount(list) < 1 is UNPREDICTABLE */ - return op_stm(s, a, 1); + return op_stm(s, a); } static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -7946,11 +7952,10 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - /* BitCount(list) < 2 is UNPREDICTABLE */ - return op_stm(s, a, 2); + return op_stm(s, a); } -static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) +static bool do_ldm(DisasContext *s, arg_ldst_block *a) { int i, j, n, list, mem_idx; bool loaded_base; @@ -7979,7 +7984,14 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) list = a->list; n = ctpop16(list); - if (n < min_n || a->rn == 15) { + /* + * This is UNPREDICTABLE for n < 1 in all encodings, and we choose + * to UNDEF. In the T32 LDM encoding n == 1 is also UNPREDICTABLE, + * but hardware treats it like the A32 version and implements the + * single-register-load, and some in-the-wild (buggy) software + * assumes that, so we don't UNDEF on that case. + */ + if (n < 1 || a->rn == 15) { unallocated_encoding(s); return true; } @@ -8045,8 +8057,7 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - /* BitCount(list) < 1 is UNPREDICTABLE */ - return do_ldm(s, a, 1); + return do_ldm(s, a); } static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -8056,16 +8067,14 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - /* BitCount(list) < 2 is UNPREDICTABLE */ - return do_ldm(s, a, 2); + return do_ldm(s, a); } static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) { /* Writeback is conditional on the base register not being loaded. */ a->w = !(a->list & (1 << a->rn)); - /* BitCount(list) < 1 is UNPREDICTABLE */ - return do_ldm(s, a, 1); + return do_ldm(s, a); } static bool trans_CLRM(DisasContext *s, arg_CLRM *a) From patchwork Thu Oct 19 13:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735583 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1521360wro; Thu, 19 Oct 2023 06:40:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHdobldn7SiP73hm5VuCj591GYT8OCR6SQknMPtF+7laA2h27iC2FoMnqvvn8JOfAvr7y0b X-Received: by 2002:a05:620a:4510:b0:775:7d81:f8bb with SMTP id t16-20020a05620a451000b007757d81f8bbmr2744121qkp.11.1697722839096; Thu, 19 Oct 2023 06:40:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722839; cv=none; d=google.com; s=arc-20160816; b=froCftG4D6t8J96zxWmi5BtHCDTK0toaq/hDc5y90k+NiZdUgpBcRI+gpUrSDZkJ2I frkMOrwLC4D/TgFd5wDyP3YekyWbTZ++OeF+3RqakmX+q8167C3qlsq2ra5ME/hCF1Kr PjglvgxxT1/2l2XGpxRdQcwmsziw09vW4Bgw0YY/ManNgNuXNujQpxEZGsX0y0gjIEKb g4UVQDwXCDMKLzksrwdpNvvvCwhoqBltjNqKjnNp8dQKaXNe45IARCnGvm9FKMBbqY4N Oxr6bsPz70Q2s+C/xVx/Rp/MqJrN/0mOKGGv1bMqoAmLdIMgqK7v0yZUJQnwfaK3xNFH 4lHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KQjZ8bTDzCLrmeviYWdiySCbGKf4nGRL3SCgsoJSs2w=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=XH6q7VFhTJPU2xSWpJcUmPvspVXauy5OmJ+PQ0LrXzMAwr8kqvwsMtes2P56nqEkWq ZOxN7Bq6/z2U3825Y2Nwyulqt/Mb/oSx7yq/+o4fNf+M3PpD0Zy2+5Oi1oX4GLARw+Uo LLjwRUant/4JwCRCTNDOGlLMmBHNAeiJa39+DCMn8OapbNzxPRVPO/QMThxgrndhEAu7 XxVrMh/i6bPBxmCKzKHtIvBfHkHYmCMCvM4C61PKo89dw32APmZx3Nxbe4Wy2GUYtYPj 03s/SKIlFa2AuUW7ruLUpI5E7fmIAYRwchQJOnomGqscr94Wr+67ZEz+2fW4Q79sTFU5 tOXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XSwNhND0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/24] hw/arm/smmuv3: Update ID register bit field definitions Date: Thu, 19 Oct 2023 14:35:29 +0100 Message-Id: <20231019133537.2114929-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Update the SMMUv3 ID register bit field definitions to the set in the most recent specification (IHI0700 F.a). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Mostafa Saleh Reviewed-by: Eric Auger Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org --- hw/arm/smmuv3-internal.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 648c2e37a27..6076025ad6a 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -38,33 +38,71 @@ REG32(IDR0, 0x0) FIELD(IDR0, S1P, 1 , 1) FIELD(IDR0, TTF, 2 , 2) FIELD(IDR0, COHACC, 4 , 1) + FIELD(IDR0, BTM, 5 , 1) + FIELD(IDR0, HTTU, 6 , 2) + FIELD(IDR0, DORMHINT, 8 , 1) + FIELD(IDR0, HYP, 9 , 1) + FIELD(IDR0, ATS, 10, 1) + FIELD(IDR0, NS1ATS, 11, 1) FIELD(IDR0, ASID16, 12, 1) + FIELD(IDR0, MSI, 13, 1) + FIELD(IDR0, SEV, 14, 1) + FIELD(IDR0, ATOS, 15, 1) + FIELD(IDR0, PRI, 16, 1) + FIELD(IDR0, VMW, 17, 1) FIELD(IDR0, VMID16, 18, 1) + FIELD(IDR0, CD2L, 19, 1) + FIELD(IDR0, VATOS, 20, 1) FIELD(IDR0, TTENDIAN, 21, 2) + FIELD(IDR0, ATSRECERR, 23, 1) FIELD(IDR0, STALL_MODEL, 24, 2) FIELD(IDR0, TERM_MODEL, 26, 1) FIELD(IDR0, STLEVEL, 27, 2) + FIELD(IDR0, RME_IMPL, 30, 1) REG32(IDR1, 0x4) FIELD(IDR1, SIDSIZE, 0 , 6) + FIELD(IDR1, SSIDSIZE, 6 , 5) + FIELD(IDR1, PRIQS, 11, 5) FIELD(IDR1, EVENTQS, 16, 5) FIELD(IDR1, CMDQS, 21, 5) + FIELD(IDR1, ATTR_PERMS_OVR, 26, 1) + FIELD(IDR1, ATTR_TYPES_OVR, 27, 1) + FIELD(IDR1, REL, 28, 1) + FIELD(IDR1, QUEUES_PRESET, 29, 1) + FIELD(IDR1, TABLES_PRESET, 30, 1) + FIELD(IDR1, ECMDQ, 31, 1) #define SMMU_IDR1_SIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 REG32(IDR2, 0x8) + FIELD(IDR2, BA_VATOS, 0, 10) + REG32(IDR3, 0xc) FIELD(IDR3, HAD, 2, 1); + FIELD(IDR3, PBHA, 3, 1); + FIELD(IDR3, XNX, 4, 1); + FIELD(IDR3, PPS, 5, 1); + FIELD(IDR3, MPAM, 7, 1); + FIELD(IDR3, FWB, 8, 1); + FIELD(IDR3, STT, 9, 1); FIELD(IDR3, RIL, 10, 1); FIELD(IDR3, BBML, 11, 2); + FIELD(IDR3, E0PD, 13, 1); + FIELD(IDR3, PTWNNC, 14, 1); + FIELD(IDR3, DPT, 15, 1); + REG32(IDR4, 0x10) + REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); FIELD(IDR5, GRAN4K, 4, 1); FIELD(IDR5, GRAN16K, 5, 1); FIELD(IDR5, GRAN64K, 6, 1); + FIELD(IDR5, VAX, 10, 2); + FIELD(IDR5, STALL_MAX, 16, 16); #define SMMU_IDR5_OAS 4 From patchwork Thu Oct 19 13:35:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735585 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1522428wro; Thu, 19 Oct 2023 06:42:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGsZj0phdxkmdC7Zblx7GRbQdOT98Oe8ARSCCRW82+Oy5AXfRqlsrsXL37SpC7PZ72oPpmt X-Received: by 2002:a05:6214:2021:b0:66c:fcfc:9174 with SMTP id 1-20020a056214202100b0066cfcfc9174mr2572685qvf.41.1697722957727; Thu, 19 Oct 2023 06:42:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722957; cv=none; d=google.com; s=arc-20160816; b=iwFey61TM440Me22bLmri0QPDcQM29lL/NFgih1fBUXsm8JwnDYc5g6hGC/MHSGnqB gh8xK05dbwPiReflCZLsfg+nOrw19jn3sf6wGB0kdeFsO1SqndjC+BeP1NG4puXZ6fnH syY81C0LsfEy4ecUNTOlUs8L4Vrjofzy3xTMxtFrqrXDDZHwBiiGxWEwxdVxj2CgjwGK Epjo38SsbRVoH7JoxB7ZyGDFNnu7E5zEIysBtmJL4u6ksAPVeIhVfSxiB8IL+hboTgNe IEZmDG+N/2XHJJ5dDZEYVPb18qzmrCFpJ2eIgH1dTUSraab/GYJoBbQ7aCxGbWekjrtz 0kBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=j1tM+l52FnQrUD9wyepjhR0Rex/I2IZngyzPJkref1s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=0uTD4r7D5GTCBsGA383pc4GPt8NfoePXFoh9bDOHF+jOOQXrxla5lnkxjeyX1Rr1cL YpnNXNneK2OzwTyfBzyMwUR9dKCsoOdSJ/IU4AkiBa5Vw/h+WYgPcdujDZ4R4xvf9b/Q KyN8FGaCoNWs06J1XkJ2kTUcv8OJ+d8U/jnl1TqgcnHQqRXvTZy5fH4Q0TsmHdTmZIC6 VJvIdhLOBjAOQ+dwOfOysNvsI0eTCt/HN3pzcU8uzKCXmEXZctfjT+txvo5wPGgLHe9J 7jgkRBYwHEeIL13z2lYhVmEJOrLpwuny26NQ+GYkVke0qHs/35ZSqgFg67DEWwRhsceQ MQ0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dp+OcxpN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/24] hw/arm/smmuv3: Sort ID register setting into field order Date: Thu, 19 Oct 2023 14:35:30 +0100 Message-Id: <20231019133537.2114929-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In smmuv3_init_regs() when we set the various bits in the ID registers, we do this almost in order of the fields in the registers, but not quite. Move the initialization of SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Mostafa Saleh Reviewed-by: Eric Auger Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org --- hw/arm/smmuv3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 6f2b2bd45f9..f03d58300fa 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -278,15 +278,15 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); - s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */ /* 4K, 16K and 64K granule support */ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); - s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */ s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); s->cmdq.prod = 0; From patchwork Thu Oct 19 13:35:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735586 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1522562wro; Thu, 19 Oct 2023 06:42:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGaDTJpvbdNfMhHZ02ZaeNE97W3/N6ZdZKjV/ImMmmTts4PO3WTJRFt6d0AU9KVX2HUTMt6 X-Received: by 2002:a05:6808:20a1:b0:3af:658f:14f9 with SMTP id s33-20020a05680820a100b003af658f14f9mr2425275oiw.41.1697722969659; Thu, 19 Oct 2023 06:42:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722969; cv=none; d=google.com; s=arc-20160816; b=EZv+0pz32GZlk0B1baC7knTedkzRLJi6plDVYoHVfdyyMWBd0cW9uf91Tbvkuv5Xfj Gpn3EpO4PNDa3RR14vXhxq4A8Xl2mbAq0u1W9h+VfXt7CwLaXtonwKbnKNV0INOgoN8j mqXBWl0Unb32o3ixmp1psaQ3SML7ryhBSCM/YhJt0fQx2ZFBj39U7kUqbpeouJ5vfSpm JfVgZBHudehqXlfAOS7YG7fAUyhfl/PULz4zJCIlpN1eZ8SA6wnNHI7/EFDdZ2Abkm7w Wo037V2OUF3M555IIpEhRu28SWhDhYW3A+x8Zne2q1C5eNsbOj055hcSqIGMJ+AcUfkK QirQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=69JHSg6SM2bIgn/IyTKVkAnCuZSRpe0YGCFy2Ih5E+M=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=JLYF3cGz1lBUrej8NRJe4QGsGbbF2TuiisvdyASP0h/xUrmOZDxWY9Nnzd4ZSo4+/s svYdVQ0wAA82ig4Q3lvuxwFMx96MgMhv/Vzx+cWLULXH+u7AkQhM/biTt9FBasR2rZix mbJpjHy5YX3IGsFwj3crMMN1f06lJhmK8gYznNtBOhmt+KnZgXIC2Z5okHRVguM1jij/ TxqsEmR5fpRsAcPJBu/Xsjp9A1dZXVZ8x8CSdeLF5W2DH5sd/HDZTjqMitDYxzB6Q+Jm iPTiPfthozFmOyvv9AnVobektkoU3KXyb0ntvFSGd8CHF5yXn7BYWyVAmDZ5pynbndg2 g8fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iThHszA7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/24] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature Date: Thu, 19 Oct 2023 14:35:31 +0100 Message-Id: <20231019133537.2114929-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is supported, so we should theoretically have implemented it as part of the recent S2P work. Fortunately, for us the implementation is a no-op. This feature is about interpretation of the stage 2 page table descriptor XN bits, which control execute permissions. For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and IOMMUAccessFlags) only indicate read and write; we do not distinguish data reads from instruction reads outside the CPU proper. In the SMMU architecture's terms, our interconnect between the client device and the SMMU doesn't have the ability to convey the INST attribute, and we therefore use the default value of "data" for this attribute. We also do not support the bits in the Stream Table Entry that can override the on-the-bus transaction attribute permissions (we do not set SMMU_IDR1.ATTR_PERMS_OVR=1). These two things together mean that for our implementation, it never has to deal with transactions with the INST attribute, and so it can correctly ignore the XN bits entirely. So we already implement FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent that we need to. Advertise the presence of the feature in SMMU_IDR3.XNX. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Mostafa Saleh Reviewed-by: Eric Auger Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org --- hw/arm/smmuv3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index f03d58300fa..c3871ae067f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -279,6 +279,10 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); + if (FIELD_EX32(s->idr[0], IDR0, S2P)) { + /* XNX is a stage-2-specific feature */ + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1); + } s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); From patchwork Thu Oct 19 13:35:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735567 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519657wro; Thu, 19 Oct 2023 06:37:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJ9qqe51Nki4oKG3JKqopuqgDSVOJsJqjYWVDKmBSzARG5S1kgf/uTcig1LXc07IhnjB9X X-Received: by 2002:a05:622a:1449:b0:41c:bbbc:2ede with SMTP id v9-20020a05622a144900b0041cbbbc2edemr2140976qtx.14.1697722620211; Thu, 19 Oct 2023 06:37:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722620; cv=none; d=google.com; s=arc-20160816; b=IfUZLPRD/BG1oNmAvk6PkxFe/doJXPf1uj+HIGxVWU7jFNZ1FM68nAUEvv6WySbrqD bsRMqw1oPcgT1hZzPDFreuLdicO9BHNNU8uLsIyd3so+7rY5v1wqbC3/qTUf7mTViHV7 Xg5xSWGy7wpUqoio6NrM3PkMLARSag/rYWyR0YTzD+MorSl6RqK18uoKqteDEBRRe6BU gi5e9Fszcsg1VJMZsyeRqKqggK8l4HkpbRazZrNYSbimTKYXvlwDcq+dQ7NvGLtAu3uM m+Vv04NeahNlZ0oM6raTwzVvt6dUlOXhFijN8ZJT/4MsnDXrbiMi4cmrnSOVzx+5y3S3 LEGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HT7bwggZNgShOlxGo+72AKdKpJoofzjD5SXuqPfjmCI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=CyFIUcZ5Z7E2XqQYjzIjxVwTDyAsFQmQDdz7c77PyXot5H7J2DdFPxmvu7joLsDyBA IwsoKdMY5hossKaEWL5XYohLnEZwPOlXOD9Jtq2UDB2o8tRPB1Ms1359AaxVUerKvFXX VcUfyFiPTCcsJrPPJs8oNZUdYkOtL3b3PzlQEKb8ky243z0MgxCinDUW1GwcDdRdq6Lc prY/YyAmwBleVAA3FqVjHesj4NXJ4dYczFXBgPqAtKzYue0NaFv76t6BiIII/80aiKNk ivVqiiiaUCopY+J5XqW1aEdtSOtWb1mec0ohTkF9wHHlHk8IOcTeSZoUnaOmfiQ/rWB+ vjHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E0h1guCi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/24] target/arm: Implement FEAT_HPMN0 Date: Thu, 19 Oct 2023 14:35:32 +0100 Message-Id: <20231019133537.2114929-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_HPMN0 is a small feature which defines that it is valid for MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided to an EL1 guest" (previously this setting was reserved). QEMU's implementation almost gets HPMN == 0 right, but we need to fix one check in pmevcntr_is_64_bit(). That is enough for us to advertise the feature in the 'max' CPU. (We don't need to make the behaviour conditional on feature presence, because the FEAT_HPMN0 behaviour is within the range of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0 implementation.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/helper.c | 2 +- target/arm/tcg/cpu32.c | 4 ++++ target/arm/tcg/cpu64.c | 1 + 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 965cbf84c51..47fd648035f 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -46,6 +46,7 @@ the following architecture extensions: - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_HPDS2 (Translation table page-based hardware attributes) +- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) - FEAT_IDST (ID space trap handling) - FEAT_IESB (Implicit error synchronization event) diff --git a/target/arm/helper.c b/target/arm/helper.c index 01cd1474565..b29edb26af8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1283,7 +1283,7 @@ static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; - if (hpmn != 0 && counter >= hpmn) { + if (counter >= hpmn) { return hlp; } } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 1f918ff5375..0d5d8e307dd 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -89,6 +89,10 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; + + t = cpu->isar.id_dfr1; + t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ + cpu->isar.id_dfr1 = t; } /* CPU models. These are not needed for the AArch64 linux-user build. */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 68928e51272..d978aa5f7ad 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1109,6 +1109,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64dfr0; t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ + t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_aa64dfr0 = t; t = cpu->isar.id_aa64smfr0; From patchwork Thu Oct 19 13:35:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735570 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519967wro; Thu, 19 Oct 2023 06:37:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHF9MGyWViENJZsS7nxqUXmI+ezkGgq7WQLNMD2WMt4DM3DVz5psQehzLBInMd3Woa1B6o0 X-Received: by 2002:a05:622a:1493:b0:41c:be07:c6ca with SMTP id t19-20020a05622a149300b0041cbe07c6camr2124107qtx.32.1697722656785; Thu, 19 Oct 2023 06:37:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722656; cv=none; d=google.com; s=arc-20160816; b=PRSEq6+nerU3pcBu2ZWNIXmTAVDb8tCLltRH0vSBrcz916U28PY5YlldxkoqBlB05h CWhv3LelGlAX2Xgiafzl6ubEHA5q/TYPa1xca4lm5NmgPoKgP39X2e1l+X0iggpUKw+1 ghVmJvL7G8vNeha7WDJDsMizrxSL8+7TTHprc9kKleAd76klK4JqX4RkvujEHFgIZXtD enXEKV9nWlG2v4BTaY2AQcdwQUhMjh9O5/Ij8j9b5Ua3ENoH1ML3u1ap7sjWUvExFCDL 2xUSJNnsGNcb1CqvVfMh65oRfXG4kRfxwBvzCnlEH4P0K8y+YIK7/K2R4S/QFr/CX1GV dYFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pWFnlBnEBWziPmtTDaxLrH+se8eDbl8V/1Yai8/lSj8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=an5ImaEoTeQAjmRiRNBBo8/1N0nLWwjh0fqnUxxKl/bD65QADrgPxskJhGE79urGua hs+IJE761a6RDZWWEvUqTzodH/SfsPdq78chrcbf5DKPGcPYaz+lsz5hNCGzysUa3UVR l69x4dZkIJxAMHiaDVMeKvpEuVe1B4FHwLuqXX/77kOm4jc1sRQJ9mteyZUv1pUW50vH CxYh6z/PpK/czr+Yx9Ktupc0zNt4zLgnd7tdPsPLoao6PFxJ86ZheRsDUJuvntsC06tS JgcPrPiG0x3W++MtnTPVeWTzfUuRFpZHthE1yfz5kdWBuvL99cj8vVUcsdF0N0d4PDjs MmIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HWxsWR+Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/24] target/arm/kvm64.c: Remove unused include Date: Thu, 19 Oct 2023 14:35:33 +0100 Message-Id: <20231019133537.2114929-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The include of hw/arm/virt.h in kvm64.c is unnecessary and also a layering violation since the generic KVM code shouldn't need to know anything about board-specifics. The include line is an accidental leftover from commit 15613357ba53a4763, where we cleaned up the code to not depend on virt board internals but forgot to also remove the now-redundant include line. Signed-off-by: Peter Maydell Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230925110429.3917202-1-peter.maydell@linaro.org --- target/arm/kvm64.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 558c0b88dd6..4bb68646e43 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -30,7 +30,6 @@ #include "internals.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" -#include "hw/arm/virt.h" static bool have_guest_debug; From patchwork Thu Oct 19 13:35:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735578 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1520729wro; Thu, 19 Oct 2023 06:39:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHADy1/XqnZgrhs2wVpBcz0B361sNTYiF9+g4j7OPpEeg6wWPT4usyJq+lwWnjwfRGkG8Vg X-Received: by 2002:ac8:5a4c:0:b0:40d:6219:d813 with SMTP id o12-20020ac85a4c000000b0040d6219d813mr2339659qta.68.1697722756702; Thu, 19 Oct 2023 06:39:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722756; cv=none; d=google.com; s=arc-20160816; b=JjjYCAj+8dyA8AA0NI27JMKg5bB0P4SfsYFl3Cb0j0gCC3I/PT6ygxGBv5gn8R+AVu BMaMdR5IiUDVnWkxfeyYZ5a7cCYDvF4JsnHXMKSPd33mAdWb6VJs47B/ucs/BZiswpeV 1mnuNQebRNPPxB+M6e1vlnj/DUH1/hlWkiby6noPlqVl2Fg+7BuGL3S3QqU8ugkJOFka p3y1H+cNEHSniMwCTPFBWaGyz/FjbJv0uVUm3NbWrfgCmr41c0QHKdr57t0HOEyEjbin ZEGReBf5nuiJO5+yvhql/0o3DVgQw42VI/jh7uzYMjn3xIhn7bg3dtOkBdZzqP/YvTZw 1CfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y0fdYuZ/itTuCs4C9nQ/nu3aGMsyGS4D2cdzozItBYw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=iOonePSw7WwYnYHp2tfY9ZKARf7Pw2rx+aoKP9d4iWR3sTvE3yPKawM+UtjDuxBzSC oG8UxtXYiscvwOmUhrM07HrYmcarDxgc3qIajHk6l+wETTBbPdiRQlx6t4I8I2xLaBMC 0nT6M1jDahQG283CgP1aKzSkur08qB7b8vj9sI1OJQNIHmyQhXBBZiDfgzbnGB34bT8N +rvYAGyhb8azVEchPaVvXWzCU/tfv3uGW05dxCIIG5hg6AFUP48l3CCmX7ZvJYo3i90u 0IU34LWpsQ2wfZlEO+Gm6LfYWUQ357oOn49UKFkbzlwL316fIPkii0w5IpgDAp2IxUvz 2Shw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ckdpjNOR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/24] target/arm/common-semi-target.h: Remove unnecessary boot.h include Date: Thu, 19 Oct 2023 14:35:34 +0100 Message-Id: <20231019133537.2114929-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The hw/arm/boot.h include in common-semi-target.h is not actually needed, and it's a bit odd because it pulls a hw/arm header into a target/arm file. This include was originally needed because the semihosting code used the arm_boot_info struct to get the base address of the RAM in system emulation, to use in a (bad) heuristic for the return values for the SYS_HEAPINFO semihosting call. We've since overhauled how we calculate the HEAPINFO values in system emulation, and the code no longer uses the arm_boot_info struct. Remove the now-redundant include line, and instead directly include the cpu-qom.h header that we were previously getting via boot.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230925112219.3919261-1-peter.maydell@linaro.org --- target/arm/common-semi-target.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h index 19438ed8cd3..da51f2d7f54 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.h @@ -10,9 +10,7 @@ #ifndef TARGET_ARM_COMMON_SEMI_TARGET_H #define TARGET_ARM_COMMON_SEMI_TARGET_H -#ifndef CONFIG_USER_ONLY -#include "hw/arm/boot.h" -#endif +#include "target/arm/cpu-qom.h" static inline target_ulong common_semi_arg(CPUState *cs, int argno) { From patchwork Thu Oct 19 13:35:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735576 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1520593wro; Thu, 19 Oct 2023 06:38:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGsBEJOWczqO9R0cZdK75gbk4IxuGe2eXw/wco6YjQihhR/LkhgA2K23OA2ziME4kyakz+U X-Received: by 2002:a67:cb8b:0:b0:457:bc95:c824 with SMTP id h11-20020a67cb8b000000b00457bc95c824mr1820722vsl.2.1697722737573; Thu, 19 Oct 2023 06:38:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722737; cv=none; d=google.com; s=arc-20160816; b=pIwDN+DUFCtmXDqP7SP1awdGY3siRyFlB5iSpzz2ToydR0M22lCABLbsXX279/tZ06 AWwjqF+oke2tG4BzgY6e6fkmU5ADYbxXlQ7tDzPOS67qh+82evoCwwOZ5r20LctktNWE ATSgssIODcn1/Whwwu+V7ygQY4JOaXSY8g/3tG9oBgfIi653BqDdzG18wGZs2sC8Qbzk m2MR5kR1iYjkqskb+qPWrB+wguXPzYbleBLN0f4H5c8+ivBjQV7sZw94DybkXX5aO5L+ e/rDsNw0gV17ZooUI8G6Tm4pKSrD2y/aPgXHJbSrFNNqyBx577xjvSihXxr/GHV1fNAO bXCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=C+WiDyAy8aq2skm+S9JHsBP5Z3J5WgdGtbpMg9UHzTc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=xno4s+R+8LyjyV0skDLMRg1esFseoDhgI1djszeRddCBzUFk6hnRsPnv/TnjxQ1Osq MYgnTg94Vgx/5/xEtjElqXhdhJ2LmCbV9DLcb76CCIAjZOMTJlfsKfvYnNQJ1WEYmCoh TijPeeJ6KELmgI2M/2oFRjlz4rbfaNH0NAaf2NnJh15EztvC+zjKkc6Fzqnprc+Jwi/h eQSk66+IrNvtDlw/I+PbPUV034vAUQqmkIqt03Ki1QPmjrlyCIArgzKIMAW19L7uRcj6 /K0hOyZrcAAWZuCxPCh4hMJhRkI0CYCZOzKFWFBAQYhVVMqcgRROe5z5KY1UaJA8k9Qm em4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vN1S4sgG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/24] target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL Date: Thu, 19 Oct 2023 14:35:35 +0100 Message-Id: <20231019133537.2114929-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The code for powering on a CPU in arm-powerctl.c has two separate use cases: * emulation of a real hardware power controller * emulation of firmware interfaces (primarily PSCI) with CPU on/off APIs For the first case, we only need to reset the CPU and set its starting PC and X0. For the second case, because we're emulating the firmware we need to ensure that it's in the state that the firmware provides. In particular, when we reset to a lower EL than the highest one we are emulating, we need to put the CPU into a state that permits correct running at that lower EL. We already do a little of this in arm-powerctl.c (for instance we set SCR_HCE to enable the HVC insn) but we don't do enough of it. This means that in the case where we are emulating EL3 but also providing emulated PSCI the guest will crash when a secondary core tries to use a feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth. The hw/arm/boot.c code also has to support this "start guest code in an EL that's lower than the highest emulated EL" case in order to do direct guest kernel booting; it has all the necessary initialization code to set the SCR_EL3 bits. Pull the relevant boot.c code out into a separate function so we can share it between there and arm-powerctl.c. This refactoring has a few code changes that look like they might be behaviour changes but aren't: * if info->secure_boot is false and info->secure_board_setup is true, then the old code would start the first CPU in Hyp mode but without changing SCR.NS and NSACR.{CP11,CP10}. This was wrong behaviour because there's no such thing as Secure Hyp mode. The new code will leave the CPU in SVC. (There is no board which sets secure_boot to false and secure_board_setup to true, so this isn't a behaviour change for any of our boards.) * we don't explicitly clear SCR.NS when arm-powerctl.c does a CPU-on to EL3. This was a no-op because CPU reset will reset to NS == 0. And some real behaviour changes: * we no longer set HCR_EL2.RW when booting into EL2: the guest can and should do that themselves before dropping into their EL1 code. (arm-powerctl and boot did this differently; I opted to use the logic from arm-powerctl, which only sets HCR_EL2.RW when it's directly starting the guest in EL1, because it's more correct, and I don't expect guests to be accidentally depending on our having set the RW bit for them.) * if we are booting a CPU into AArch32 Secure SVC then we won't set SCR.HCE any more. This affects only the vexpress-a15 and raspi2b machine types. Guests booting in this case will either: - be able to set SCR.HCE themselves as part of moving from Secure SVC into NS Hyp mode - will move from Secure SVC to NS SVC, and won't care about behaviour of the HVC insn - will stay in Secure SVC, and won't care about HVC * on an arm-powerctl CPU-on we will now set the SCR bits for pauth/mte/sve/sme/hcx/fgt features The first two of these are very minor and I don't expect guest code to trip over them, so I didn't judge it worth convoluting the code in an attempt to keep exactly the same boot.c behaviour. The third change fixes issue 1899. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org --- target/arm/cpu.h | 22 +++++++++ hw/arm/boot.c | 95 ++++++++++----------------------------- target/arm/arm-powerctl.c | 53 +--------------------- target/arm/cpu.c | 95 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+), 124 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a9edfb8353e..76d4cef9e3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1149,6 +1149,28 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); +/** + * arm_emulate_firmware_reset: Emulate firmware CPU reset handling + * @cpu: CPU (which must have been freshly reset) + * @target_el: exception level to put the CPU into + * @secure: whether to put the CPU in secure state + * + * When QEMU is directly running a guest kernel at a lower level than + * EL3 it implicitly emulates some aspects of the guest firmware. + * This includes that on reset we need to configure the parts of the + * CPU corresponding to EL3 so that the real guest code can run at its + * lower exception level. This function does that post-reset CPU setup, + * for when we do direct boot of a guest kernel, and for when we + * emulate PSCI and similar firmware interfaces starting a CPU at a + * lower exception level. + * + * @target_el must be an EL implemented by the CPU between 1 and 3. + * We do not support dropping into a Secure EL other than 3. + * + * It is the responsibility of the caller to call arm_rebuild_hflags(). + */ +void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); + #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 24fa1690600..84ea6a807a4 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -722,84 +722,35 @@ static void do_cpu_reset(void *opaque) cpu_set_pc(cs, entry); } else { - /* If we are booting Linux then we need to check whether we are - * booting into secure or non-secure state and adjust the state - * accordingly. Out of reset, ARM is defined to be in secure state - * (SCR.NS = 0), we change that here if non-secure boot has been - * requested. + /* + * If we are booting Linux then we might need to do so at: + * - AArch64 NS EL2 or NS EL1 + * - AArch32 Secure SVC (EL3) + * - AArch32 NS Hyp (EL2) + * - AArch32 NS SVC (EL1) + * Configure the CPU in the way boot firmware would do to + * drop us down to the appropriate level. */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* AArch64 is defined to come out of reset into EL3 if enabled. - * If we are booting Linux then we need to adjust our EL as - * Linux expects us to be in EL2 or EL1. AArch32 resets into - * SVC, which Linux expects, so no privilege/exception level to - * adjust. - */ - if (env->aarch64) { - env->cp15.scr_el3 |= SCR_RW; - if (arm_feature(env, ARM_FEATURE_EL2)) { - env->cp15.hcr_el2 |= HCR_RW; - env->pstate = PSTATE_MODE_EL2h; - } else { - env->pstate = PSTATE_MODE_EL1h; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - env->cp15.scr_el3 |= SCR_API | SCR_APK; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - env->cp15.scr_el3 |= SCR_ATA; - } - if (cpu_isar_feature(aa64_sve, cpu)) { - env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; - env->vfp.zcr_el[3] = 0xf; - } - if (cpu_isar_feature(aa64_sme, cpu)) { - env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; - env->cp15.scr_el3 |= SCR_ENTP2; - env->vfp.smcr_el[3] = 0xf; - } - if (cpu_isar_feature(aa64_hcx, cpu)) { - env->cp15.scr_el3 |= SCR_HXEN; - } - if (cpu_isar_feature(aa64_fgt, cpu)) { - env->cp15.scr_el3 |= SCR_FGTEN; - } + int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; - /* AArch64 kernels never boot in secure mode */ - assert(!info->secure_boot); - /* This hook is only supported for AArch32 currently: - * bootloader_aarch64[] will not call the hook, and - * the code above has already dropped us into EL2 or EL1. - */ - assert(!info->secure_board_setup); - } - - if (arm_feature(env, ARM_FEATURE_EL2)) { - /* If we have EL2 then Linux expects the HVC insn to work */ - env->cp15.scr_el3 |= SCR_HCE; - } - - /* Set to non-secure if not a secure boot */ - if (!info->secure_boot && - (cs != first_cpu || !info->secure_board_setup)) { - /* Linux expects non-secure state */ - env->cp15.scr_el3 |= SCR_NS; - /* Set NSACR.{CP11,CP10} so NS can access the FPU */ - env->cp15.nsacr |= 3 << 10; - } - } - - if (!env->aarch64 && !info->secure_boot && - arm_feature(env, ARM_FEATURE_EL2)) { + if (env->aarch64) { /* - * This is an AArch32 boot not to Secure state, and - * we have Hyp mode available, so boot the kernel into - * Hyp mode. This is not how the CPU comes out of reset, - * so we need to manually put it there. + * AArch64 kernels never boot in secure mode, and we don't + * support the secure_board_setup hook for AArch64. */ - cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw); + assert(!info->secure_boot); + assert(!info->secure_board_setup); + } else { + if (arm_feature(env, ARM_FEATURE_EL3) && + (info->secure_boot || + (info->secure_board_setup && cs == first_cpu))) { + /* Start this CPU in Secure SVC */ + target_el = 3; + } } + arm_emulate_firmware_reset(cs, target_el); + if (cs == first_cpu) { AddressSpace *as = arm_boot_address_space(cpu, info); diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 326a03153df..c078849403c 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -65,60 +65,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); + arm_emulate_firmware_reset(target_cpu_state, info->target_el); target_cpu_state->halted = 0; - if (info->target_aa64) { - if ((info->target_el < 3) && arm_feature(&target_cpu->env, - ARM_FEATURE_EL3)) { - /* - * As target mode is AArch64, we need to set lower - * exception level (the requested level 2) to AArch64 - */ - target_cpu->env.cp15.scr_el3 |= SCR_RW; - } - - if ((info->target_el < 2) && arm_feature(&target_cpu->env, - ARM_FEATURE_EL2)) { - /* - * As target mode is AArch64, we need to set lower - * exception level (the requested level 1) to AArch64 - */ - target_cpu->env.cp15.hcr_el2 |= HCR_RW; - } - - target_cpu->env.pstate = aarch64_pstate_mode(info->target_el, true); - } else { - /* We are requested to boot in AArch32 mode */ - static const uint32_t mode_for_el[] = { 0, - ARM_CPU_MODE_SVC, - ARM_CPU_MODE_HYP, - ARM_CPU_MODE_SVC }; - - cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, - CPSRWriteRaw); - } - - if (info->target_el == 3) { - /* Processor is in secure mode */ - target_cpu->env.cp15.scr_el3 &= ~SCR_NS; - } else { - /* Processor is not in secure mode */ - target_cpu->env.cp15.scr_el3 |= SCR_NS; - - /* Set NSACR.{CP11,CP10} so NS can access the FPU */ - target_cpu->env.cp15.nsacr |= 3 << 10; - - /* - * If QEMU is providing the equivalent of EL3 firmware, then we need - * to make sure a CPU targeting EL2 comes out of reset with a - * functional HVC insn. - */ - if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) - && info->target_el == 2) { - target_cpu->env.cp15.scr_el3 |= SCR_HCE; - } - } - /* We check if the started CPU is now at the correct level */ assert(info->target_el == arm_current_el(&target_cpu->env)); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6c6c551573e..aa4e006f21a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -553,6 +553,101 @@ static void arm_cpu_reset_hold(Object *obj) } } +void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) +{ + ARMCPU *cpu = ARM_CPU(cpustate); + CPUARMState *env = &cpu->env; + bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); + bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); + + /* + * Check we have the EL we're aiming for. If that is the + * highest implemented EL, then cpu_reset has already done + * all the work. + */ + switch (target_el) { + case 3: + assert(have_el3); + return; + case 2: + assert(have_el2); + if (!have_el3) { + return; + } + break; + case 1: + if (!have_el3 && !have_el2) { + return; + } + break; + default: + g_assert_not_reached(); + } + + if (have_el3) { + /* + * Set the EL3 state so code can run at EL2. This should match + * the requirements set by Linux in its booting spec. + */ + if (env->aarch64) { + env->cp15.scr_el3 |= SCR_RW; + if (cpu_isar_feature(aa64_pauth, cpu)) { + env->cp15.scr_el3 |= SCR_API | SCR_APK; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + env->cp15.scr_el3 |= SCR_ATA; + } + if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; + env->vfp.zcr_el[3] = 0xf; + } + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; + env->cp15.scr_el3 |= SCR_ENTP2; + env->vfp.smcr_el[3] = 0xf; + } + if (cpu_isar_feature(aa64_hcx, cpu)) { + env->cp15.scr_el3 |= SCR_HXEN; + } + if (cpu_isar_feature(aa64_fgt, cpu)) { + env->cp15.scr_el3 |= SCR_FGTEN; + } + } + + if (target_el == 2) { + /* If the guest is at EL2 then Linux expects the HVC insn to work */ + env->cp15.scr_el3 |= SCR_HCE; + } + + /* Put CPU into non-secure state */ + env->cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + env->cp15.nsacr |= 3 << 10; + } + + if (have_el2 && target_el < 2) { + /* Set EL2 state so code can run at EL1. */ + if (env->aarch64) { + env->cp15.hcr_el2 |= HCR_RW; + } + } + + /* Set the CPU to the desired state */ + if (env->aarch64) { + env->pstate = aarch64_pstate_mode(target_el, true); + } else { + static const uint32_t mode_for_el[] = { + 0, + ARM_CPU_MODE_SVC, + ARM_CPU_MODE_HYP, + ARM_CPU_MODE_SVC, + }; + + cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); + } +} + + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, From patchwork Thu Oct 19 13:35:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735572 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1519990wro; Thu, 19 Oct 2023 06:37:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWUD06bIgh3LaOvEYsF7s10r8JoQ/MOSHm323JqQp6jKMQFNwovxaUv1KVHp+TSBan7gvU X-Received: by 2002:a25:5386:0:b0:d15:7402:f7cd with SMTP id h128-20020a255386000000b00d157402f7cdmr1913826ybb.27.1697722659373; Thu, 19 Oct 2023 06:37:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722659; cv=none; d=google.com; s=arc-20160816; b=TEjFnPgWC1Mdy8bmwvZJ8I/lwkmSrpv2lnc7Oo7ye37U9xnSSToJqMkwRFJWrDH/L4 47GTVmN/LIg/5i+LjMnILm30f6rSTH6GIkx8hYEsWGjU5nEUtPEmwJa7zrwdIp1AyoO8 SWKgX7aAezERj8vnaH4qme99iDHfH6Nzs8u6OC+wGJn9t+rjusgceKrN87usBAIqOg1v acUtm+4t9WAJuxLQYAUOeoIYjVy5UpMChuilGxaYzPTDcdoXw5cgA2JtX2llYZDqQdH9 wKQ7oN4PpxcoSqNKSwHnP+rKyLazHmv7ci38KD4HHXaXmmAQ+ZyQ9+J746QBqiqv3ij4 RGAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3ZO8XemeV6MKZJes6/JMerENEJvAmmFZYOx50CoERRE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=kH+j16AdB9nP3+e5K9UnMNOp3dA45iUILNa7uHtttrsiJpe+DoQX6ZwU16GTIJkhFz mepyx0zZpjRrl67w4fkC9XdiA2EzMI21VcmrN6hUDu7SViHPTfhd0mrFrrxNo7FPWLP8 n1oFp9Pdzm3VQ4rh+hC1g1bLivCFbRHzagHp+LEJQ9lHWbRyVq+Uo/rxfzlji5fp17Eb R6ZRCiKVph/0GZQ0yMRrxIzNWagyEtIY1yi8HzzLUEg6KqbRhYcaIV3l6HfBkdGTUR7v FZO3wCz0VRHdfdtvfQtZiiA8NvpnGB29xlZYWbjJgSb+9KgjWi7ussn5duzo7jkI6/jD twag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l9IWPIs6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ei6-20020ad45a06000000b0064c92f86b15si1529686qvb.145.2023.10.19.06.37.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 19 Oct 2023 06:37:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l9IWPIs6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtTCm-0003Y2-Bq; Thu, 19 Oct 2023 09:36:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtTBx-000246-DM for qemu-devel@nongnu.org; Thu, 19 Oct 2023 09:36:03 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtTBt-0001F1-6k for qemu-devel@nongnu.org; Thu, 19 Oct 2023 09:36:01 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-32d9d8284abso5191148f8f.3 for ; Thu, 19 Oct 2023 06:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697722549; x=1698327349; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3ZO8XemeV6MKZJes6/JMerENEJvAmmFZYOx50CoERRE=; b=l9IWPIs6XvPiDF938nzefTqci2yWJcHuj8ZlLqFXVID0Uhh9M3ufj17+E7/Iwzd+cq wiWZ7OwKHFhj7So6if4gtxiKTS1TDzWnORMt7G6Xm3hULrTa8MDhNzASw5prC+woKmr/ vQqXrSoOf6oNn4auETZcS9JAQt7d/bijzlygkY/CBgU0MiS1xhaIFC8JPDwZYt5cnBM7 +18pihWOSMugRlSjl1Wu3CsjceTGGwNnaHjvCNgXVnGO1sM29jWbyadPdv0iX77s5bSf 5epPQPLOFU6pwtQFXFI8SJUKLoQR64PLsZBQ/WWP6+WnE6+kSlrbG2HVMth51vjxKdJ+ W1kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697722549; x=1698327349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3ZO8XemeV6MKZJes6/JMerENEJvAmmFZYOx50CoERRE=; b=fLV3nUoimuR0nN16F1Qntv8/92Ij2ZVtGM+R3KVYAQfs6LUAHNs1R8kGvt1iaGP3HL gsP0oVAiOIt5LdxgLl4QVi7Ue7UWW8vrkVT1H+02RAEWPfmnVNugvS2y6A2LQTyp5EQX pvOwBvSj5HZ4d1PmDTuJY0hDGKaL1XKXJHfBEjasbb6wVIM96gfNMATcPE04I12NDxTF 442GEierE/a81QTOLSWaZs/EHvoAu+B5soYZV12MiA2AvOlyrIiCcuWYX+JZoZmaH0Dn QMoATqGaOvtWBlopUo8Bfi0DG83oJsye+SP1iJPDVzhADugPHzK256owf04y1DgAhXrS DQIg== X-Gm-Message-State: AOJu0Yypum+/Ua0EqcDyu6o2fI01/WsShUuPASRXy87Z7mDxWLp7jeOA w0DLla4saEuonqip42Wm2+FobbljDO7H+WrHB2E= X-Received: by 2002:a05:6000:b92:b0:309:1532:8287 with SMTP id dl18-20020a0560000b9200b0030915328287mr1507404wrb.19.1697722549524; Thu, 19 Oct 2023 06:35:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/24] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero Date: Thu, 19 Oct 2023 14:35:36 +0100 Message-Id: <20231019133537.2114929-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chris Rauer The counter register is only 24-bits and counts down. If the timer is running but the qtimer to reset it hasn't fired off yet, there is a chance the regster read can return an invalid result. Signed-off-by: Chris Rauer Message-id: 20230922181411.2697135-1-crauer@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/npcm7xx_timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index 32f5e021f85..a8bd93aeb2c 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -138,6 +138,9 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) /* Convert a time interval in nanoseconds to a timer cycle count. */ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) { + if (ns < 0) { + return 0; + } return clock_ns_to_ticks(t->ctrl->clock, ns) / npcm7xx_tcsr_prescaler(t->tcsr); } From patchwork Thu Oct 19 13:35:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 735584 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp1521997wro; Thu, 19 Oct 2023 06:41:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF2Q/8MAi3x9E/gOQJbO/ArIkPbrI7qsWdbK9NwMoRZOhOsqGmn43KXAz/1UvQcrshvLXy7 X-Received: by 2002:ac8:5c04:0:b0:410:a088:38f5 with SMTP id i4-20020ac85c04000000b00410a08838f5mr2560886qti.4.1697722913127; Thu, 19 Oct 2023 06:41:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697722913; cv=none; d=google.com; s=arc-20160816; b=Hn00fzQ/AxTRhZeYGDGyX5uRq3d7HclDv21T8z7sLs8sB18iwD7HvvbcQ9YtswNYsE 7eCGrtrGgTM4Fu1zDolNqE7alSaCWIj7bNV0aDZCE8YwfvLyIZMviFvn9zhHF7/omHnG +BlkQWI/QZQBRN1y37HHzTjYX+7KlGc7DgNZ5+sa92Pn8dpXGWt3kI/h/Vehi4QJdCIf M4UyptPKvVvHQ7qrmmssxKyve/JvSR5t5f7oRB/Io6YWldSDUTZDgxy/N/l44mJB4tNU ZvrRLjmkAYFfyzcHzNGPGzmfnF8b5aWFUMPFRhXBOQuVk6c0orGyMLvKCtMbOhltu4Oz gY9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DCEBJydvw/gsEIeAPEKmaoZZ5w+fj2mZw0RxfZs5m5s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=t1qhowkY6esnIC4LhF5xMGL4CDEKkw+FvN6OqBzM4UjADXWs4lKPOjWf+SRZemdR8S 6wY5ZhJ41CiXcZNU/pz71IOqZbN/0IWuUSSGs1Gp9A7u9jXCs5PJSz3MVJe2Yis7iFPX 6F83k5Ncru2kWhvAQeeubvOQRlkXBs5rxgwtrwHsha0hONoDO330tKaHb0aF8HdA+1eq vzSFDR9HDa7suma7RkEoBetFqDRxfC2Q7ifx6pMM7Fwqubqm3OdjW21zZpqrpIW2e1u2 i3TCK/uXdMnoTm9uua9uA8s7yr3aArGTw86DwfKGAq561hKI9eqeeL9uF3HC3Ixb0L6z vA3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vnvB20EI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/24] contrib/elf2dmp: Use g_malloc(), g_new() and g_free() Date: Thu, 19 Oct 2023 14:35:37 +0100 Message-Id: <20231019133537.2114929-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Suraj Shirvankar QEMU coding style uses the glib memory allocation APIs, not the raw libc malloc/free. Switch the allocation and free calls in elf2dmp to use these functions (dropping the now-unneeded checks for failure). Signed-off-by: Suraj Shirvankar Message-id: 169753938460.23804.11418813007617535750-1@git.sr.ht [PMM: also remove NULL checks from g_malloc() calls; beef up commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- contrib/elf2dmp/addrspace.c | 7 ++----- contrib/elf2dmp/main.c | 9 +++------ contrib/elf2dmp/pdb.c | 19 ++++++++----------- contrib/elf2dmp/qemu_elf.c | 7 ++----- 4 files changed, 15 insertions(+), 27 deletions(-) diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c index 64b5d680adc..6f608a517b1 100644 --- a/contrib/elf2dmp/addrspace.c +++ b/contrib/elf2dmp/addrspace.c @@ -72,10 +72,7 @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf) } } - ps->block = malloc(sizeof(*ps->block) * ps->block_nr); - if (!ps->block) { - return 1; - } + ps->block = g_new(struct pa_block, ps->block_nr); for (i = 0; i < phdr_nr; i++) { if (phdr[i].p_type == PT_LOAD) { @@ -97,7 +94,7 @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf) void pa_space_destroy(struct pa_space *ps) { ps->block_nr = 0; - free(ps->block); + g_free(ps->block); } void va_space_set_dtb(struct va_space *vs, uint64_t dtb) diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c index 6de5c9808ef..cbc38a7c103 100644 --- a/contrib/elf2dmp/main.c +++ b/contrib/elf2dmp/main.c @@ -120,14 +120,11 @@ static KDDEBUGGER_DATA64 *get_kdbg(uint64_t KernBase, struct pdb_reader *pdb, } } - kdbg = malloc(kdbg_hdr.Size); - if (!kdbg) { - return NULL; - } + kdbg = g_malloc(kdbg_hdr.Size); if (va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) { eprintf("Failed to extract entire KDBG\n"); - free(kdbg); + g_free(kdbg); return NULL; } @@ -643,7 +640,7 @@ int main(int argc, char *argv[]) } out_kdbg: - free(kdbg); + g_free(kdbg); out_pdb: pdb_exit(&pdb); out_pdb_file: diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c index 8e3c18c82f7..40991f5f4c3 100644 --- a/contrib/elf2dmp/pdb.c +++ b/contrib/elf2dmp/pdb.c @@ -94,18 +94,18 @@ uint64_t pdb_resolve(uint64_t img_base, struct pdb_reader *r, const char *name) static void pdb_reader_ds_exit(struct pdb_reader *r) { - free(r->ds.toc); + g_free(r->ds.toc); } static void pdb_exit_symbols(struct pdb_reader *r) { - free(r->modimage); - free(r->symbols); + g_free(r->modimage); + g_free(r->symbols); } static void pdb_exit_segments(struct pdb_reader *r) { - free(r->segs); + g_free(r->segs); } static void *pdb_ds_read(const PDB_DS_HEADER *header, @@ -120,10 +120,7 @@ static void *pdb_ds_read(const PDB_DS_HEADER *header, nBlocks = (size + header->block_size - 1) / header->block_size; - buffer = malloc(nBlocks * header->block_size); - if (!buffer) { - return NULL; - } + buffer = g_malloc(nBlocks * header->block_size); for (i = 0; i < nBlocks; i++) { memcpy(buffer + i * header->block_size, (const char *)header + @@ -206,7 +203,7 @@ static int pdb_init_symbols(struct pdb_reader *r) return 0; out_symbols: - free(symbols); + g_free(symbols); return err; } @@ -263,7 +260,7 @@ static int pdb_reader_init(struct pdb_reader *r, void *data) out_sym: pdb_exit_symbols(r); out_root: - free(r->ds.root); + g_free(r->ds.root); out_ds: pdb_reader_ds_exit(r); @@ -274,7 +271,7 @@ static void pdb_reader_exit(struct pdb_reader *r) { pdb_exit_segments(r); pdb_exit_symbols(r); - free(r->ds.root); + g_free(r->ds.root); pdb_reader_ds_exit(r); } diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c index de6ad744c6d..055e6f8792e 100644 --- a/contrib/elf2dmp/qemu_elf.c +++ b/contrib/elf2dmp/qemu_elf.c @@ -94,10 +94,7 @@ static int init_states(QEMU_Elf *qe) printf("%zu CPU states has been found\n", cpu_nr); - qe->state = malloc(sizeof(*qe->state) * cpu_nr); - if (!qe->state) { - return 1; - } + qe->state = g_new(QEMUCPUState*, cpu_nr); cpu_nr = 0; @@ -115,7 +112,7 @@ static int init_states(QEMU_Elf *qe) static void exit_states(QEMU_Elf *qe) { - free(qe->state); + g_free(qe->state); } static bool check_ehdr(QEMU_Elf *qe)