From patchwork Thu Aug 8 21:22:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170847 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9117486ile; Thu, 8 Aug 2019 14:27:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqwDkrMTgooDWGgl65ddeVxqPyIVOlPpf1WyY0YzHCkFnQlx/KI9LFQ51YpZtJxVwn4wFvuq X-Received: by 2002:a17:90a:bc0c:: with SMTP id w12mr5764238pjr.111.1565299656086; Thu, 08 Aug 2019 14:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565299656; cv=none; d=google.com; s=arc-20160816; b=jZeG4BM2ryrGb+MMToWU8qu+Qe4SvbmUymyx98GMoo+QVP1Ugpr9dxBOtrBsKecZ1V A8KagTqBzrtX5YFOSPGy/7YGKZAF2oJukMQCV6CwGe3X99yU+IgNMtNrhAlP4h7HeowF TNbXi1e0RNR7q3F8hYDKJbU37JPLiqp06VYlwUHwreU6c+tlxo6RH19dDDMNfpcQLFom kbC//N2KsbEMg2/SfCA3YdbEDynbCfdAqIdmuscc/n+2FoUjROmq/CDflTpHn7H3ezmg DcpXGco+h/qeT7uTNF+ZdEUwCeSLK3EepnA16HsDAplJBA8HG4UeohIJ3azByr/2khPo WMFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=HtWqapwStAQRenrDq9o8EL8v5XN0xK7Qlnq9fUhR6MI=; b=PxqOZxNimsgD867BBzQITfKMTVL/AW7xN7wp3YAbSgqveogz9eRJVdBwJA61Czci3G bFv+lFuaI2NFkrnrzTvrau9SyuLBWPoyaFrlST6/B54EQ/5YChHoaNbFYkyTlI8zsm07 6mD7IFQoAsm+aZXahEjZZieVv0fGppNnEB+xVsJHyxaJey63SZzsvL6x5d4fP0K12ZHK NqDDD7Sh3g4FVdyyQ113IrMBlKeemSOJQNIk1NXzn+AxR1e3NGXFkcZmrW9ADWGoZoZk WmmiZzzpnxgxnuaF3Mf3HDEdSFNG6MBfDSfM60lqyPRmLMrm7rczbQZQtgfcBYTDcijE RERA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si2477467plv.189.2019.08.08.14.27.35; Thu, 08 Aug 2019 14:27:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403970AbfHHV1f (ORCPT + 5 others); Thu, 8 Aug 2019 17:27:35 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:59993 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732609AbfHHV1f (ORCPT ); Thu, 8 Aug 2019 17:27:35 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.129]) with ESMTPA (Nemesis) id 1Mae7u-1iTFkD13hS-00cAUB; Thu, 08 Aug 2019 23:27:11 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Paul Walmsley , Felipe Balbi , Greg Kroah-Hartman , Alan Stern Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH 05/22] ARM: omap1: move mach/usb.h to include/linux/soc Date: Thu, 8 Aug 2019 23:22:14 +0200 Message-Id: <20190808212234.2213262-6-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:7EGvG9MpSe9Tat/1OUNribL9cDQ0sxKW61daPJqVL1gxJb8OEBR SI9Y51w8PPLJpodpTJzERNyjlfay9T96WdETvnRYbl3xr/qBnhKa1ZWca43USmz9o3DJyVu t9C+a53+DEZl/FsNdTps8DotMHx1K7ibwXsZ1KMj0eQ2DvfiVGdgJ4Yiml3uxHEe3+uWfvu V3X2angRNbQEMC+psMg9A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:6raSuf2fSPs=:wswGz7TSCdp6+NKQAd3LV+ 1VzQqn6TcE2KeXFsiXfm75ict2KWKFcc6yl3Ir3rT+HVMJrO85712goOOhgyZTJtuKb8uARXw 9HfSp8RAx72pMfVXkksS0T6Wmw46KXBsf1lcvSEjdorAxfdtdrhBC2BjbmXLQiZRnQokICoc4 SVXx44owCJP7eULDbmM7wsX/0eapZUGoxY25crfKSsnoYfpFwjZK9nlv1j4n1eymS65qreupi RpbBgCS3eRRpm25/7VpOsxve1pH9xPOtL5enxzwBMgciTGHFqCEgLmjM37wEqzcJjuwGZ6P6I m/Tu3FO2B1riROySQq5FcVBB7kwaeouWw/TC3EX5FYsoGG3e+sfR9zQilXVte/kD/ywuYPek0 othyya7ws7YFE3z0XOzoISXPnur06nOn+yExHUkP2y7YlDmLMOmQHiNh2cLcsIOT0WThemZko L2vgYD4B6H9fWGoo5w5loHqFbgxH1HqjhSYSmYCHk8qbNhSEGVZKuC/+hVdoSJUWPV8WqbwHo uTcqWydcd7e83PJbXkdbXIOltuNTahVYFI5CA65z+3/6QYbOk0eaWA8kGvkAeHVtygRQH04e7 PFBaApAuDBMpA9BjMdmO0w1H8idanXAettibgGtEPp4S5toAxksUz1IOg8WMg2UMdAg+RCZHx Vgep4U5+Oy0SUR3XxbDD+8HnOfOHsU2HbUeg9mg1gcAOJweqOeKfDNU/k9hVT90G1qQdQGWCP m0CuqU4ZOuQzLsFfxbMJfT3g/Bum8mX6oacmhA== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The register definitions in this header are used in at least four different places, with little hope of completely cleaning that up. Split up the file into a portion that becomes a linux-wide header under include/linux/soc/ti/, and the parts that are actually only needed by board files. Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/board-ams-delta.c | 2 +- arch/arm/mach-omap1/board-generic.c | 2 +- arch/arm/mach-omap1/board-h2.c | 2 +- arch/arm/mach-omap1/board-h3.c | 2 +- arch/arm/mach-omap1/board-htcherald.c | 2 +- arch/arm/mach-omap1/board-innovator.c | 2 +- arch/arm/mach-omap1/board-nokia770.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-omap1/board-palmte.c | 2 +- arch/arm/mach-omap1/board-palmtt.c | 2 +- arch/arm/mach-omap1/board-palmz71.c | 2 +- arch/arm/mach-omap1/board-sx1.c | 2 +- arch/arm/mach-omap1/clock_data.c | 2 +- arch/arm/mach-omap1/usb.c | 2 +- arch/arm/mach-omap1/usb.h | 25 +++++++++++++++++ drivers/usb/gadget/udc/omap_udc.c | 3 +- drivers/usb/host/ohci-omap.c | 4 +-- drivers/usb/phy/phy-isp1301-omap.c | 2 +- .../usb.h => include/linux/soc/ti/omap1-usb.h | 28 ++++++------------- 19 files changed, 52 insertions(+), 38 deletions(-) create mode 100644 arch/arm/mach-omap1/usb.h rename arch/arm/mach-omap1/include/mach/usb.h => include/linux/soc/ti/omap1-usb.h (86%) -- 2.20.0 diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index e47a6fbcfd6e..2d63db557792 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -39,7 +39,7 @@ #include #include "camera.h" -#include +#include "usb.h" #include "ams-delta-fiq.h" #include "board-ams-delta.h" diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index c62554990115..8ef0a9b17e92 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -21,7 +21,7 @@ #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index cb7ce627ffe8..92a31727a069 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -41,7 +41,7 @@ #include "flash.h" #include -#include +#include "usb.h" #include "common.h" #include "board-h2.h" diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4249984f9c30..86260498c344 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -45,7 +45,7 @@ #include #include -#include +#include "usb.h" #include "common.h" #include "board-h3.h" diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 258304edf23e..f7220b60eb61 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -31,7 +31,7 @@ #include "mmc.h" #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 653af63320a8..f169e172421d 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -34,7 +34,7 @@ #include #include -#include +#include "usb.h" #include "iomap.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 11511ae2e0a2..e43c852103f5 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -31,7 +31,7 @@ #include #include -#include +#include "usb.h" #include "common.h" #include "clock.h" diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 3be7b3b580d3..99ebe4503787 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -51,7 +51,7 @@ #include #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index ce6f0fcd9d12..4ac981c5cf74 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -38,7 +38,7 @@ #include #include -#include +#include "usb.h" #include "mmc.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 8a08311c4e05..e48ae5fbe1b1 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -38,7 +38,7 @@ #include #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 034e5bc6a029..37db0ab31528 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -40,7 +40,7 @@ #include #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index bb9ec345e204..0965b1b689ec 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -38,7 +38,7 @@ #include "board-sx1.h" #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 3ebcd96efbff..ef46c5f67cf9 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -22,7 +22,7 @@ #include "soc.h" #include -#include /* for OTG_BASE */ +#include "usb.h" /* for OTG_BASE */ #include "iomap.h" #include "clock.h" diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 740c876ae46b..a9deda073822 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -16,7 +16,7 @@ #include -#include +#include "usb.h" #include "common.h" diff --git a/arch/arm/mach-omap1/usb.h b/arch/arm/mach-omap1/usb.h new file mode 100644 index 000000000000..08c9344c46e3 --- /dev/null +++ b/arch/arm/mach-omap1/usb.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * fixme correct answer depends on hmc_mode, + * as does (on omap1) any nonzero value for config->otg port number + */ +#include +#include + +#if IS_ENABLED(CONFIG_USB_OMAP) +#define is_usb0_device(config) 1 +#else +#define is_usb0_device(config) 0 +#endif + +#if IS_ENABLED(CONFIG_USB_SUPPORT) +void omap1_usb_init(struct omap_usb_config *pdata); +#else +static inline void omap1_usb_init(struct omap_usb_config *pdata) +{ +} +#endif + +#define OMAP1_OHCI_BASE 0xfffba000 +#define OMAP2_OHCI_BASE 0x4805e000 +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index f36f0730afab..721c9c3fe5a7 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -40,8 +40,9 @@ #include #include +#include -#include +#include #include "omap_udc.h" diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index e92ef3231f2c..841563fba20d 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include #include @@ -37,8 +39,6 @@ #include #include -#include - #define DRIVER_DESC "OHCI OMAP driver" diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c index 7041ba030052..18cf87dcc21f 100644 --- a/drivers/usb/phy/phy-isp1301-omap.c +++ b/drivers/usb/phy/phy-isp1301-omap.c @@ -25,7 +25,7 @@ #include -#include +#include #undef VERBOSE diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/include/linux/soc/ti/omap1-usb.h similarity index 86% rename from arch/arm/mach-omap1/include/mach/usb.h rename to include/linux/soc/ti/omap1-usb.h index 5429d86c7190..67488698601a 100644 --- a/arch/arm/mach-omap1/include/mach/usb.h +++ b/include/linux/soc/ti/omap1-usb.h @@ -1,34 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOC_TI_OMAP1_USB +#define __SOC_TI_OMAP1_USB /* - * FIXME correct answer depends on hmc_mode, - * as does (on omap1) any nonzero value for config->otg port number + * Constants in this file are used all over the place, in platform + * code, as well as the udc, phy and ohci drivers. + * This is not a great design, but unlikely to get fixed after + * such a long time. Don't do this elsewhere. */ -#if IS_ENABLED(CONFIG_USB_OMAP) -#define is_usb0_device(config) 1 -#else -#define is_usb0_device(config) 0 -#endif - -#include - -#if IS_ENABLED(CONFIG_USB_SUPPORT) -void omap1_usb_init(struct omap_usb_config *pdata); -#else -static inline void omap1_usb_init(struct omap_usb_config *pdata) -{ -} -#endif #define OMAP1_OTG_BASE 0xfffb0400 #define OMAP1_UDC_BASE 0xfffb4000 -#define OMAP1_OHCI_BASE 0xfffba000 -#define OMAP2_OHCI_BASE 0x4805e000 #define OMAP2_UDC_BASE 0x4805e200 #define OMAP2_OTG_BASE 0x4805e300 #define OTG_BASE OMAP1_OTG_BASE #define UDC_BASE OMAP1_UDC_BASE -#define OMAP_OHCI_BASE OMAP1_OHCI_BASE /* * OTG and transceiver registers, for OMAPs starting with ARM926 @@ -126,3 +112,5 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata) # define CONF_USB0_ISOLATE_R (1 << 3) # define CONF_USB_PWRDN_DM_R (1 << 2) # define CONF_USB_PWRDN_DP_R (1 << 1) + +#endif From patchwork Thu Aug 8 21:22:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170850 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9119567ile; Thu, 8 Aug 2019 14:30:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqywsoaSOD2CAhulKhQ4MtovOvzzz6SPwEucXHpC9vS9ciX1mSkxMpFFxJ/6n/UwgLGci/5k X-Received: by 2002:a17:902:728b:: with SMTP id d11mr11906670pll.265.1565299808075; Thu, 08 Aug 2019 14:30:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565299808; cv=none; d=google.com; s=arc-20160816; b=YWS6C7D7exs3zj/5xjigXIUsqNmCE3ivzoXOTYhxohyMvMNqxXTMlZEd8r1AA/GXWh NgqvF11xsUJwKosJFsAhV3PWRY10kZJXSDfggJ5oCbibuRWNy/OyGdclVRUz0jWhhsWN +8Sx0yBk1gp8QmfCzDqHBeTnHueeOaWqpB8p43VL5IcigsxYaDGrmAAcxgtSMm+01Sw/ D6ddU5uCy7UUbhM97OshDpXzwcdzCwwF4nHJwgp9GJjanX/6z3IEGAxlR3MqvrFvavCm mMnZCDZTm+tDDGxNu1yCG30X6RBPPLoTsbfza7tMjCCLObPG4zr60Vj3oaI0c1AdT0GL NXbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5JCNXA3w6m5E3yKL+CR4jcJA3crcfOsGPw5k+a78rjM=; b=uTAc8Kp4fpQ8jdgN2DgQd0FuzGr/izV+OChj/RR0izP7bYWQRrrjcyuvoG+aE9I71t rgqcQu4t7P9Ei8Pe0cxewlMZ9VJqO2joALkHBbvDZbPe6tDj1rwwc03JBK6uQJb9+fPc J0uQKy6LDX+2W8053GEszP/TuqiHDWHpjeU3FLM6EvJkoyKJffIaPFVkATLCnNSJMSbM 8yq3fD2iD7JPWSaMN7haNe9eelndD+kOqxMzsdztUE2/kFQAS/WUfummNLT7Cx5NrXnP ZXV80lNEV3t0Sx1a/cqblw4MNMRNujXTAe0N48Zr4TJIxsuPvP6XkHE9yE8W+H1vaCH6 2s7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 36si3514884pld.289.2019.08.08.14.30.07; Thu, 08 Aug 2019 14:30:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390430AbfHHVaH (ORCPT + 5 others); Thu, 8 Aug 2019 17:30:07 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:59461 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729780AbfHHVaH (ORCPT ); Thu, 8 Aug 2019 17:30:07 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.129]) with ESMTPA (Nemesis) id 1M3VAI-1hwOCu3Lmc-000coR; Thu, 08 Aug 2019 23:29:38 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Dominik Brodowski Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 08/22] ARM: omap1: move CF chipselect setup to board file Date: Thu, 8 Aug 2019 23:22:17 +0200 Message-Id: <20190808212234.2213262-9-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:RnYUAFwmM2m8m3O3+HxSSuGDaMoTlH+cBY3+Em0tOAfUOFvgiWl DGMc8fUF062WVjG28ZUaUjq8Rg2rNw40pVJ58L5chj9rpHv7J9L6TBrJIbFnL2h5o1QXtr+ N1LXPAFl2IyKboH9pXfEpzkQKV8H24+tFDXlUzWzf7JVy+Fjg4ifDix1Jwg3YkZHCkarvJT lUbx971y+k3+es6cqk4IQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:3VR5CSysz1I=:iP2/yKLl57ITrfMx5hjul6 Bha0XcVmbYovcD/iBBKCj1uzDy6KT6vwjB4AwlmFrHTUgLY8BZ9tMa4Ik7mrU7uwssU8dIisD hsTQV37EhUVgQdj5dgWluuFjcN3+pa0+qH8W6b5QTm5+wheWeI/mTSjcDhLxfQNnE5M27rAoN 6w5kFCm9zXloTf7MTln36UQhMBuBD6KtIy/qB9QqAkBv6VgyfYm4eSf+fZnxuOr9ySD3fXtxq gzhLRHVOq5nbGPWiTU3CdSzJNL9vEYA/k+TyRbOGjMysq24f1xzKvsQXGTnozTh1iOoAV0UN1 nfg991BHUM03zZIqEM95pXgK9tQmmT8B+0FLs/JLIZAwRASO+7qWrnAhW3lrbgcqIHipijx3u u1Iwn6jv+L0/O+2PC7Lm1XH57FCtrqKSc/stl7FR+4o5GeSWmMXogqHTBETKwdGIllisM869y +Ivw/KTqHMoHIyoHfAmV7FOx4KLiohSYfUsdZnaEMwzi/sipZ58arT/gYewDn9Lg2nq3F2u+2 80KDfRMKJtWwoF/0bYnvEudR4BUgBsigLclTvrYtOMpTkK0LA/5GuKjikcV63LsE6SwjMOuaW Zh6xUwqQTt98d4Sui0D7PxTTOOxySM2Ra1SL0fUEGqJEMs86urCOWEVa4Bc9L/Xfk+5Ko5cAq LSrjWl+ZK+HnowMJwtfwlKxQ+lNLoHCvP5dKyjDiWHgSlPIz0yfWER7OdqfmoBiqTsDYvi7zs 28RqK/XWNHaas+ei7eQnVMT0HLgv3qFs9OwM9Q== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org There is only one board that uses the omap_cf driver, so moving the chipselect configuration there does not lead to code duplication but avoids the use of mach/tc.h in drivers. Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/board-osk.c | 38 ++++++++++++++++++++++++++++----- drivers/pcmcia/Kconfig | 3 ++- drivers/pcmcia/omap_cf.c | 38 ++++++--------------------------- 3 files changed, 42 insertions(+), 37 deletions(-) -- 2.20.0 diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 99ebe4503787..38d73da5d13d 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -149,14 +149,14 @@ static struct resource osk5912_cf_resources[] = { [0] = { .flags = IORESOURCE_IRQ, }, + [1] = { + .flags = IORESOURCE_MEM, + }, }; static struct platform_device osk5912_cf_device = { .name = "omap_cf", .id = -1, - .dev = { - .platform_data = (void *) 2 /* CS2 */, - }, .num_resources = ARRAY_SIZE(osk5912_cf_resources), .resource = osk5912_cf_resources, }; @@ -267,13 +267,41 @@ static void __init osk_init_smc91x(void) omap_writel(l, EMIFS_CCS(1)); } -static void __init osk_init_cf(void) +static void __init osk_init_cf(int seg) { + struct resource *res = &osk5912_cf_resources[1]; + omap_cfg_reg(M7_1610_GPIO62); if ((gpio_request(62, "cf_irq")) < 0) { printk("Error requesting gpio 62 for CF irq\n"); return; } + + switch (seg) { + /* NOTE: CS0 could be configured too ... */ + case 1: + res->start = OMAP_CS1_PHYS; + break; + case 2: + res->start = OMAP_CS2_PHYS; + break; + case 3: + res->start = omap_cs3_phys(); + break; + } + + res->end = res->start + SZ_8K - 1; + osk5912_cf_device.dev.platform_data = (void *)(uintptr_t)seg; + + /* NOTE: better EMIFS setup might support more cards; but the + * TRM only shows how to affect regular flash signals, not their + * CF/PCMCIA variants... + */ + pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", __func__, + seg, omap_readl(EMIFS_CCS(seg)), omap_readl(EMIFS_ACS(seg))); + omap_writel(0x0004a1b3, EMIFS_CCS(seg)); /* synch mode 4 etc */ + omap_writel(0x00000000, EMIFS_ACS(seg)); /* OE hold/setup */ + /* the CF I/O IRQ is really active-low */ irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); } @@ -577,7 +605,7 @@ static void __init osk_init(void) u32 l; osk_init_smc91x(); - osk_init_cf(); + osk_init_cf(2); /* CS2 */ /* Workaround for wrong CS3 (NOR flash) timing * There are some U-Boot versions out there which configure diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index e004d8da03dc..ca6e2ac2a92f 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -250,7 +250,8 @@ config PCMCIA_VRC4173 config OMAP_CF tristate "OMAP CompactFlash Controller" - depends on PCMCIA && ARCH_OMAP16XX + depends on PCMCIA + depends on ARCH_OMAP16XX || (ARM && COMPILE_TEST) help Say Y here to support the CompactFlash controller on OMAP. Note that this doesn't support "True IDE" mode. diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index 0a04eb04f3a2..98df6473034d 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c @@ -16,13 +16,12 @@ #include -#include #include #include -#include -#include - +#include +#include +#include /* NOTE: don't expect this to support many I/O cards. The 16xx chips have * hard-wired timings to support Compact Flash memory cards; they won't work @@ -205,6 +204,7 @@ static int __init omap_cf_probe(struct platform_device *pdev) struct omap_cf_socket *cf; int irq; int status; + struct resource *res; seg = (int) pdev->dev.platform_data; if (seg == 0 || seg > 3) @@ -215,6 +215,8 @@ static int __init omap_cf_probe(struct platform_device *pdev) if (irq < 0) return -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + cf = kzalloc(sizeof *cf, GFP_KERNEL); if (!cf) return -ENOMEM; @@ -230,24 +232,7 @@ static int __init omap_cf_probe(struct platform_device *pdev) goto fail0; cf->irq = irq; cf->socket.pci_irq = irq; - - switch (seg) { - /* NOTE: CS0 could be configured too ... */ - case 1: - cf->phys_cf = OMAP_CS1_PHYS; - break; - case 2: - cf->phys_cf = OMAP_CS2_PHYS; - break; - case 3: - cf->phys_cf = omap_cs3_phys(); - break; - default: - goto fail1; - } - cf->iomem.start = cf->phys_cf; - cf->iomem.end = cf->iomem.end + SZ_8K - 1; - cf->iomem.flags = IORESOURCE_MEM; + cf->phys_cf = res->start; /* pcmcia layer only remaps "real" memory */ cf->socket.io_offset = (unsigned long) @@ -269,15 +254,6 @@ static int __init omap_cf_probe(struct platform_device *pdev) pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq); - /* NOTE: better EMIFS setup might support more cards; but the - * TRM only shows how to affect regular flash signals, not their - * CF/PCMCIA variants... - */ - pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name, - seg, omap_readl(EMIFS_CCS(seg)), omap_readl(EMIFS_ACS(seg))); - omap_writel(0x0004a1b3, EMIFS_CCS(seg)); /* synch mode 4 etc */ - omap_writel(0x00000000, EMIFS_ACS(seg)); /* OE hold/setup */ - /* CF uses armxor_ck, which is "always" available */ pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name, From patchwork Thu Aug 8 21:22:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170852 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9121489ile; Thu, 8 Aug 2019 14:32:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyThmi+zPy2pLaCEqLUi6bwjx69Pp7RTLUzpzAzGs/UgVmuU+chaYnhcXcLNBtx+KQPOmRD X-Received: by 2002:a62:3895:: with SMTP id f143mr17528311pfa.116.1565299924050; Thu, 08 Aug 2019 14:32:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565299924; cv=none; d=google.com; s=arc-20160816; b=tQ8+JjyjSgb4RctIWYgTT69qGIcrSkq0gjOGiaRsymd0852Wcfju9O+jTuuigyqqTC /I61iHcePxgSCvTiubNNZ+InxDRkfW8tx/bzYyRGgLYm49CS5/kcgyos4VU4DeQNC8iW Lg3794rr+2g0ObVnfNwn5u6qF94TM/dKNBTiazW/X+fDM9SPWR6U6cRf9EidB4KJCjnd uh3dVzw0MLkIJwecn+kJmbBCxFJ+4Fqvbqg8oREXZrFPoMfCk3cQR6B1J6AcD+E6RSQG VS0SHcDf5gdv5jq8MOTz7PtwirXkSVy2m188i6A/YR9+gcpdj7bx6gFVHoK40bknAWHF 98FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=xHjhPRQhVcykejQja7xu5zkJYJMoOvKlGzfN28Trek0=; b=jU7NeeZjYchdqswtNHS7Trg3lvBoEPcLjeEWmtUMAOPp58ihcm8zDjbjHuYzjzFxMF cWst4adAZmPh6ZKDYIcJloBpWVj7k1yIIPhFoYZGN3PXLGLhDaGg5IRdBo6Fuf/1dAT8 79tlR61VrnTy26YKeg6mf/xX6zJ3wQxFJa2lKaz9juPCYyy2SssL7tmiwEr+XctIJMp+ h6fZ9CSbnQ4YW3ZByW/pc6+gpuO4iMqmfss31LGZer77HR/xSSXpklvjOA6kDZHc9AHZ Z6GzE/Yemc67b2+jN7I3pOaMpyHpwHmYHJ7bzMRw9Tq0RG/Ve7d98LtNOGdqTPYy7F4d b2QA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x130si57793428pgx.526.2019.08.08.14.32.03; Thu, 08 Aug 2019 14:32:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728020AbfHHVcD (ORCPT + 5 others); Thu, 8 Aug 2019 17:32:03 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:43579 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390151AbfHHVcD (ORCPT ); Thu, 8 Aug 2019 17:32:03 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.129]) with ESMTPA (Nemesis) id 1MOm9H-1hgDtV07kV-00Q9Tu; Thu, 08 Aug 2019 23:31:38 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Felipe Balbi , Greg Kroah-Hartman , Alan Stern Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/22] usb: omap: avoid mach/*.h headers Date: Thu, 8 Aug 2019 23:22:19 +0200 Message-Id: <20190808212234.2213262-11-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:K8p91cbBYQ5A6juVoYtAsHFWMTNlYAsjgZ8+WIV+MCLOAHAN+bI 9MmlQhFN1ZowAxZ2w9fUiyN+IDd8DmdzaDEwPUwTeCdhZom/wIlrusHmEAlUofR52EyMf+e 5eRWH1Am5fD3Nt9jU6lvvx7GI4Ud+CVsUuDyp00MS9K9a9/2I83Ahg4E5lqMvM2KP7M60r4 v1lqaRtJAhI5kuZaXg0tA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:d64A3weE10U=:stpqXJN3P6K37+8vT1wNmi w2ZB0cYFfx2bIMi755d558sXZJ4Ikum1Pc5j7XFqiKdcZlsJLE4aR4MdO72rRkd1/KfcVcvQz WUf56OUsz83T4vUdgyOZQMuZR3MlKXpGa53RKx6/OLEeEfSRb4D4hMN0spyhJv/TTT7oJs/th 1SVpt9luHJ3d+6AfznWsujYZLEKvV0xsxzmbzTlsstKOS8JgQtoU0WHZJ3LE4jlmvAxDjEaZt zIuSZyXlPGJf+vxOIATOkABFt408UThVINSP/yXFxVcfhhkpFcdCWELRnHEzcaKEBoAoZgK+n NDUUAHNOqFV5/oFLXo8aLJPal7sPHJslOZPbB5ij3vDkEtnVfshyPA6v04LGEaxyUmT6QS+FT 7XxR4EF6ScOzbmnzgvLw42bvw11PuhJiiIHRAcuNJADkMOJIiLv8DCZEnjc4fEQNYpk/8Ie9w 7LjutujJNs8+VMPWkZqp07RNwpW3zxOCZ1xJZwO/VNbPQz0oxsbe+7FCULX+uZZXNaSCv9Uq/ WuZz1xuttxDEkT5xYTDdplbMiJ0Tmzm3NHiiCqh7wLeLDtlC5DObut2TXL/VXVPM+rRYbS8Lk cth6BTlmBj/47eFsfiuczPUILFHZ3PAmbZ2cDSkvp4r5OPKpP6UNeiufJrtKfIVPv91bHBVqt qxlAcwYcjCQbsN+S/9LysYAVKNLFhTy8OiOfZF1NejD4/iyi1cYXJQpcXoYF6Fr5hEjgNK2vv wvNvx4b7vfBdtG9p2QGmSQbbejnM9UZXlH83qw== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The omap usb drivers still rely on mach/*.h headers that are explicitly or implicitly included, but all the required definitions are now in include/linux/soc/ti/, so use those instead and allow compile-testing on other architectures. Signed-off-by: Arnd Bergmann --- drivers/usb/gadget/udc/Kconfig | 2 +- drivers/usb/gadget/udc/omap_udc.c | 2 ++ drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ohci-omap.c | 7 +++---- drivers/usb/phy/Kconfig | 3 ++- drivers/usb/phy/phy-isp1301-omap.c | 4 ++-- 6 files changed, 11 insertions(+), 9 deletions(-) -- 2.20.0 Acked-by: Greg Kroah-Hartman diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig index d354036ff6c8..ac0891a3dbf2 100644 --- a/drivers/usb/gadget/udc/Kconfig +++ b/drivers/usb/gadget/udc/Kconfig @@ -128,7 +128,7 @@ config USB_GR_UDC config USB_OMAP tristate "OMAP USB Device Controller" - depends on ARCH_OMAP1 + depends on ARCH_OMAP1 || (ARCH_OMAP && COMPILE_TEST) depends on ISP1301_OMAP || !(MACH_OMAP_H2 || MACH_OMAP_H3) help Many Texas Instruments OMAP processors have flexible full diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index 721c9c3fe5a7..27b6142ea803 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -43,6 +43,8 @@ #include #include +#include +#include #include "omap_udc.h" diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 79bbce685583..e566a99bc8c9 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -201,7 +201,7 @@ config USB_EHCI_HCD_NPCM7XX config USB_EHCI_HCD_OMAP tristate "EHCI support for OMAP3 and later chips" - depends on ARCH_OMAP + depends on ARCH_OMAP || COMPILE_TEST depends on NOP_USB_XCEIV default y ---help--- diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index 841563fba20d..be3571778b60 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -27,6 +27,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -36,10 +39,6 @@ #include #include -#include - -#include - #define DRIVER_DESC "OHCI OMAP driver" #ifdef CONFIG_TPS65010 diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 24b4f091acb8..c6b2559fd334 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -30,7 +30,8 @@ config FSL_USB2_OTG config ISP1301_OMAP tristate "Philips ISP1301 with OMAP OTG" - depends on I2C && ARCH_OMAP_OTG + depends on I2C + depends on ARCH_OMAP_OTG || (ARM && COMPILE_TEST) depends on USB depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y' select USB_PHY diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c index 18cf87dcc21f..0f3475e91403 100644 --- a/drivers/usb/phy/phy-isp1301-omap.c +++ b/drivers/usb/phy/phy-isp1301-omap.c @@ -23,9 +23,9 @@ #include #include -#include - +#include #include +#include #undef VERBOSE From patchwork Thu Aug 8 21:22:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170853 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9121965ile; Thu, 8 Aug 2019 14:32:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxt29jgSyoZCvXOxh/gn+Wn2kaY2eW88Tvvp/nr9D6asZjHSwuAWAu5dWqCf9Zfd6oFjBZI X-Received: by 2002:a62:cd45:: with SMTP id o66mr17960361pfg.112.1565299950962; Thu, 08 Aug 2019 14:32:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565299950; cv=none; d=google.com; s=arc-20160816; b=wsZiEslcouVcozVg8VB4oLb7LmIJnlOlutAF+Cwm/RvOchq0Dd5qoWSQmMjhU/9tVS 55h1UR5DFouBX0xRSrY5iPPy4VryiKF11zAMWXm+jtM/ZSdQeCqcrzjv23TSCqPFy1gk LIQqvejqJ+TxCqmzaoPE9wSbKhIRDzlfoxfoddQpkFrWC4+1kcWpESWNEtGfEgUQFJzT vQGAN4X5QYOVj9y7Rtfl11hXMBrcKTEiaH8RMKef+iIr8jF3wEpsnu2nASLdam+5P9ZI cfVy2cp0bE2+FveZuAFPhYAMxqJfOkJvvBHPWKqUUk+X/qs7KjGwDlo7K59kpN52iF/S tzFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=EgizjEc6UeyYLnJOkNW6YpP71Q2EBtH8vOYrH18gk2A=; b=aNK6NWs95eHTO1VtB7I1/yFt9kkc5JH26hr+qyX9wo+pfA5gfmObKTtRy+5cer6uL/ LMYsx0IY256HWVypUSMcCSu8rvF7PZb/sU3S/YAme+GGeMk8KnFIYcqwnWa+gQvsBR1l T0+LTXHInYzSTDKzn3xrcUMeFLtGzOLRxHeUqIQdc7EWizmKfjCe5sqs50qgco9opHji HwNxupRD4Vfz6MdZzpn6+qIYANVqMyxTScCeJ/oTD0NlrgQcp6e9mJhKAkQ0pX3v+seg abKEFx1KY/AW74/nwBa5K+C1IGGpRW3rJQ40WySxOLrYS8uezieH0hQzU3magP5MTsWB y9cw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c3si2812756pje.1.2019.08.08.14.32.30; Thu, 08 Aug 2019 14:32:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403798AbfHHVca (ORCPT + 5 others); Thu, 8 Aug 2019 17:32:30 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:59617 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730768AbfHHVca (ORCPT ); Thu, 8 Aug 2019 17:32:30 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.129]) with ESMTPA (Nemesis) id 1MHEPI-1i93Qp43sm-00DK8b; Thu, 08 Aug 2019 23:32:04 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Daniel Lezcano , Thomas Gleixner Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 11/22] clocksource: ti-dmtimer: avoid using mach/hardware.h Date: Thu, 8 Aug 2019 23:22:20 +0200 Message-Id: <20190808212234.2213262-12-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:3tljNrXw83+F4Hazcc57iyTVuqcANP1caRyw1sEvbkwOygXkbr1 2ASndSMUrdeHCNbt1U3/d4g6qDaH9k8V17XP2mqlGCEr/0WkuW4dpT0luK3Ib7tzCq3jePR BGIFP9qnN11wrBgaVcqYGbcuHh66bIzNhqhuwqjrw5DHew75jqoOoa8BFA3OkhD3Df5sApL 8Rp7aRufJofird7OveVzg== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:c+WCVkEggaY=:c38mMZPYd8pl1vXQe/HjSA DBUWUCNFjnUJbBngyRKBRfKPQh7GsHAImDc+yv3V7nryPEmK/AmVc0yULOOpMsZRogR9HyphU IUkECTgE4tRvMXh9k64YOLT8YnXTq5QuxwoV9XwFj4F3GHhkrsJ6bFp30AnMG/D2f2ZsafdG4 yTzGXMB2SLhbHRGbxywX4gIz7ERYYwsWlbvmjHxGnS1E5p1E0E88XsCZSGQz0MHCmQckQOkE+ 2YsOUR4fllQDmC1aTYZFqJjY+2amkjolTkB+F3G5vrDW3efKKAoga5h4ZujEjLAlahRw8zpK6 lqrPBFihWNmjchEyQkPqsMIMAsrLCia9XhWzLfB6l7e/1hk4ZpBVHK5mKTv1MBj8T8n7dsEEh Y6WSDp9awK/eLo4MwI8Dw4VQSsIXA1AX76bqXMKoA6mmkEVaTW98dgPgPgNNu/6JtWg9WkjrH 5VcOE42yVkZLddcgBxeBhxQ6DQ48Q1VbzXZTuQADwcme5dJZvMC4xgv9ocOHIdf5+4RF4J7Jt 3lVUGDobZk45oXSv3t5vfWa+zh/oo1cRc8w05FzGCgRVvUXucWsIKMtnBI5JsYSvoesblkdiz sWZNvg6+WbPYA+hFDWF3Nc3jlTEm9ppDVyuk5gKxn5tRriaHB0xXHyVyVdYf3FvAiJoz/gBS5 2JRVH49k0FFL7f+CUQC7jnAOzJ34LYZceQlNBkqIsEBjBhM39l9iSQButSSt9PowGTmOyEa8n bXNX4gD8IhG84AdyKAiVXFr1ylArol+ND1mdAA== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org As a preparation for future omap1 multiplatform support, stop using mach/hardware.h and instead include the omap1-io.h for low-level register access to MOD_CONF_CTRL_1. Signed-off-by: Arnd Bergmann --- drivers/clocksource/timer-ti-dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.0 diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c index 5394d9dbdfbc..422f96384dc5 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -448,7 +448,7 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer) } #if defined(CONFIG_ARCH_OMAP1) -#include +#include static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) { From patchwork Thu Aug 8 21:22:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170856 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9123045ile; Thu, 8 Aug 2019 14:33:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyHZRWKJb0ATJZ+L1pzIMZ6Xlsy0y634MHuXdeg0AjMYOn80zVP3Qq+11YN/T7WxSNe7Px2 X-Received: by 2002:a63:c64b:: with SMTP id x11mr14434018pgg.319.1565300017693; Thu, 08 Aug 2019 14:33:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565300017; cv=none; d=google.com; s=arc-20160816; b=t5g6A8DBKCDA+zGOuCAdvvxWUO8LXyNpCn7OdFoionqCMvME0HOr+EqjC9xw16C1Sk lF3beD+1iXy/4wXeb6OIHGJ+GMU4K9WJOVnnTHoMQftl4ZxA9UKNw0xKGYKc9n4m77QA jSS+SqN1R//KxEsceEgqob/yjkikcTjIzrdB/coa6eM08hpWp2qRBnuG4LdUp6Pm3KNd dtutAskSbGHQPHbrdEZKZEbZnszZWIrXBVBKAv34g7go2AuYgQ3FZehbAdJOxcW84g3t 69rowUBPHQPuEdHXfSuSRmRUtgVBwG/s6D9dF1pdTBSn+WY8AC58oAPq3Hgvu8rhLNgI zfbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Y0prPd/hVnyiOegmCAosmg9P5KmhNdoVuacX1qETRqw=; b=KlQ6klRs+ZJptxm/rYjYJRowu4DThLJmofkd/VWAB/xpi57K0xbeF2KUDZDN+pK70C L2dNAHP7FLg7PiJ8LINdUl4NbiUl0Erny6iGVYitrZoBbmjBP7m1Ni6dBfDn1ZTzH1UN XvwWZk7OdZSlQr18SeHq5dqiXG8M4tIHIbxKu1a8ja4AAU0nZ3vBPKvVO4JzF9DdW3WK 5nKlHlUHibUHhVszgw8tdfNW9iLFuXKZeH5PWy8wuMK3aAOPlcDYNPjVj7fxubukowEx ZY8eAnjxd+gdGK/43YeVgmq1rpHETEQNh7/Q0TMnB3mXZEDaE0A522tzIQHm2b8gM2s6 vm6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 4si55654404pfo.266.2019.08.08.14.33.37; Thu, 08 Aug 2019 14:33:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730768AbfHHVdh (ORCPT + 5 others); Thu, 8 Aug 2019 17:33:37 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:40783 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728020AbfHHVdg (ORCPT ); Thu, 8 Aug 2019 17:33:36 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.129]) with ESMTPA (Nemesis) id 1Mx0VH-1iGO1F3rXX-00yOIw; Thu, 08 Aug 2019 23:33:11 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Dominik Brodowski Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 14/22] ARM: omap1: use pci_ioremap_io() for omap_cf Date: Thu, 8 Aug 2019 23:22:23 +0200 Message-Id: <20190808212234.2213262-15-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:T0h7JpBfhfIzzYs7SKu4WH/fYD3z37b4wcHxdCbVevtJL0SMgqT MzlFe2+AoIx6riMlQsNqVmF4HbP4A9qrAZpDoYTaYJNHGUGDxJfnK4RioNPDRkftU67cUIM 0EV3FUdLQx3th9oUOUhABs6eV9TtFbK63ICTI9THmC6/PPmRK2yikOBeo1rTEhpHTqw2Omq GGWcW9jBHJVztyQvj1+2Q== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:gXhQq6dGukQ=:HBAKuxIRKY9jeG1BoJ80W9 eBMGVEbY6rqj0cUwfxjAQ471IvOegHVlF+xzSz4u7bfeGr35FS1bL9Sj+aZJwGPJoOvhkv8/g FXX+6vhT/maYfeJTd2/F7SduLYw2F0edqaSV9TExPZ3NMb1VUaJGYNWzNKyjK684aWsxduMzC a0qtr3GAWoyy+7D8yPAVBseTLUHW9wiWBol3cfOHwyBr/qSw5jt1dAxADs5P5mmjMvYmj1dM4 4pQxDFvn/pjNrsG+kdQPDWCMY7PUhRRmZeZ0J+b3E34uUOKisHqhuxGN1VqH8e8ukIwUxOCBh lLsP5v6P49pUsDuZh0UBLeQHQ2VO2bFwEJ2bv61pu8YEz4CnDf2ljOxXrMl0gGY3DMNUzhn4I Dyo+Q45U35zXtbvOw1CgBATdtQDkIsqKpVszduAUa6gXTxHoDaIn70yhaC33rA6G9lsxGN1xv haHVS/EXhnf+z0lEDBfo1VonrUP2raV0QH77x6V8VEGIYk2iLtsj88zf/Uyu4dnHnNESUfH24 4LDinB2dzm9/vXlkNGAlSe1ERpX708QiQbzTiYGzYAtCVOTdmpdt05JLreM1vaGQ77IqBIpq9 me8HJs6u0BUekqyv9tgC2HMOudt4xvEcNcwg57enFk+Ddidd0nC8ILlvDhCEVE5ACaolsL+vV 4yEQKvRDrHOwzlVOjKbNzl9W/7/xIkucERhLnrkAlCzWmic+L+lPNm0+wH3o3+swSEOvuuV5y aIekoO1WYWBMAGamIwyTr1QbjPOmS5muzbBEZQ== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The ISA I/O space handling in omap_cf is incompatible with PCI drivers in a multiplatform kernel, and requires a custom mach/io.h. Change the driver to use pci_ioremap_io() like PCI drivers do, so the generic ioport access can work across platforms. To actually use that code, we have to select CONFIG_PCI here. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 2 +- arch/arm/mach-omap1/include/mach/io.h | 45 --------------------------- drivers/pcmcia/omap_cf.c | 9 ++---- 3 files changed, 4 insertions(+), 52 deletions(-) delete mode 100644 arch/arm/mach-omap1/include/mach/io.h -- 2.20.0 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b7162ac8d756..8263fe7a5e64 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -496,13 +496,13 @@ config ARCH_OMAP1 select ARCH_OMAP select CLKDEV_LOOKUP select CLKSRC_MMIO + select FORCE_PCI if PCCARD select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select HAVE_IDE select IRQ_DOMAIN - select NEED_MACH_IO_H if PCCARD select NEED_MACH_MEMORY_H select SPARSE_IRQ help diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h deleted file mode 100644 index ce4f8005b26f..000000000000 --- a/arch/arm/mach-omap1/include/mach/io.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-omap1/include/mach/io.h - * - * IO definitions for TI OMAP processors and boards - * - * Copied from arch/arm/mach-sa1100/include/mach/io.h - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) - -#endif diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index 98df6473034d..9f8ad82f5fce 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c @@ -235,9 +235,9 @@ static int __init omap_cf_probe(struct platform_device *pdev) cf->phys_cf = res->start; /* pcmcia layer only remaps "real" memory */ - cf->socket.io_offset = (unsigned long) - ioremap(cf->phys_cf + SZ_4K, SZ_2K); - if (!cf->socket.io_offset) + cf->socket.io_offset = 0x10000; + status = pci_ioremap_io(cf->socket.io_offset, cf->phys_cf + SZ_4K); + if (status) goto fail1; if (!request_mem_region(cf->phys_cf, SZ_8K, driver_name)) @@ -281,8 +281,6 @@ static int __init omap_cf_probe(struct platform_device *pdev) fail2: release_mem_region(cf->phys_cf, SZ_8K); fail1: - if (cf->socket.io_offset) - iounmap((void __iomem *) cf->socket.io_offset); free_irq(irq, cf); fail0: kfree(cf); @@ -296,7 +294,6 @@ static int __exit omap_cf_remove(struct platform_device *pdev) cf->active = 0; pcmcia_unregister_socket(&cf->socket); del_timer_sync(&cf->timer); - iounmap((void __iomem *) cf->socket.io_offset); release_mem_region(cf->phys_cf, SZ_8K); free_irq(cf->irq, cf); kfree(cf); From patchwork Thu Aug 8 21:41:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170858 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9131111ile; Thu, 8 Aug 2019 14:43:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqwLVXPfkg/+spfl0luWlGg7ccnEagPpA6XJShtlEOU0cADP8iz8tyUis0wce+G21Rlis6Os X-Received: by 2002:aa7:8202:: with SMTP id k2mr18085234pfi.31.1565300625620; Thu, 08 Aug 2019 14:43:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565300625; cv=none; d=google.com; s=arc-20160816; b=oI66Z8R5QFt18/HZaqyrd6s6Fx5ZikLr7BSmxg64UP7dDub9fTXswLkZEhrfseIJoL HEI4pJ39WcQOl6Kc3aaQMdjY5e8nT3gF96oFdNf00QqthNu9poPab3RuFt9eB9Ud1jn1 a8bTce5isnZiUDLTWlKZ05N3ylgd2gy4XMVSjH9a1jsRFMUIA6O9sMCmP6gutCSHz4DM yh9+F7zPOzWbv8xbCl9PvD10P0x3t7VC9L/nkCJ//dJb8tE+k4vHMrYq8uuD6GNxKXud RhzIh3ICvv+rp4qse6HuHl13rNjxN009tE8lahFoJZrJsvRGqu4yu1oVFCsIBrE//YUm aiTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Ls4TDnNgTL9n8MQaaHDnjRvqxwxTPO+1z3lYCbBLcAA=; b=Wx9Pmf10xwV8eB3I1skTf1pqRLsdJ+wpWSmjzPMBuesxJg9PzZPr3ULzb0OQUKp5jr NnmRuocsP/X3jPzqe4qTIdo/0JiuW8EW+HCK9mDmNxe3MTYr3KoaUjxLIjtzPsS1Vkk5 2gdma6U1wnqnKz1lVLQhpKAeIONl4PfgVcaEbP/44DzbuFLPqU10sfYSfTpyVUpeNqVv ZniS11aW6TMxZJ7BpVhYy3VSiCxG4/+buuwhcaTHsrMqtYQqtn7mXidzN0bj8nYgr4+o 7y2TeWb8DHixb7GsuwAR9HJv1wrqRGPw4eeSjWhX6/NB7p9Vfv9tjxTFDiUfFfhCL+EN x4cg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t134si54042129pgc.361.2019.08.08.14.43.44; Thu, 08 Aug 2019 14:43:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733140AbfHHVno (ORCPT + 5 others); Thu, 8 Aug 2019 17:43:44 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:56213 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733295AbfHHVno (ORCPT ); Thu, 8 Aug 2019 17:43:44 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.145]) with ESMTPA (Nemesis) id 1MGhi0-1i9bYi2gEs-00DsZM; Thu, 08 Aug 2019 23:43:02 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Paul Walmsley , Kevin Hilman Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 16/22] ARM: omap1: move clk support into a single file Date: Thu, 8 Aug 2019 23:41:26 +0200 Message-Id: <20190808214232.2798396-2-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808214232.2798396-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> <20190808214232.2798396-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:esNHGviDobkgGOdcVSEFZe01urPRNHC2Mha6XfJrImPmyRZiCEw mK2n3I7x/p+OzgjiP0Af9UVZZ5DXvUshrOr6cYQLFPojbw+ag93wpDeaYJt7lRhusiha1xZ qbuk/oPK+c63S2jJviggkye41tC8EMRnHHGllWudUrGf1PWLlDGfv/LDDuRgkPd4U+3QngF 1ugdtKkLzOSaVSB/N3+FA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:QS6dRrmqwwA=:OoEPpbFvGeVrTJDY9LOFik EdEHX2VbeyFLWml4uqhbRMAHL7EjBFbTBwJ7OXOtCBKfMUN3YxmEly0sE4WK2lAVwJ73y1RV2 nO9q/TJUISuw145gCsgN5v41K1eKQntWcXB3b9ohWbPM7/v34IC/vuVwE9DgtJl/EToqrfpSx m25djJBPva9EtkiGma4KOt5Pw33ptAu0bujUip4iMUQpbWylyKtezJBLUvCAg15q6kRKPNmlj fw0V9ni5lHppxSqcGs08nFkztlfIJWm6ktcNX4GjECYcKYX0naCQLzyq4xUvkMBdnzH5Yrk4P t/AG2SveaD1gfkauB+W+QwzhESLqkpksmJt7u/nlsEPNBrID2B0En6vpIubybqtyggVIHecRr 3hyC7Rdy3nzhQkNeVHlu5eM+SXbZxMXi07dYYv08seDIowCRJy3fKemd8skB0Zgot4TfI+92b 0IXplxrW/5+4L8lwm0PiedObNWTnrceGTF2V5HYgcDC8MCYqLLN6Kw3SAZ8KegPbiXQDwYDDJ /gYw8xDdgk8Y4dcaUeQsDnIM/QwfPRo0zE+9R5bb9an4jCqJs4thF1971GCncDFiw2KlC1Apa +J+rLUKJW2jsCmC16af8WL4ALqKzB2B4iKMl+pN58i7XMCKPRckVSSRsU+HfK43FqV8J3IDvq m7fgD3FGf1HaZa/lfqrIb9OLrpCbOiS831FsSDwwlrYMPEd3DTcXB316z1tHn3s+MAHO98/AI mMQrTXtBzfC0HI+Hgwyj7JEbowIMJAJISNsLdg== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The omap1 clock support is traditionally split into the clock.c, clock_data.c and opp_data.c files. As a preparation for cleaning this up, move everything into one file. No functional change, each added line comes from an existing file. Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/Makefile | 2 +- arch/arm/mach-omap1/board-nokia770.c | 1 - arch/arm/mach-omap1/clock.c | 1215 +++++++++++++++++++++++++- arch/arm/mach-omap1/clock.h | 288 ------ arch/arm/mach-omap1/clock_data.c | 920 ------------------- arch/arm/mach-omap1/common.h | 2 + arch/arm/mach-omap1/devices.c | 1 - arch/arm/mach-omap1/io.c | 1 - arch/arm/mach-omap1/opp.h | 26 - arch/arm/mach-omap1/opp_data.c | 51 -- arch/arm/mach-omap1/pm.c | 1 - 11 files changed, 1216 insertions(+), 1292 deletions(-) delete mode 100644 arch/arm/mach-omap1/clock.h delete mode 100644 arch/arm/mach-omap1/clock_data.c delete mode 100644 arch/arm/mach-omap1/opp.h delete mode 100644 arch/arm/mach-omap1/opp_data.c -- 2.20.0 diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 450bbf552b57..1337d7a2754c 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -6,7 +6,7 @@ # Common support obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \ serial.o devices.o dma.o fb.o -obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o +obj-y += clock.o reset.o pm_bus.o timer.o ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),) obj-y += mcbsp.o diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8e0e58495023..4f7e2fe58d63 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -32,7 +32,6 @@ #include "hardware.h" #include "usb.h" #include "common.h" -#include "clock.h" #include "mmc.h" #define ADS7846_PENDOWN_GPIO 15 diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 24db9b723a6f..bc51d5e24a9e 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include @@ -23,9 +25,318 @@ #include "hardware.h" #include "soc.h" #include "iomap.h" -#include "clock.h" -#include "opp.h" #include "sram.h" +#include "usb.h" + +struct module; +struct clk; + +struct omap_clk { + u16 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +/* Platform flags for the clkdev-OMAP integration code */ +#define CK_310 (1 << 0) +#define CK_7XX (1 << 1) /* 7xx, 850 */ +#define CK_1510 (1 << 2) +#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ +#define CK_1710 (1 << 4) /* 1710 extra for rate selection */ + + +/* Temporary, needed during the common clock framework conversion */ +#define __clk_get_name(clk) (clk->name) +#define __clk_get_parent(clk) (clk->parent) +#define __clk_get_rate(clk) (clk->rate) + +/** + * struct clkops - some clock function pointers + * @enable: fn ptr that enables the current clock in hardware + * @disable: fn ptr that enables the current clock in hardware + * @find_idlest: function returning the IDLEST register for the clock's IP blk + * @find_companion: function returning the "companion" clk reg for the clock + * @allow_idle: fn ptr that enables autoidle for the current clock in hardware + * @deny_idle: fn ptr that disables autoidle for the current clock in hardware + * + * A "companion" clk is an accompanying clock to the one being queried + * that must be enabled for the IP module connected to the clock to + * become accessible by the hardware. Neither @find_idlest nor + * @find_companion should be needed; that information is IP + * block-specific; the hwmod code has been created to handle this, but + * until hwmod data is ready and drivers have been converted to use PM + * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and + * @find_companion must, unfortunately, remain. + */ +struct clkops { + int (*enable)(struct clk *); + void (*disable)(struct clk *); + void (*find_idlest)(struct clk *, void __iomem **, + u8 *, u8 *); + void (*find_companion)(struct clk *, void __iomem **, + u8 *); + void (*allow_idle)(struct clk *); + void (*deny_idle)(struct clk *); +}; + +/* + * struct clk.flags possibilities + * + * XXX document the rest of the clock flags here + * + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL + * bits share the same register. This flag allows the + * omap4_dpllmx*() code to determine which GATE_CTRL bit field + * should be used. This is a temporary solution - a better approach + * would be to associate clock type-specific data with the clock, + * similar to the struct dpll_data approach. + */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ +#define CLOCK_CLKOUTX2 (1 << 5) + +/** + * struct clk - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @ops: struct clkops * for this clock + * @name: the name of the clock in the hardware (used in hwmod data and debug) + * @parent: pointer to this clock's parent struct clk + * @children: list_head connecting to the child clks' @sibling list_heads + * @sibling: list_head connecting this clk to its parent clk's @children + * @rate: current clock rate + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @recalc: fn ptr that returns the clock's current rate + * @set_rate: fn ptr that can change the clock's current rate + * @round_rate: fn ptr that can round the clock's current rate + * @init: fn ptr to do clock-specific initialization + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @usecount: number of users that have requested this clock to be enabled + * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div + * @flags: see "struct clk.flags possibilities" above + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) + * @src_offset: bitshift for source selection bitfield (OMAP1 only) + * + * XXX @rate_offset, @src_offset should probably be removed and OMAP1 + * clock code converted to use clksel. + * + * XXX @usecount is poorly named. It should be "enable_count" or + * something similar. "users" in the description refers to kernel + * code (core code or drivers) that have called clk_enable() and not + * yet called clk_disable(); the usecount of parent clocks is also + * incremented by the clock code when clk_enable() is called on child + * clocks and decremented by the clock code when clk_disable() is + * called on child clocks. + * + * XXX @clkdm, @usecount, @children, @sibling should be marked for + * internal use only. + * + * @children and @sibling are used to optimize parent-to-child clock + * tree traversals. (child-to-parent traversals use @parent.) + * + * XXX The notion of the clock's current rate probably needs to be + * separated from the clock's target rate. + */ +struct clk { + struct list_head node; + const struct clkops *ops; + const char *name; + struct clk *parent; + struct list_head children; + struct list_head sibling; /* node for children */ + unsigned long rate; + void __iomem *enable_reg; + unsigned long (*recalc)(struct clk *); + int (*set_rate)(struct clk *, unsigned long); + long (*round_rate)(struct clk *, unsigned long); + void (*init)(struct clk *); + u8 enable_bit; + s8 usecount; + u8 fixed_div; + u8 flags; + u8 rate_offset; + u8 src_offset; +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) + struct dentry *dent; /* For visible tree hierarchy */ +#endif +}; + +struct clk_functions { + int (*clk_enable)(struct clk *clk); + void (*clk_disable)(struct clk *clk); + long (*clk_round_rate)(struct clk *clk, unsigned long rate); + int (*clk_set_rate)(struct clk *clk, unsigned long rate); + int (*clk_set_parent)(struct clk *clk, struct clk *parent); + void (*clk_allow_idle)(struct clk *clk); + void (*clk_deny_idle)(struct clk *clk); + void (*clk_disable_unused)(struct clk *clk); +}; + +extern int clk_init(struct clk_functions *custom_clocks); +extern void clk_preinit(struct clk *clk); +extern int clk_register(struct clk *clk); +extern void clk_reparent(struct clk *child, struct clk *parent); +extern void clk_unregister(struct clk *clk); +extern void propagate_rate(struct clk *clk); +extern void recalculate_root_clocks(void); +extern unsigned long followparent_recalc(struct clk *clk); +extern void clk_enable_init_clocks(void); +unsigned long omap_fixed_divisor_recalc(struct clk *clk); +extern struct clk *omap_clk_get_by_name(const char *name); +extern int omap_clk_enable_autoidle_all(void); +extern int omap_clk_disable_autoidle_all(void); + +extern const struct clkops clkops_null; + +extern struct clk dummy_ck; + +extern int omap1_clk_enable(struct clk *clk); +extern void omap1_clk_disable(struct clk *clk); +extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); +extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); +extern unsigned long omap1_ckctl_recalc(struct clk *clk); +extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); +extern unsigned long omap1_sossi_recalc(struct clk *clk); +extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); +extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); +extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); +extern unsigned long omap1_uart_recalc(struct clk *clk); +extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); +extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); +extern void omap1_init_ext_clk(struct clk *clk); +extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); +extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); +extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); +extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); +extern unsigned long omap1_watchdog_recalc(struct clk *clk); + +#ifdef CONFIG_OMAP_RESET_CLOCKS +extern void omap1_clk_disable_unused(struct clk *clk); +#else +#define omap1_clk_disable_unused NULL +#endif + +struct uart_clk { + struct clk clk; + unsigned long sysc_addr; +}; + +/* Provide a method for preventing idling some ARM IDLECT clocks */ +struct arm_idlect1_clk { + struct clk clk; + unsigned long no_idle_count; + __u8 idlect_shift; +}; + +/* ARM_CKCTL bit shifts */ +#define CKCTL_PERDIV_OFFSET 0 +#define CKCTL_LCDDIV_OFFSET 2 +#define CKCTL_ARMDIV_OFFSET 4 +#define CKCTL_DSPDIV_OFFSET 6 +#define CKCTL_TCDIV_OFFSET 8 +#define CKCTL_DSPMMUDIV_OFFSET 10 +/*#define ARM_TIMXO 12*/ +#define EN_DSPCK 13 +/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ +/* DSP_CKCTL bit shifts */ +#define CKCTL_DSPPERDIV_OFFSET 0 + +/* ARM_IDLECT2 bit shifts */ +#define EN_WDTCK 0 +#define EN_XORPCK 1 +#define EN_PERCK 2 +#define EN_LCDCK 3 +#define EN_LBCK 4 /* Not on 1610/1710 */ +/*#define EN_HSABCK 5*/ +#define EN_APICK 6 +#define EN_TIMCK 7 +#define DMACK_REQ 8 +#define EN_GPIOCK 9 /* Not on 1610/1710 */ +/*#define EN_LBFREECK 10*/ +#define EN_CKOUT_ARM 11 + +/* ARM_IDLECT3 bit shifts */ +#define EN_OCPI_CK 0 +#define EN_TC1_CK 2 +#define EN_TC2_CK 4 + +/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ +#define EN_DSPTIMCK 5 + +/* Various register defines for clock controls scattered around OMAP chip */ +#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ +#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ +#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ +#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ +#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ +#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 +#define COM_CLK_DIV_CTRL_SEL 0xfffe0878 +#define SOFT_REQ_REG 0xfffe0834 +#define SOFT_REQ_REG2 0xfffe0880 + +extern __u32 arm_idlect1_mask; +extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; + +extern const struct clkops clkops_dspck; +extern const struct clkops clkops_dummy; +extern const struct clkops clkops_uart_16xx; +extern const struct clkops clkops_generic; + +/* used for passing SoC type to omap1_{select,round_to}_table_rate() */ +extern u32 cpu_mask; + + +/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ +#define IDL_CLKOUT_ARM_SHIFT 12 +#define IDLTIM_ARM_SHIFT 9 +#define IDLAPI_ARM_SHIFT 8 +#define IDLIF_ARM_SHIFT 6 +#define IDLLB_ARM_SHIFT 4 /* undocumented? */ +#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ +#define IDLPER_ARM_SHIFT 2 +#define IDLXORP_ARM_SHIFT 1 +#define IDLWDT_ARM_SHIFT 0 + +/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ +#define CONF_MOD_UART3_CLK_MODE_R 31 +#define CONF_MOD_UART2_CLK_MODE_R 30 +#define CONF_MOD_UART1_CLK_MODE_R 29 +#define CONF_MOD_MMC_SD_CLK_REQ_R 23 +#define CONF_MOD_MCBSP3_AUXON 20 + +/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ +#define CONF_MOD_SOSSI_CLK_EN_R 16 + +/* Some OTG_SYSCON_2-specific bit fields */ +#define OTG_SYSCON_2_UHOST_EN_SHIFT 8 + +/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ +#define SOFT_MMC2_DPLL_REQ_SHIFT 13 +#define SOFT_MMC_DPLL_REQ_SHIFT 12 +#define SOFT_UART3_DPLL_REQ_SHIFT 11 +#define SOFT_UART2_DPLL_REQ_SHIFT 10 +#define SOFT_UART1_DPLL_REQ_SHIFT 9 +#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 +#define SOFT_CAM_DPLL_REQ_SHIFT 7 +#define SOFT_COM_MCKO_REQ_SHIFT 6 +#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ +#define USB_REQ_EN_SHIFT 4 +#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ +#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ +#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ +#define SOFT_DPLL_REQ_SHIFT 0 + __u32 arm_idlect1_mask; struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; @@ -187,6 +498,54 @@ unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) return clk->parent->rate / dsor; } +/*------------------------------------------------------------------------- + * Omap1 MPU rate table + *-------------------------------------------------------------------------*/ +struct mpu_rate { + unsigned long rate; + unsigned long xtal; + unsigned long pll_rate; + __u16 ckctl_val; + __u16 dpllctl_val; + u32 flags; +}; + +struct mpu_rate omap1_rate_table[] = { + /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL + * NOTE: Comment order here is different from bits in CKCTL value: + * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv + */ + { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */ + CK_1710 }, + { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */ + CK_7XX }, + { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */ + CK_16XX }, + { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */ + CK_16XX }, + { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */ + CK_16XX }, + { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */ + CK_16XX }, + { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */ + CK_16XX }, + { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */ + CK_7XX }, + { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */ + CK_16XX|CK_7XX }, + { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */ + CK_1510 }, + { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 96000000, 12000000, 96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 60000000, 12000000, 60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 30000000, 12000000, 60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */ + CK_16XX|CK_1510|CK_310|CK_7XX }, + { 0, 0, 0, 0, 0 }, +}; + /* MPU virtual clock functions */ int omap1_select_table_rate(struct clk *clk, unsigned long rate) { @@ -1029,3 +1388,855 @@ static int __init clk_debugfs_init(void) late_initcall(clk_debugfs_init); #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ + +/* + * Omap1 clocks + */ + +static struct clk ck_ref = { + .name = "ck_ref", + .ops = &clkops_null, + .rate = 12000000, +}; + +static struct clk ck_dpll1 = { + .name = "ck_dpll1", + .ops = &clkops_null, + .parent = &ck_ref, +}; + +/* + * FIXME: This clock seems to be necessary but no-one has asked for its + * activation. [ FIX: SoSSI, SSR ] + */ +static struct arm_idlect1_clk ck_dpll1out = { + .clk = { + .name = "ck_dpll1out", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | + ENABLE_ON_INIT, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_CKOUT_ARM, + .recalc = &followparent_recalc, + }, + .idlect_shift = IDL_CLKOUT_ARM_SHIFT, +}; + +static struct clk sossi_ck = { + .name = "ck_sossi", + .ops = &clkops_generic, + .parent = &ck_dpll1out.clk, + .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), + .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, + .recalc = &omap1_sossi_recalc, + .set_rate = &omap1_set_sossi_rate, +}; + +static struct clk arm_ck = { + .name = "arm_ck", + .ops = &clkops_null, + .parent = &ck_dpll1, + .rate_offset = CKCTL_ARMDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct arm_idlect1_clk armper_ck = { + .clk = { + .name = "armper_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_PERCK, + .rate_offset = CKCTL_PERDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, + }, + .idlect_shift = IDLPER_ARM_SHIFT, +}; + +/* + * FIXME: This clock seems to be necessary but no-one has asked for its + * activation. [ GPIO code for 1510 ] + */ +static struct clk arm_gpio_ck = { + .name = "ick", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = ENABLE_ON_INIT, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_GPIOCK, + .recalc = &followparent_recalc, +}; + +static struct arm_idlect1_clk armxor_ck = { + .clk = { + .name = "armxor_ck", + .ops = &clkops_generic, + .parent = &ck_ref, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_XORPCK, + .recalc = &followparent_recalc, + }, + .idlect_shift = IDLXORP_ARM_SHIFT, +}; + +static struct arm_idlect1_clk armtim_ck = { + .clk = { + .name = "armtim_ck", + .ops = &clkops_generic, + .parent = &ck_ref, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_TIMCK, + .recalc = &followparent_recalc, + }, + .idlect_shift = IDLTIM_ARM_SHIFT, +}; + +static struct arm_idlect1_clk armwdt_ck = { + .clk = { + .name = "armwdt_ck", + .ops = &clkops_generic, + .parent = &ck_ref, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_WDTCK, + .fixed_div = 14, + .recalc = &omap_fixed_divisor_recalc, + }, + .idlect_shift = IDLWDT_ARM_SHIFT, +}; + +static struct clk arminth_ck16xx = { + .name = "arminth_ck", + .ops = &clkops_null, + .parent = &arm_ck, + .recalc = &followparent_recalc, + /* Note: On 16xx the frequency can be divided by 2 by programming + * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 + * + * 1510 version is in TC clocks. + */ +}; + +static struct clk dsp_ck = { + .name = "dsp_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), + .enable_bit = EN_DSPCK, + .rate_offset = CKCTL_DSPDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct clk dspmmu_ck = { + .name = "dspmmu_ck", + .ops = &clkops_null, + .parent = &ck_dpll1, + .rate_offset = CKCTL_DSPMMUDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct clk dspper_ck = { + .name = "dspper_ck", + .ops = &clkops_dspck, + .parent = &ck_dpll1, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_PERCK, + .rate_offset = CKCTL_PERDIV_OFFSET, + .recalc = &omap1_ckctl_recalc_dsp_domain, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = &omap1_clk_set_rate_dsp_domain, +}; + +static struct clk dspxor_ck = { + .name = "dspxor_ck", + .ops = &clkops_dspck, + .parent = &ck_ref, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_XORPCK, + .recalc = &followparent_recalc, +}; + +static struct clk dsptim_ck = { + .name = "dsptim_ck", + .ops = &clkops_dspck, + .parent = &ck_ref, + .enable_reg = DSP_IDLECT2, + .enable_bit = EN_DSPTIMCK, + .recalc = &followparent_recalc, +}; + +static struct arm_idlect1_clk tc_ck = { + .clk = { + .name = "tc_ck", + .ops = &clkops_null, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL, + .rate_offset = CKCTL_TCDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, + }, + .idlect_shift = IDLIF_ARM_SHIFT, +}; + +static struct clk arminth_ck1510 = { + .name = "arminth_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, + /* Note: On 1510 the frequency follows TC_CK + * + * 16xx version is in MPU clocks. + */ +}; + +static struct clk tipb_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "tipb_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk l3_ocpi_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "l3_ocpi_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), + .enable_bit = EN_OCPI_CK, + .recalc = &followparent_recalc, +}; + +static struct clk tc1_ck = { + .name = "tc1_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), + .enable_bit = EN_TC1_CK, + .recalc = &followparent_recalc, +}; + +/* + * FIXME: This clock seems to be necessary but no-one has asked for its + * activation. [ pm.c (SRAM), CCP, Camera ] + */ +static struct clk tc2_ck = { + .name = "tc2_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .flags = ENABLE_ON_INIT, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), + .enable_bit = EN_TC2_CK, + .recalc = &followparent_recalc, +}; + +static struct clk dma_ck = { + /* No-idle controlled by "tc_ck" */ + .name = "dma_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk dma_lcdfree_ck = { + .name = "dma_lcdfree_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct arm_idlect1_clk api_ck = { + .clk = { + .name = "api_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_APICK, + .recalc = &followparent_recalc, + }, + .idlect_shift = IDLAPI_ARM_SHIFT, +}; + +static struct arm_idlect1_clk lb_ck = { + .clk = { + .name = "lb_ck", + .ops = &clkops_generic, + .parent = &tc_ck.clk, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_LBCK, + .recalc = &followparent_recalc, + }, + .idlect_shift = IDLLB_ARM_SHIFT, +}; + +static struct clk rhea1_ck = { + .name = "rhea1_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk rhea2_ck = { + .name = "rhea2_ck", + .ops = &clkops_null, + .parent = &tc_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk lcd_ck_16xx = { + .name = "lcd_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_LCDCK, + .rate_offset = CKCTL_LCDDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, +}; + +static struct arm_idlect1_clk lcd_ck_1510 = { + .clk = { + .name = "lcd_ck", + .ops = &clkops_generic, + .parent = &ck_dpll1, + .flags = CLOCK_IDLE_CONTROL, + .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), + .enable_bit = EN_LCDCK, + .rate_offset = CKCTL_LCDDIV_OFFSET, + .recalc = &omap1_ckctl_recalc, + .round_rate = omap1_clk_round_rate_ckctl_arm, + .set_rate = omap1_clk_set_rate_ckctl_arm, + }, + .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, +}; + +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX does this need SYSC register handling? + */ +static struct clk uart1_1510 = { + .name = "uart1_ck", + .ops = &clkops_null, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = CONF_MOD_UART1_CLK_MODE_R, + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, +}; + +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX SYSC register handling does not belong in the clock framework + */ +static struct uart_clk uart1_16xx = { + .clk = { + .name = "uart1_ck", + .ops = &clkops_uart_16xx, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = CONF_MOD_UART1_CLK_MODE_R, + }, + .sysc_addr = 0xfffb0054, +}; + +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX does this need SYSC register handling? + */ +static struct clk uart2_ck = { + .name = "uart2_ck", + .ops = &clkops_null, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = CONF_MOD_UART2_CLK_MODE_R, + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, +}; + +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX does this need SYSC register handling? + */ +static struct clk uart3_1510 = { + .name = "uart3_ck", + .ops = &clkops_null, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 12000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = CONF_MOD_UART3_CLK_MODE_R, + .set_rate = &omap1_set_uart_rate, + .recalc = &omap1_uart_recalc, +}; + +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX SYSC register handling does not belong in the clock framework + */ +static struct uart_clk uart3_16xx = { + .clk = { + .name = "uart3_ck", + .ops = &clkops_uart_16xx, + /* Direct from ULPD, no real parent */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = CONF_MOD_UART3_CLK_MODE_R, + }, + .sysc_addr = 0xfffb9854, +}; + +static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ + .name = "usb_clko", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 6000000, + .flags = ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), + .enable_bit = USB_MCLK_EN_BIT, +}; + +static struct clk usb_hhc_ck1510 = { + .name = "usb_hhc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ + .flags = ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = USB_HOST_HHC_UHOST_EN, +}; + +static struct clk usb_hhc_ck16xx = { + .name = "usb_hhc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, + /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ + .flags = ENABLE_REG_32BIT, + .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ + .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT +}; + +static struct clk usb_dc_ck = { + .name = "usb_dc_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 48000000, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, +}; + +static struct clk uart1_7xx = { + .name = "uart1_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 12000000, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 9, +}; + +static struct clk uart2_7xx = { + .name = "uart2_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 12000000, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 11, +}; + +static struct clk mclk_1510 = { + .name = "mclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .rate = 12000000, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, +}; + +static struct clk mclk_16xx = { + .name = "mclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), + .enable_bit = COM_ULPD_PLL_CLK_REQ, + .set_rate = &omap1_set_ext_clk_rate, + .round_rate = &omap1_round_ext_clk_rate, + .init = &omap1_init_ext_clk, +}; + +static struct clk bclk_1510 = { + .name = "bclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .rate = 12000000, +}; + +static struct clk bclk_16xx = { + .name = "bclk", + .ops = &clkops_generic, + /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), + .enable_bit = SWD_ULPD_PLL_CLK_REQ, + .set_rate = &omap1_set_ext_clk_rate, + .round_rate = &omap1_round_ext_clk_rate, + .init = &omap1_init_ext_clk, +}; + +static struct clk mmc1_ck = { + .name = "mmc1_ck", + .ops = &clkops_generic, + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, +}; + +/* + * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as + * CONF_MOD_MCBSP3_AUXON ?? + */ +static struct clk mmc2_ck = { + .name = "mmc2_ck", + .ops = &clkops_generic, + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), + .enable_bit = 20, +}; + +static struct clk mmc3_ck = { + .name = "mmc3_ck", + .ops = &clkops_generic, + /* Functional clock is direct from ULPD, interface clock is ARMPER */ + .parent = &armper_ck.clk, + .rate = 48000000, + .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, +}; + +static struct clk virtual_ck_mpu = { + .name = "mpu", + .ops = &clkops_null, + .parent = &arm_ck, /* Is smarter alias for */ + .recalc = &followparent_recalc, + .set_rate = &omap1_select_table_rate, + .round_rate = &omap1_round_to_table_rate, +}; + +/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK +remains active during MPU idle whenever this is enabled */ +static struct clk i2c_fck = { + .name = "i2c_fck", + .ops = &clkops_null, + .flags = CLOCK_NO_IDLE_PARENT, + .parent = &armxor_ck.clk, + .recalc = &followparent_recalc, +}; + +static struct clk i2c_ick = { + .name = "i2c_ick", + .ops = &clkops_null, + .flags = CLOCK_NO_IDLE_PARENT, + .parent = &armper_ck.clk, + .recalc = &followparent_recalc, +}; + +/* + * clkdev integration + */ + +static struct omap_clk omap_clks[] = { + /* non-ULPD clocks */ + CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), + /* CK_GEN1 clocks */ + CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), + CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), + CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), + CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), + CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), + CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), + /* CK_GEN2 clocks */ + CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), + /* CK_GEN3 clocks */ + CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), + CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), + CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), + CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), + CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), + CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), + CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), + CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), + CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), + CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), + /* ULPD clocks */ + CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), + CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), + CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), + CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), + CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), + CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), + CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), + CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), + CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), + CLK(NULL, "mclk", &mclk_16xx, CK_16XX), + CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), + CLK(NULL, "bclk", &bclk_16xx, CK_16XX), + CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), + CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), + CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), + CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), + /* Virtual clocks */ + CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), + CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), + CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), + CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), + CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), + CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), + CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), + CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), + CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), + CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), +}; + +/* + * init + */ + +static void __init omap1_show_rates(void) +{ + pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); +} + +u32 cpu_mask; + +int __init omap1_clk_init(void) +{ + struct omap_clk *c; + int crystal_type = 0; /* Default 12 MHz */ + u32 reg; + +#ifdef CONFIG_DEBUG_LL + /* + * Resets some clocks that may be left on from bootloader, + * but leaves serial clocks on. + */ + omap_writel(0x3 << 29, MOD_CONF_CTRL_0); +#endif + + /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ + reg = omap_readw(SOFT_REQ_REG) & (1 << 4); + omap_writew(reg, SOFT_REQ_REG); + if (!cpu_is_omap15xx()) + omap_writew(0, SOFT_REQ_REG2); + + /* By default all idlect1 clocks are allowed to idle */ + arm_idlect1_mask = ~0; + + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + clk_preinit(c->lk.clk); + + cpu_mask = 0; + if (cpu_is_omap1710()) + cpu_mask |= CK_1710; + if (cpu_is_omap16xx()) + cpu_mask |= CK_16XX; + if (cpu_is_omap1510()) + cpu_mask |= CK_1510; + if (cpu_is_omap7xx()) + cpu_mask |= CK_7XX; + if (cpu_is_omap310()) + cpu_mask |= CK_310; + + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + if (c->cpu & cpu_mask) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + } + + /* Pointers to these clocks are needed by code in clock.c */ + api_ck_p = clk_get(NULL, "api_ck"); + ck_dpll1_p = clk_get(NULL, "ck_dpll1"); + ck_ref_p = clk_get(NULL, "ck_ref"); + + if (cpu_is_omap7xx()) + ck_ref.rate = 13000000; + if (cpu_is_omap16xx() && crystal_type == 2) + ck_ref.rate = 19200000; + + pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", + omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), + omap_readw(ARM_CKCTL)); + + /* We want to be in syncronous scalable mode */ + omap_writew(0x1000, ARM_SYSST); + + + /* + * Initially use the values set by bootloader. Determine PLL rate and + * recalculate dependent clocks as if kernel had changed PLL or + * divisors. See also omap1_clk_late_init() that can reprogram dpll1 + * after the SRAM is initialized. + */ + { + unsigned pll_ctl_val = omap_readw(DPLL_CTL); + + ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ + if (pll_ctl_val & 0x10) { + /* PLL enabled, apply multiplier and divisor */ + if (pll_ctl_val & 0xf80) + ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; + ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; + } else { + /* PLL disabled, apply bypass divisor */ + switch (pll_ctl_val & 0xc) { + case 0: + break; + case 0x4: + ck_dpll1.rate /= 2; + break; + default: + ck_dpll1.rate /= 4; + break; + } + } + } + propagate_rate(&ck_dpll1); + /* Cache rates for clocks connected to ck_ref (not dpll1) */ + propagate_rate(&ck_ref); + omap1_show_rates(); + if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { + /* Select slicer output as OMAP input clock */ + omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, + OMAP7XX_PCC_UPLD_CTRL); + } + + /* Amstrad Delta wants BCLK high when inactive */ + if (machine_is_ams_delta()) + omap_writel(omap_readl(ULPD_CLOCK_CTRL) | + (1 << SDW_MCLK_INV_BIT), + ULPD_CLOCK_CTRL); + + /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ + /* (on 730, bit 13 must not be cleared) */ + if (cpu_is_omap7xx()) + omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); + else + omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); + + /* Put DSP/MPUI into reset until needed */ + omap_writew(0, ARM_RSTCT1); + omap_writew(1, ARM_RSTCT2); + omap_writew(0x400, ARM_IDLECT1); + + /* + * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) + * of the ARM_IDLECT2 register must be set to zero. The power-on + * default value of this bit is one. + */ + omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + clk_enable(&armper_ck.clk); + clk_enable(&armxor_ck.clk); + clk_enable(&armtim_ck.clk); /* This should be done by timer code */ + + if (cpu_is_omap15xx()) + clk_enable(&arm_gpio_ck); + + return 0; +} + +#define OMAP1_DPLL1_SANE_VALUE 60000000 + +void __init omap1_clk_late_init(void) +{ + unsigned long rate = ck_dpll1.rate; + + /* Find the highest supported frequency and enable it */ + if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { + pr_err("System frequencies not set, using default. Check your config.\n"); + /* + * Reprogramming the DPLL is tricky, it must be done from SRAM. + */ + omap_sram_reprogram_clock(0x2290, 0x0005); + ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; + } + propagate_rate(&ck_dpll1); + omap1_show_rates(); + loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); +} diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h deleted file mode 100644 index f3b8811f5ac0..000000000000 --- a/arch/arm/mach-omap1/clock.h +++ /dev/null @@ -1,288 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/mach-omap1/clock.h - * - * Copyright (C) 2004 - 2005, 2009 Nokia corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - */ - -#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H -#define __ARCH_ARM_MACH_OMAP1_CLOCK_H - -#include -#include - -#include - -struct module; -struct clk; - -struct omap_clk { - u16 cpu; - struct clk_lookup lk; -}; - -#define CLK(dev, con, ck, cp) \ - { \ - .cpu = cp, \ - .lk = { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - }, \ - } - -/* Platform flags for the clkdev-OMAP integration code */ -#define CK_310 (1 << 0) -#define CK_7XX (1 << 1) /* 7xx, 850 */ -#define CK_1510 (1 << 2) -#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ -#define CK_1710 (1 << 4) /* 1710 extra for rate selection */ - - -/* Temporary, needed during the common clock framework conversion */ -#define __clk_get_name(clk) (clk->name) -#define __clk_get_parent(clk) (clk->parent) -#define __clk_get_rate(clk) (clk->rate) - -/** - * struct clkops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock - * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); -}; - -/* - * struct clk.flags possibilities - * - * XXX document the rest of the clock flags here - * - * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL - * bits share the same register. This flag allows the - * omap4_dpllmx*() code to determine which GATE_CTRL bit field - * should be used. This is a temporary solution - a better approach - * would be to associate clock type-specific data with the clock, - * similar to the struct dpll_data approach. - */ -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 1) -#define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ -#define CLOCK_CLKOUTX2 (1 << 5) - -/** - * struct clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @ops: struct clkops * for this clock - * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children - * @rate: current clock rate - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @recalc: fn ptr that returns the clock's current rate - * @set_rate: fn ptr that can change the clock's current rate - * @round_rate: fn ptr that can round the clock's current rate - * @init: fn ptr to do clock-specific initialization - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @usecount: number of users that have requested this clock to be enabled - * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div - * @flags: see "struct clk.flags possibilities" above - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - * XXX @usecount is poorly named. It should be "enable_count" or - * something similar. "users" in the description refers to kernel - * code (core code or drivers) that have called clk_enable() and not - * yet called clk_disable(); the usecount of parent clocks is also - * incremented by the clock code when clk_enable() is called on child - * clocks and decremented by the clock code when clk_disable() is - * called on child clocks. - * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) - * - * XXX The notion of the clock's current rate probably needs to be - * separated from the clock's target rate. - */ -struct clk { - struct list_head node; - const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); - u8 enable_bit; - s8 usecount; - u8 fixed_div; - u8 flags; - u8 rate_offset; - u8 src_offset; -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -}; - -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -unsigned long omap_fixed_divisor_recalc(struct clk *clk); -extern struct clk *omap_clk_get_by_name(const char *name); -extern int omap_clk_enable_autoidle_all(void); -extern int omap_clk_disable_autoidle_all(void); - -extern const struct clkops clkops_null; - -extern struct clk dummy_ck; - -int omap1_clk_init(void); -void omap1_clk_late_init(void); -extern int omap1_clk_enable(struct clk *clk); -extern void omap1_clk_disable(struct clk *clk); -extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); -extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_ckctl_recalc(struct clk *clk); -extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_sossi_recalc(struct clk *clk); -extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); -extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); -extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); -extern unsigned long omap1_uart_recalc(struct clk *clk); -extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); -extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); -extern void omap1_init_ext_clk(struct clk *clk); -extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); -extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); -extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); -extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); -extern unsigned long omap1_watchdog_recalc(struct clk *clk); - -#ifdef CONFIG_OMAP_RESET_CLOCKS -extern void omap1_clk_disable_unused(struct clk *clk); -#else -#define omap1_clk_disable_unused NULL -#endif - -struct uart_clk { - struct clk clk; - unsigned long sysc_addr; -}; - -/* Provide a method for preventing idling some ARM IDLECT clocks */ -struct arm_idlect1_clk { - struct clk clk; - unsigned long no_idle_count; - __u8 idlect_shift; -}; - -/* ARM_CKCTL bit shifts */ -#define CKCTL_PERDIV_OFFSET 0 -#define CKCTL_LCDDIV_OFFSET 2 -#define CKCTL_ARMDIV_OFFSET 4 -#define CKCTL_DSPDIV_OFFSET 6 -#define CKCTL_TCDIV_OFFSET 8 -#define CKCTL_DSPMMUDIV_OFFSET 10 -/*#define ARM_TIMXO 12*/ -#define EN_DSPCK 13 -/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ -/* DSP_CKCTL bit shifts */ -#define CKCTL_DSPPERDIV_OFFSET 0 - -/* ARM_IDLECT2 bit shifts */ -#define EN_WDTCK 0 -#define EN_XORPCK 1 -#define EN_PERCK 2 -#define EN_LCDCK 3 -#define EN_LBCK 4 /* Not on 1610/1710 */ -/*#define EN_HSABCK 5*/ -#define EN_APICK 6 -#define EN_TIMCK 7 -#define DMACK_REQ 8 -#define EN_GPIOCK 9 /* Not on 1610/1710 */ -/*#define EN_LBFREECK 10*/ -#define EN_CKOUT_ARM 11 - -/* ARM_IDLECT3 bit shifts */ -#define EN_OCPI_CK 0 -#define EN_TC1_CK 2 -#define EN_TC2_CK 4 - -/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ -#define EN_DSPTIMCK 5 - -/* Various register defines for clock controls scattered around OMAP chip */ -#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ -#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ -#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ -#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ -#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ -#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 -#define COM_CLK_DIV_CTRL_SEL 0xfffe0878 -#define SOFT_REQ_REG 0xfffe0834 -#define SOFT_REQ_REG2 0xfffe0880 - -extern __u32 arm_idlect1_mask; -extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; - -extern const struct clkops clkops_dspck; -extern const struct clkops clkops_dummy; -extern const struct clkops clkops_uart_16xx; -extern const struct clkops clkops_generic; - -/* used for passing SoC type to omap1_{select,round_to}_table_rate() */ -extern u32 cpu_mask; - -#endif diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c deleted file mode 100644 index 36f04da4b939..000000000000 --- a/arch/arm/mach-omap1/clock_data.c +++ /dev/null @@ -1,920 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/clock_data.c - * - * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - * - * To do: - * - Clocks that are only available on some chips should be marked with the - * chips that they are present on. - */ - -#include -#include -#include -#include -#include -#include - -#include /* for machine_is_* */ - -#include "soc.h" -#include "hardware.h" -#include "usb.h" /* for OTG_BASE */ -#include "iomap.h" -#include "clock.h" -#include "sram.h" - -/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ -#define IDL_CLKOUT_ARM_SHIFT 12 -#define IDLTIM_ARM_SHIFT 9 -#define IDLAPI_ARM_SHIFT 8 -#define IDLIF_ARM_SHIFT 6 -#define IDLLB_ARM_SHIFT 4 /* undocumented? */ -#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ -#define IDLPER_ARM_SHIFT 2 -#define IDLXORP_ARM_SHIFT 1 -#define IDLWDT_ARM_SHIFT 0 - -/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ -#define CONF_MOD_UART3_CLK_MODE_R 31 -#define CONF_MOD_UART2_CLK_MODE_R 30 -#define CONF_MOD_UART1_CLK_MODE_R 29 -#define CONF_MOD_MMC_SD_CLK_REQ_R 23 -#define CONF_MOD_MCBSP3_AUXON 20 - -/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ -#define CONF_MOD_SOSSI_CLK_EN_R 16 - -/* Some OTG_SYSCON_2-specific bit fields */ -#define OTG_SYSCON_2_UHOST_EN_SHIFT 8 - -/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ -#define SOFT_MMC2_DPLL_REQ_SHIFT 13 -#define SOFT_MMC_DPLL_REQ_SHIFT 12 -#define SOFT_UART3_DPLL_REQ_SHIFT 11 -#define SOFT_UART2_DPLL_REQ_SHIFT 10 -#define SOFT_UART1_DPLL_REQ_SHIFT 9 -#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 -#define SOFT_CAM_DPLL_REQ_SHIFT 7 -#define SOFT_COM_MCKO_REQ_SHIFT 6 -#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ -#define USB_REQ_EN_SHIFT 4 -#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ -#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ -#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ -#define SOFT_DPLL_REQ_SHIFT 0 - -/* - * Omap1 clocks - */ - -static struct clk ck_ref = { - .name = "ck_ref", - .ops = &clkops_null, - .rate = 12000000, -}; - -static struct clk ck_dpll1 = { - .name = "ck_dpll1", - .ops = &clkops_null, - .parent = &ck_ref, -}; - -/* - * FIXME: This clock seems to be necessary but no-one has asked for its - * activation. [ FIX: SoSSI, SSR ] - */ -static struct arm_idlect1_clk ck_dpll1out = { - .clk = { - .name = "ck_dpll1out", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | - ENABLE_ON_INIT, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_CKOUT_ARM, - .recalc = &followparent_recalc, - }, - .idlect_shift = IDL_CLKOUT_ARM_SHIFT, -}; - -static struct clk sossi_ck = { - .name = "ck_sossi", - .ops = &clkops_generic, - .parent = &ck_dpll1out.clk, - .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), - .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, - .recalc = &omap1_sossi_recalc, - .set_rate = &omap1_set_sossi_rate, -}; - -static struct clk arm_ck = { - .name = "arm_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, - .rate_offset = CKCTL_ARMDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct arm_idlect1_clk armper_ck = { - .clk = { - .name = "armper_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_PERCK, - .rate_offset = CKCTL_PERDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, - }, - .idlect_shift = IDLPER_ARM_SHIFT, -}; - -/* - * FIXME: This clock seems to be necessary but no-one has asked for its - * activation. [ GPIO code for 1510 ] - */ -static struct clk arm_gpio_ck = { - .name = "ick", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = ENABLE_ON_INIT, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_GPIOCK, - .recalc = &followparent_recalc, -}; - -static struct arm_idlect1_clk armxor_ck = { - .clk = { - .name = "armxor_ck", - .ops = &clkops_generic, - .parent = &ck_ref, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, - }, - .idlect_shift = IDLXORP_ARM_SHIFT, -}; - -static struct arm_idlect1_clk armtim_ck = { - .clk = { - .name = "armtim_ck", - .ops = &clkops_generic, - .parent = &ck_ref, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_TIMCK, - .recalc = &followparent_recalc, - }, - .idlect_shift = IDLTIM_ARM_SHIFT, -}; - -static struct arm_idlect1_clk armwdt_ck = { - .clk = { - .name = "armwdt_ck", - .ops = &clkops_generic, - .parent = &ck_ref, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_WDTCK, - .fixed_div = 14, - .recalc = &omap_fixed_divisor_recalc, - }, - .idlect_shift = IDLWDT_ARM_SHIFT, -}; - -static struct clk arminth_ck16xx = { - .name = "arminth_ck", - .ops = &clkops_null, - .parent = &arm_ck, - .recalc = &followparent_recalc, - /* Note: On 16xx the frequency can be divided by 2 by programming - * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 - * - * 1510 version is in TC clocks. - */ -}; - -static struct clk dsp_ck = { - .name = "dsp_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), - .enable_bit = EN_DSPCK, - .rate_offset = CKCTL_DSPDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct clk dspmmu_ck = { - .name = "dspmmu_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, - .rate_offset = CKCTL_DSPMMUDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct clk dspper_ck = { - .name = "dspper_ck", - .ops = &clkops_dspck, - .parent = &ck_dpll1, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_PERCK, - .rate_offset = CKCTL_PERDIV_OFFSET, - .recalc = &omap1_ckctl_recalc_dsp_domain, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = &omap1_clk_set_rate_dsp_domain, -}; - -static struct clk dspxor_ck = { - .name = "dspxor_ck", - .ops = &clkops_dspck, - .parent = &ck_ref, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_XORPCK, - .recalc = &followparent_recalc, -}; - -static struct clk dsptim_ck = { - .name = "dsptim_ck", - .ops = &clkops_dspck, - .parent = &ck_ref, - .enable_reg = DSP_IDLECT2, - .enable_bit = EN_DSPTIMCK, - .recalc = &followparent_recalc, -}; - -static struct arm_idlect1_clk tc_ck = { - .clk = { - .name = "tc_ck", - .ops = &clkops_null, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL, - .rate_offset = CKCTL_TCDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, - }, - .idlect_shift = IDLIF_ARM_SHIFT, -}; - -static struct clk arminth_ck1510 = { - .name = "arminth_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, - /* Note: On 1510 the frequency follows TC_CK - * - * 16xx version is in MPU clocks. - */ -}; - -static struct clk tipb_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "tipb_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk l3_ocpi_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "l3_ocpi_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), - .enable_bit = EN_OCPI_CK, - .recalc = &followparent_recalc, -}; - -static struct clk tc1_ck = { - .name = "tc1_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), - .enable_bit = EN_TC1_CK, - .recalc = &followparent_recalc, -}; - -/* - * FIXME: This clock seems to be necessary but no-one has asked for its - * activation. [ pm.c (SRAM), CCP, Camera ] - */ -static struct clk tc2_ck = { - .name = "tc2_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = ENABLE_ON_INIT, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), - .enable_bit = EN_TC2_CK, - .recalc = &followparent_recalc, -}; - -static struct clk dma_ck = { - /* No-idle controlled by "tc_ck" */ - .name = "dma_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk dma_lcdfree_ck = { - .name = "dma_lcdfree_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct arm_idlect1_clk api_ck = { - .clk = { - .name = "api_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_APICK, - .recalc = &followparent_recalc, - }, - .idlect_shift = IDLAPI_ARM_SHIFT, -}; - -static struct arm_idlect1_clk lb_ck = { - .clk = { - .name = "lb_ck", - .ops = &clkops_generic, - .parent = &tc_ck.clk, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_LBCK, - .recalc = &followparent_recalc, - }, - .idlect_shift = IDLLB_ARM_SHIFT, -}; - -static struct clk rhea1_ck = { - .name = "rhea1_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk rhea2_ck = { - .name = "rhea2_ck", - .ops = &clkops_null, - .parent = &tc_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk lcd_ck_16xx = { - .name = "lcd_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_LCDCK, - .rate_offset = CKCTL_LCDDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, -}; - -static struct arm_idlect1_clk lcd_ck_1510 = { - .clk = { - .name = "lcd_ck", - .ops = &clkops_generic, - .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL, - .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), - .enable_bit = EN_LCDCK, - .rate_offset = CKCTL_LCDDIV_OFFSET, - .recalc = &omap1_ckctl_recalc, - .round_rate = omap1_clk_round_rate_ckctl_arm, - .set_rate = omap1_clk_set_rate_ckctl_arm, - }, - .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, -}; - -/* - * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. - * - * XXX does this need SYSC register handling? - */ -static struct clk uart1_1510 = { - .name = "uart1_ck", - .ops = &clkops_null, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = CONF_MOD_UART1_CLK_MODE_R, - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, -}; - -/* - * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. - * - * XXX SYSC register handling does not belong in the clock framework - */ -static struct uart_clk uart1_16xx = { - .clk = { - .name = "uart1_ck", - .ops = &clkops_uart_16xx, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = CONF_MOD_UART1_CLK_MODE_R, - }, - .sysc_addr = 0xfffb0054, -}; - -/* - * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. - * - * XXX does this need SYSC register handling? - */ -static struct clk uart2_ck = { - .name = "uart2_ck", - .ops = &clkops_null, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = CONF_MOD_UART2_CLK_MODE_R, - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, -}; - -/* - * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. - * - * XXX does this need SYSC register handling? - */ -static struct clk uart3_1510 = { - .name = "uart3_ck", - .ops = &clkops_null, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 12000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = CONF_MOD_UART3_CLK_MODE_R, - .set_rate = &omap1_set_uart_rate, - .recalc = &omap1_uart_recalc, -}; - -/* - * XXX The enable_bit here is misused - it simply switches between 12MHz - * and 48MHz. Reimplement with clksel. - * - * XXX SYSC register handling does not belong in the clock framework - */ -static struct uart_clk uart3_16xx = { - .clk = { - .name = "uart3_ck", - .ops = &clkops_uart_16xx, - /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = CONF_MOD_UART3_CLK_MODE_R, - }, - .sysc_addr = 0xfffb9854, -}; - -static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ - .name = "usb_clko", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 6000000, - .flags = ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), - .enable_bit = USB_MCLK_EN_BIT, -}; - -static struct clk usb_hhc_ck1510 = { - .name = "usb_hhc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ - .flags = ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = USB_HOST_HHC_UHOST_EN, -}; - -static struct clk usb_hhc_ck16xx = { - .name = "usb_hhc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ - .flags = ENABLE_REG_32BIT, - .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ - .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT -}; - -static struct clk usb_dc_ck = { - .name = "usb_dc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, -}; - -static struct clk uart1_7xx = { - .name = "uart1_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 12000000, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 9, -}; - -static struct clk uart2_7xx = { - .name = "uart2_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 12000000, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 11, -}; - -static struct clk mclk_1510 = { - .name = "mclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, -}; - -static struct clk mclk_16xx = { - .name = "mclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), - .enable_bit = COM_ULPD_PLL_CLK_REQ, - .set_rate = &omap1_set_ext_clk_rate, - .round_rate = &omap1_round_ext_clk_rate, - .init = &omap1_init_ext_clk, -}; - -static struct clk bclk_1510 = { - .name = "bclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .rate = 12000000, -}; - -static struct clk bclk_16xx = { - .name = "bclk", - .ops = &clkops_generic, - /* Direct from ULPD, no parent. May be enabled by ext hardware. */ - .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), - .enable_bit = SWD_ULPD_PLL_CLK_REQ, - .set_rate = &omap1_set_ext_clk_rate, - .round_rate = &omap1_round_ext_clk_rate, - .init = &omap1_init_ext_clk, -}; - -static struct clk mmc1_ck = { - .name = "mmc1_ck", - .ops = &clkops_generic, - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, -}; - -/* - * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as - * CONF_MOD_MCBSP3_AUXON ?? - */ -static struct clk mmc2_ck = { - .name = "mmc2_ck", - .ops = &clkops_generic, - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 20, -}; - -static struct clk mmc3_ck = { - .name = "mmc3_ck", - .ops = &clkops_generic, - /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, - .rate = 48000000, - .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, -}; - -static struct clk virtual_ck_mpu = { - .name = "mpu", - .ops = &clkops_null, - .parent = &arm_ck, /* Is smarter alias for */ - .recalc = &followparent_recalc, - .set_rate = &omap1_select_table_rate, - .round_rate = &omap1_round_to_table_rate, -}; - -/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK -remains active during MPU idle whenever this is enabled */ -static struct clk i2c_fck = { - .name = "i2c_fck", - .ops = &clkops_null, - .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armxor_ck.clk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c_ick = { - .name = "i2c_ick", - .ops = &clkops_null, - .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armper_ck.clk, - .recalc = &followparent_recalc, -}; - -/* - * clkdev integration - */ - -static struct omap_clk omap_clks[] = { - /* non-ULPD clocks */ - CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), - /* CK_GEN1 clocks */ - CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), - CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), - CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), - CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), - CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), - CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), - CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), - /* CK_GEN2 clocks */ - CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), - /* CK_GEN3 clocks */ - CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), - CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), - CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), - CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), - CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), - CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), - CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), - CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), - CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), - CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), - /* ULPD clocks */ - CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), - CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), - CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), - CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), - CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), - CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), - CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), - CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), - CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), - CLK(NULL, "mclk", &mclk_16xx, CK_16XX), - CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), - CLK(NULL, "bclk", &bclk_16xx, CK_16XX), - CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), - CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), - CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), - CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), - /* Virtual clocks */ - CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), - CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), - CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), - CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), - CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), - CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), - CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), - CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), - CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), -}; - -/* - * init - */ - -static void __init omap1_show_rates(void) -{ - pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); -} - -u32 cpu_mask; - -int __init omap1_clk_init(void) -{ - struct omap_clk *c; - int crystal_type = 0; /* Default 12 MHz */ - u32 reg; - -#ifdef CONFIG_DEBUG_LL - /* - * Resets some clocks that may be left on from bootloader, - * but leaves serial clocks on. - */ - omap_writel(0x3 << 29, MOD_CONF_CTRL_0); -#endif - - /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ - reg = omap_readw(SOFT_REQ_REG) & (1 << 4); - omap_writew(reg, SOFT_REQ_REG); - if (!cpu_is_omap15xx()) - omap_writew(0, SOFT_REQ_REG2); - - /* By default all idlect1 clocks are allowed to idle */ - arm_idlect1_mask = ~0; - - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - clk_preinit(c->lk.clk); - - cpu_mask = 0; - if (cpu_is_omap1710()) - cpu_mask |= CK_1710; - if (cpu_is_omap16xx()) - cpu_mask |= CK_16XX; - if (cpu_is_omap1510()) - cpu_mask |= CK_1510; - if (cpu_is_omap7xx()) - cpu_mask |= CK_7XX; - if (cpu_is_omap310()) - cpu_mask |= CK_310; - - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - if (c->cpu & cpu_mask) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - } - - /* Pointers to these clocks are needed by code in clock.c */ - api_ck_p = clk_get(NULL, "api_ck"); - ck_dpll1_p = clk_get(NULL, "ck_dpll1"); - ck_ref_p = clk_get(NULL, "ck_ref"); - - if (cpu_is_omap7xx()) - ck_ref.rate = 13000000; - if (cpu_is_omap16xx() && crystal_type == 2) - ck_ref.rate = 19200000; - - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", - omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), - omap_readw(ARM_CKCTL)); - - /* We want to be in syncronous scalable mode */ - omap_writew(0x1000, ARM_SYSST); - - - /* - * Initially use the values set by bootloader. Determine PLL rate and - * recalculate dependent clocks as if kernel had changed PLL or - * divisors. See also omap1_clk_late_init() that can reprogram dpll1 - * after the SRAM is initialized. - */ - { - unsigned pll_ctl_val = omap_readw(DPLL_CTL); - - ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ - if (pll_ctl_val & 0x10) { - /* PLL enabled, apply multiplier and divisor */ - if (pll_ctl_val & 0xf80) - ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; - ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; - } else { - /* PLL disabled, apply bypass divisor */ - switch (pll_ctl_val & 0xc) { - case 0: - break; - case 0x4: - ck_dpll1.rate /= 2; - break; - default: - ck_dpll1.rate /= 4; - break; - } - } - } - propagate_rate(&ck_dpll1); - /* Cache rates for clocks connected to ck_ref (not dpll1) */ - propagate_rate(&ck_ref); - omap1_show_rates(); - if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { - /* Select slicer output as OMAP input clock */ - omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, - OMAP7XX_PCC_UPLD_CTRL); - } - - /* Amstrad Delta wants BCLK high when inactive */ - if (machine_is_ams_delta()) - omap_writel(omap_readl(ULPD_CLOCK_CTRL) | - (1 << SDW_MCLK_INV_BIT), - ULPD_CLOCK_CTRL); - - /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ - /* (on 730, bit 13 must not be cleared) */ - if (cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); - else - omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); - - /* Put DSP/MPUI into reset until needed */ - omap_writew(0, ARM_RSTCT1); - omap_writew(1, ARM_RSTCT2); - omap_writew(0x400, ARM_IDLECT1); - - /* - * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) - * of the ARM_IDLECT2 register must be set to zero. The power-on - * default value of this bit is one. - */ - omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable(&armper_ck.clk); - clk_enable(&armxor_ck.clk); - clk_enable(&armtim_ck.clk); /* This should be done by timer code */ - - if (cpu_is_omap15xx()) - clk_enable(&arm_gpio_ck); - - return 0; -} - -#define OMAP1_DPLL1_SANE_VALUE 60000000 - -void __init omap1_clk_late_init(void) -{ - unsigned long rate = ck_dpll1.rate; - - /* Find the highest supported frequency and enable it */ - if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { - pr_err("System frequencies not set, using default. Check your config.\n"); - /* - * Reprogramming the DPLL is tricky, it must be done from SRAM. - */ - omap_sram_reprogram_clock(0x2290, 0x0005); - ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; - } - propagate_rate(&ck_dpll1); - omap1_show_rates(); - loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); -} diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index 5ceff05e15c0..fb360902c6fc 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -77,6 +77,8 @@ void omap1_init_irq(void); void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs); void omap1_init_late(void); void omap1_restart(enum reboot_mode, const char *); +int omap1_clk_init(void); +void omap1_clk_late_init(void); extern void __init omap_check_revision(void); diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 36b03410b210..01213ad07b5c 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -25,7 +25,6 @@ #include "camera.h" #include "hardware.h" #include "common.h" -#include "clock.h" #include "mmc.h" #include "sram.h" diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index cf425aeeb240..b0465a956ea8 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -18,7 +18,6 @@ #include "mux.h" #include "iomap.h" #include "common.h" -#include "clock.h" /* * The machine specific code may provide the extra mapping besides the diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h deleted file mode 100644 index 5b8b9c8edfe3..000000000000 --- a/arch/arm/mach-omap1/opp.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/mach-omap1/opp.h - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - */ - -#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H -#define __ARCH_ARM_MACH_OMAP1_OPP_H - -#include - -struct mpu_rate { - unsigned long rate; - unsigned long xtal; - unsigned long pll_rate; - __u16 ckctl_val; - __u16 dpllctl_val; - u32 flags; -}; - -extern struct mpu_rate omap1_rate_table[]; - -#endif diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c deleted file mode 100644 index a27ca7dc03a2..000000000000 --- a/arch/arm/mach-omap1/opp_data.c +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/opp_data.c - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - */ - -#include "clock.h" -#include "opp.h" - -/*------------------------------------------------------------------------- - * Omap1 MPU rate table - *-------------------------------------------------------------------------*/ -struct mpu_rate omap1_rate_table[] = { - /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL - * NOTE: Comment order here is different from bits in CKCTL value: - * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv - */ - { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */ - CK_1710 }, - { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */ - CK_7XX }, - { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */ - CK_16XX }, - { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */ - CK_16XX }, - { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */ - CK_16XX }, - { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */ - CK_16XX }, - { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */ - CK_16XX }, - { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */ - CK_7XX }, - { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */ - CK_16XX|CK_7XX }, - { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */ - CK_1510 }, - { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */ - CK_16XX|CK_1510|CK_310|CK_7XX }, - { 96000000, 12000000, 96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */ - CK_16XX|CK_1510|CK_310|CK_7XX }, - { 60000000, 12000000, 60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */ - CK_16XX|CK_1510|CK_310|CK_7XX }, - { 30000000, 12000000, 60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */ - CK_16XX|CK_1510|CK_310|CK_7XX }, - { 0, 0, 0, 0, 0 }, -}; - diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index dd3743c891b7..754119028138 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -61,7 +61,6 @@ #include "mux.h" #include "irqs.h" #include "iomap.h" -#include "clock.h" #include "pm.h" #include "soc.h" #include "sram.h" From patchwork Thu Aug 8 21:43:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170862 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9131653ile; Thu, 8 Aug 2019 14:44:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFH4MRKzvsgbm0eXJlFlvuZaxuSBw03cGtYroX3g6w1vloRnQAitSTU5Vjj54VO+mN707u X-Received: by 2002:a17:90a:b394:: with SMTP id e20mr6123998pjr.76.1565300667545; Thu, 08 Aug 2019 14:44:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565300667; cv=none; d=google.com; s=arc-20160816; b=JQBBW0PkMzk9IfhoV2+tQLE/A5xoutHIS/YpAb7k6Z/NrC76qs79sC3yj47pDD8Jo3 vqb54JmpmfhMDN6am9xUnjxhaxRrKfmshcyj1h0b63K0lZIl+iQ5YlWTzAXuAhs5EZxj viA1YVLNEn3ReDzVBwa/n8w8CF/yRPQpIYoj9jGWId+8HYg16QwDEQDnibOyYv3gndiX 0kdQufDh8YX2IOzjV5OQo/3BybEH/1IIINrZt4m71hpXqJbreyAnfLyy2+nkCbrk6pLr YNNuwjv0/VOzqJAFtzcXikEa9fM+pXQtMFpLf7YmYcDKl9LBEIZIG44IevLKnjLQkDKW G2yw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id 145si52962955pfb.262.2019.08.08.14.44.27; Thu, 08 Aug 2019 14:44:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725785AbfHHVo0 (ORCPT + 5 others); Thu, 8 Aug 2019 17:44:26 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:43669 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390296AbfHHVo0 (ORCPT ); Thu, 8 Aug 2019 17:44:26 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.129]) with ESMTPA (Nemesis) id 1MkYHO-1iazFW2Apy-00m3mb; Thu, 08 Aug 2019 23:43:52 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Paul Walmsley Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 20/22] ARM: omap1: clk: use clk_init_data Date: Thu, 8 Aug 2019 23:43:38 +0200 Message-Id: <20190808214347.2865294-1-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:7CygOTNWAv1Av7TOKR/RAGZa48JmJsWvplaC3q5QjRSaot6Tf3G xSdZFqrddrDFAUElqBsK+HbI9Zq3JadcMPECZH3AUDApmDnaQ5ROETqev+ECyLyb7Ssjsqv ch2dT6C9CKYmOAZWc24iiTzrXHOC04g54TAGVHztuQ1c2wZhIo5PHxS8cRazgy4zMtDM9Uy ffAeBDyJSJhR0yyZTaJ7g== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:hFAG7pdixrc=:J0ayFI++OrSdTM60JwL4ky Ducp45r6hG17ig/7aS5TRt2AeEPp858c405l9BwICopZ/ZKRxEfFd+KRUYLCh8aYDbtVFdj2/ NYkAKvlKG/Bopj1v2PFj+HmUT3Wx6tUmFTlU6cX4vUbk02qPkIjvWqCEFwTr/UjLvO0cHCEiJ AWxH2NNPk5HuNRkv0ZlvWQ/9LOkNFSptgN3WZqgkXA2tDPje6BurI7sK2FD5RyFL+S0lQs3Ea T8aVHrdU7C6rtJ+gctWqX+Tuy7edQN2K6KqoSEZ9ZIOT2ja2EwjNA8fgwRCN+qttYtCyoSujR I/AeQa7s7DfQvtqxIIIz4aEynOdjkiheGSjGDrIAYUea9/MfFV3JwNye0lp5RMm3L85Ciwh98 EC091m7EGIK9mMT2FnFzmwJvpwcFaSBc9Ohjnn8oNoTUfjcIwBsR0nDE2M+LQ1S75SG70wJL4 A0rfe7k7MWCsVFYFskYDlYye19oQ3yi1VxmjGp7hZmoSh9LHmWLqYe2rcRDcDavCGu/VHzmLq DgLhoYWOgBLzQkxn7vnwHTBQnlyfFVYYzaKd3d45RejZK5G4/8DVt1kg4ByODWlD6PCd3CHEy +2zmiqPo6mFEyAp3/m3MyjrT94f2bEe0C+pnf3Vt6jlv35g7MpX2RW7DahxtiSDO9SHmVkO26 CWXsDgsyW1ZAKYY78mJ5HS7NeM5Ahihwm+hTjSNFKvcBLu+6JCX7HE0QThx1nLH5sF16F7B2r Qeuu508cxl8bf5CEjeHzFxJwLPq1YpsIxXz+Gg== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The common_clk layer requires common data to be passed as clk_init_data, so mimic this here. Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap1/clock.c | 266 ++++++++++++++---------------------- 1 file changed, 99 insertions(+), 167 deletions(-) -- 2.20.0 diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 8b4d5ee13ba0..a951c787adb4 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -128,15 +128,22 @@ struct clk { struct clk_hw *clk_hw; }; +struct clk_init_data { + const char *name; + const struct clk_ops *ops; + const struct clk_hw **parent_hws; + u8 num_parents; + unsigned long flags; +}; + struct clk_hw { struct clk clk; + const struct clk_init_data *init; }; struct omap1_clk { struct clk_hw clk_hw; struct list_head node; - const struct clk_ops *ops; - const char *name; struct omap1_clk *parent; struct list_head children; struct list_head sibling; /* node for children */ @@ -686,7 +693,7 @@ static void omap1_clk_disable(struct clk_hw *clk_hw) struct clk_hw *parent = clk_hw_get_parent(clk_hw); if (clk->usecount > 0 && !(--clk->usecount)) { - clk->ops->disable(clk_hw); + clk->clk_hw.init->ops->disable(&clk->clk_hw); if (likely(parent)) { omap1_clk_disable(parent); if (clk->flags & CLOCK_NO_IDLE_PARENT) @@ -711,7 +718,7 @@ static omap1_clk_enable(struct clk_hw *clk_hw) omap1_clk_deny_idle(parent); } - ret = clk->ops->enable(&clk->clk_hw); + ret = clk->clk_hw.init->ops->enable(&clk->clk_hw); if (ret) { if (parent) omap1_clk_disable(parent); @@ -733,7 +740,7 @@ static int omap1_clk_enable_generic(struct clk_hw *clk_hw) if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", - clk->name); + clk->clk_hw.init->name); return -EINVAL; } @@ -865,8 +872,8 @@ static long omap1_clk_round_rate(struct clk_hw *clk_hw, unsigned long rate) parent_rate = parent_clk->rate; } - if (clk->ops->round_rate != NULL) - return clk->ops->round_rate(clk_hw, rate, &parent_rate); + if (clk_hw->init->ops->round_rate != NULL) + return clk_hw->init->ops->round_rate(clk_hw, rate, &parent_rate); if (parent) parent_clk->rate = parent_rate; @@ -876,7 +883,6 @@ static long omap1_clk_round_rate(struct clk_hw *clk_hw, unsigned long rate) static int omap1_clk_set_rate(struct clk_hw *clk_hw, unsigned long rate) { - struct omap1_clk *clk = to_omap1_clk(clk_hw); struct clk_hw *parent = clk_hw_get_parent(clk_hw); unsigned long parent_rate = 0; int ret = -EINVAL; @@ -884,8 +890,9 @@ static int omap1_clk_set_rate(struct clk_hw *clk_hw, unsigned long rate) if (parent) parent_rate = to_omap1_clk(parent)->rate; - if (clk->ops->set_rate) - ret = clk->ops->set_rate(clk_hw, rate, parent_rate); + if (clk_hw->init->ops->set_rate) + ret = clk_hw->init->ops->set_rate(clk_hw, rate, parent_rate); + return ret; } @@ -895,8 +902,8 @@ static void propagate_rate(struct omap1_clk *tclk) struct omap1_clk *clkp; list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->ops->recalc_rate) - clkp->rate = clkp->ops->recalc_rate(&clkp->clk_hw, tclk->rate); + if (clkp->clk_hw.init->ops->recalc_rate) + clkp->rate = clkp->clk_hw.init->ops->recalc_rate(&clkp->clk_hw, tclk->rate); propagate_rate(clkp); } } @@ -932,7 +939,7 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clockfw_lock, flags); if (_clk->usecount == 0) { pr_err("Trying disable clock %s with 0 usecount\n", - _clk->name); + _clk->clk_hw.init->name); WARN_ON(1); goto out; } @@ -1068,12 +1075,14 @@ static int clk_register(struct device *dev, struct clk_hw *clk_hw) clk_hw->clk.clk_hw = clk_hw; mutex_lock(&clocks_mutex); - if (clk->parent) + if (clk_hw->init->num_parents) { + clk->parent = to_omap1_clk(clk_hw->init->parent_hws[0]); list_add(&clk->sibling, &clk->parent->children); + } list_add(&clk->node, &clocks); - if (clk->ops->init) - clk->ops->init(&clk->clk_hw); + if (clk_hw->init->ops->init) + clk_hw->init->ops->init(clk_hw); mutex_unlock(&clocks_mutex); return 0; @@ -1102,14 +1111,28 @@ static const struct clk_ops clkops_followparent = { .recalc_rate = followparent_recalc, }; +#define CLK_INIT(_name, _ops, _parent) \ + .clk_hw.init = &(struct clk_init_data) { \ + .name = (_name), \ + .ops = (_ops), \ + .parent_hws = (const struct clk_hw *[1])\ + {&(_parent)->clk_hw}, \ + .num_parents = 1, \ + } + +#define CLK_INIT_ROOT(_name, _ops) \ + .clk_hw.init = &(struct clk_init_data) { \ + .name = (_name), \ + .ops = (_ops), \ + } + /* * Dummy clock * * Used for clock aliases that are needed on some OMAPs, but not others */ static struct omap1_clk dummy_ck = { - .name = "dummy", - .ops = &clkops_null, + CLK_INIT_ROOT("dummy", &clkops_null), }; /* @@ -1128,7 +1151,7 @@ static void omap1_clk_disable_unused(struct omap1_clk *clk) * has not enabled any DSP clocks */ if (clk->enable_reg == DSP_IDLECT2) { pr_info("Skipping reset check for DSP domain clock \"%s\"\n", - clk->name); + clk->clk_hw.init->name); return; } @@ -1141,8 +1164,8 @@ static void omap1_clk_disable_unused(struct omap1_clk *clk) if ((regval32 & (1 << clk->enable_bit)) == 0) return; - printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); - clk->ops->disable(&clk->clk_hw); + printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->clk_hw.init->name); + clk->clk_hw.init->ops->disable(&clk->clk_hw); printk(" done\n"); } @@ -1155,7 +1178,7 @@ static int __init clk_disable_unused(void) spin_lock_irqsave(&clockfw_lock, flags); list_for_each_entry(ck, &clocks, node) { - if (ck->ops == &clkops_null) + if (ck->clk_hw.init->ops == &clkops_null) continue; if (ck->usecount > 0 || !ck->enable_reg) @@ -1248,17 +1271,13 @@ late_initcall(clk_debugfs_init); /* * Omap1 clocks */ - static struct omap1_clk ck_ref = { - .name = "ck_ref", - .ops = &clkops_null, + CLK_INIT_ROOT("ck_ref", &clkops_null), .rate = 12000000, }; static struct omap1_clk ck_dpll1 = { - .name = "ck_dpll1", - .ops = &clkops_null, - .parent = &ck_ref, + CLK_INIT("ck_dpll1", &clkops_null, &ck_ref), }; static const struct clk_ops clkops_generic_followparent = { @@ -1273,9 +1292,7 @@ static const struct clk_ops clkops_generic_followparent = { */ static struct arm_idlect1_clk ck_dpll1out = { .clk = { - .name = "ck_dpll1out", - .ops = &clkops_generic_followparent, - .parent = &ck_dpll1, + CLK_INIT("ck_dpll1out", &clkops_generic_followparent, &ck_dpll1), .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_CKOUT_ARM, @@ -1291,15 +1308,13 @@ static const struct clk_ops clkops_sossi = { }; static struct omap1_clk sossi_ck = { - .name = "ck_sossi", - .ops = &clkops_sossi, - .parent = &ck_dpll1out.clk, + CLK_INIT("ck_sossi", &clkops_sossi, &ck_dpll1out.clk), .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, }; -struct clk_ops clkops_null_ckctl = { +static const struct clk_ops clkops_null_ckctl = { .enable = clkll_enable_null, .disable = clkll_disable_null, .recalc_rate = omap1_ckctl_recalc, @@ -1308,13 +1323,11 @@ struct clk_ops clkops_null_ckctl = { }; static struct omap1_clk arm_ck = { - .name = "arm_ck", - .ops = &clkops_null_ckctl, - .parent = &ck_dpll1, + CLK_INIT("arm_ck", &clkops_null_ckctl, &ck_dpll1), .rate_offset = CKCTL_ARMDIV_OFFSET, }; -struct clk_ops clkops_generic_ckctl = { +static const struct clk_ops clkops_generic_ckctl = { .enable = omap1_clk_enable_generic, .disable = omap1_clk_disable_generic, .recalc_rate = omap1_ckctl_recalc, @@ -1324,9 +1337,7 @@ struct clk_ops clkops_generic_ckctl = { static struct arm_idlect1_clk armper_ck = { .clk = { - .name = "armper_ck", - .ops = &clkops_generic_ckctl, - .parent = &ck_dpll1, + CLK_INIT("armper_ck", &clkops_generic_ckctl, &ck_dpll1), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_PERCK, @@ -1340,18 +1351,14 @@ static struct arm_idlect1_clk armper_ck = { * activation. [ GPIO code for 1510 ] */ static struct omap1_clk arm_gpio_ck = { - .name = "ick", - .ops = &clkops_generic_followparent, - .parent = &ck_dpll1, + CLK_INIT("ick", &clkops_generic_followparent, &ck_dpll1), .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_GPIOCK, }; static struct arm_idlect1_clk armxor_ck = { .clk = { - .name = "armxor_ck", - .ops = &clkops_generic_followparent, - .parent = &ck_ref, + CLK_INIT("armxor_ck", &clkops_generic_followparent, &ck_ref), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_XORPCK, @@ -1361,9 +1368,7 @@ static struct arm_idlect1_clk armxor_ck = { static struct arm_idlect1_clk armtim_ck = { .clk = { - .name = "armtim_ck", - .ops = &clkops_generic_followparent, - .parent = &ck_ref, + CLK_INIT("armtim_ck", &clkops_generic_followparent, &ck_ref), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_TIMCK, @@ -1379,9 +1384,7 @@ static const struct clk_ops clkops_fixed_divisor = { static struct arm_idlect1_clk armwdt_ck = { .clk = { - .name = "armwdt_ck", - .ops = &clkops_generic, - .parent = &ck_ref, + CLK_INIT("armwdt_ck", &clkops_generic, &ck_ref), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_WDTCK, @@ -1391,9 +1394,7 @@ static struct arm_idlect1_clk armwdt_ck = { }; static struct omap1_clk arminth_ck16xx = { - .name = "arminth_ck", - .ops = &clkops_followparent, - .parent = &arm_ck, + CLK_INIT("arminth_ck", &clkops_followparent, &arm_ck), /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * @@ -1402,18 +1403,14 @@ static struct omap1_clk arminth_ck16xx = { }; static struct omap1_clk dsp_ck = { - .name = "dsp_ck", - .ops = &clkops_generic_ckctl, - .parent = &ck_dpll1, + CLK_INIT("dsp_ck", &clkops_generic_ckctl, &ck_dpll1), .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), .enable_bit = EN_DSPCK, .rate_offset = CKCTL_DSPDIV_OFFSET, }; static struct omap1_clk dspmmu_ck = { - .name = "dspmmu_ck", - .ops = &clkops_null_ckctl, - .parent = &ck_dpll1, + CLK_INIT("dspmmu_ck", &clkops_null_ckctl, &ck_dpll1), .rate_offset = CKCTL_DSPMMUDIV_OFFSET, }; @@ -1426,9 +1423,7 @@ static const struct clk_ops clkops_dspck = { }; static struct omap1_clk dspper_ck = { - .name = "dspper_ck", - .ops = &clkops_dspck, - .parent = &ck_dpll1, + CLK_INIT("dspper_ck", &clkops_dspck, &ck_dpll1), .enable_reg = DSP_IDLECT2, .enable_bit = EN_PERCK, .rate_offset = CKCTL_PERDIV_OFFSET, @@ -1441,26 +1436,20 @@ static const struct clk_ops clkops_dspck_followparent = { }; static struct omap1_clk dspxor_ck = { - .name = "dspxor_ck", - .ops = &clkops_dspck_followparent, - .parent = &ck_ref, + CLK_INIT("dspxor_ck", &clkops_dspck_followparent, &ck_ref), .enable_reg = DSP_IDLECT2, .enable_bit = EN_XORPCK, }; static struct omap1_clk dsptim_ck = { - .name = "dsptim_ck", - .ops = &clkops_dspck_followparent, - .parent = &ck_ref, + CLK_INIT("dsptim_ck", &clkops_dspck_followparent, &ck_ref), .enable_reg = DSP_IDLECT2, .enable_bit = EN_DSPTIMCK, }; static struct arm_idlect1_clk tc_ck = { .clk = { - .name = "tc_ck", - .ops = &clkops_null_ckctl, - .parent = &ck_dpll1, + CLK_INIT("tc_ck", &clkops_null_ckctl, &ck_dpll1), .flags = CLOCK_IDLE_CONTROL, .rate_offset = CKCTL_TCDIV_OFFSET, }, @@ -1468,9 +1457,7 @@ static struct arm_idlect1_clk tc_ck = { }; static struct omap1_clk arminth_ck1510 = { - .name = "arminth_ck", - .ops = &clkops_followparent, - .parent = &tc_ck.clk, + CLK_INIT("arminth_ck", &clkops_followparent, &tc_ck.clk), /* Note: On 1510 the frequency follows TC_CK * * 16xx version is in MPU clocks. @@ -1479,24 +1466,18 @@ static struct omap1_clk arminth_ck1510 = { static struct omap1_clk tipb_ck = { /* No-idle controlled by "tc_ck" */ - .name = "tipb_ck", - .ops = &clkops_followparent, - .parent = &tc_ck.clk, + CLK_INIT("tipb_ck", &clkops_followparent, &tc_ck.clk), }; static struct omap1_clk l3_ocpi_ck = { /* No-idle controlled by "tc_ck" */ - .name = "l3_ocpi_ck", - .ops = &clkops_generic_followparent, - .parent = &tc_ck.clk, + CLK_INIT("l3_ocpi_ck", &clkops_generic_followparent, &tc_ck.clk), .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_OCPI_CK, }; static struct omap1_clk tc1_ck = { - .name = "tc1_ck", - .ops = &clkops_generic_followparent, - .parent = &tc_ck.clk, + CLK_INIT("tc1_ck", &clkops_generic_followparent, &tc_ck.clk), .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC1_CK, }; @@ -1506,31 +1487,23 @@ static struct omap1_clk tc1_ck = { * activation. [ pm.c (SRAM), CCP, Camera ] */ static struct omap1_clk tc2_ck = { - .name = "tc2_ck", - .ops = &clkops_generic_followparent, - .parent = &tc_ck.clk, + CLK_INIT("tc2_ck", &clkops_generic_followparent, &tc_ck.clk), .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC2_CK, }; static struct omap1_clk dma_ck = { /* No-idle controlled by "tc_ck" */ - .name = "dma_ck", - .ops = &clkops_followparent, - .parent = &tc_ck.clk, + CLK_INIT("dma_ck", &clkops_followparent, &tc_ck.clk), }; static struct omap1_clk dma_lcdfree_ck = { - .name = "dma_lcdfree_ck", - .ops = &clkops_followparent, - .parent = &tc_ck.clk, + CLK_INIT("dma_lcdfree_ck", &clkops_followparent, &tc_ck.clk), }; static struct arm_idlect1_clk api_ck = { .clk = { - .name = "api_ck", - .ops = &clkops_generic_followparent, - .parent = &tc_ck.clk, + CLK_INIT("api_ck", &clkops_generic_followparent, &tc_ck.clk), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_APICK, @@ -1540,9 +1513,7 @@ static struct arm_idlect1_clk api_ck = { static struct arm_idlect1_clk lb_ck = { .clk = { - .name = "lb_ck", - .ops = &clkops_generic_followparent, - .parent = &tc_ck.clk, + CLK_INIT("lb_ck", &clkops_generic_followparent, &tc_ck.clk), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LBCK, @@ -1551,21 +1522,15 @@ static struct arm_idlect1_clk lb_ck = { }; static struct omap1_clk rhea1_ck = { - .name = "rhea1_ck", - .ops = &clkops_followparent, - .parent = &tc_ck.clk, + CLK_INIT("rhea1_ck", &clkops_followparent, &tc_ck.clk), }; static struct omap1_clk rhea2_ck = { - .name = "rhea2_ck", - .ops = &clkops_followparent, - .parent = &tc_ck.clk, + CLK_INIT("rhea2_ck", &clkops_followparent, &tc_ck.clk), }; static struct omap1_clk lcd_ck_16xx = { - .name = "lcd_ck", - .ops = &clkops_generic_ckctl, - .parent = &ck_dpll1, + CLK_INIT("lcd_ck", &clkops_generic_ckctl, &ck_dpll1), .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, .rate_offset = CKCTL_LCDDIV_OFFSET, @@ -1573,9 +1538,7 @@ static struct omap1_clk lcd_ck_16xx = { static struct arm_idlect1_clk lcd_ck_1510 = { .clk = { - .name = "lcd_ck", - .ops = &clkops_generic_ckctl, - .parent = &ck_dpll1, + CLK_INIT("lcd_ck", &clkops_generic_ckctl, &ck_dpll1), .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, @@ -1598,10 +1561,8 @@ static const struct clk_ops clkops_uart = { * XXX does this need SYSC register handling? */ static struct omap1_clk uart1_1510 = { - .name = "uart1_ck", - .ops = &clkops_uart, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + CLK_INIT("uart1_ck", &clkops_uart, &armper_ck.clk), .rate = 12000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1616,10 +1577,8 @@ static struct omap1_clk uart1_1510 = { */ static struct uart_clk uart1_16xx = { .clk = { - .name = "uart1_ck", - .ops = &clkops_uart_16xx, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + CLK_INIT("uart1_ck", &clkops_uart_16xx, &armper_ck.clk), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1635,10 +1594,8 @@ static struct uart_clk uart1_16xx = { * XXX does this need SYSC register handling? */ static struct omap1_clk uart2_ck = { - .name = "uart2_ck", - .ops = &clkops_uart, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + CLK_INIT("uart2_ck", &clkops_uart, &armper_ck.clk), .rate = 12000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1652,10 +1609,8 @@ static struct omap1_clk uart2_ck = { * XXX does this need SYSC register handling? */ static struct omap1_clk uart3_1510 = { - .name = "uart3_ck", - .ops = &clkops_uart, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + CLK_INIT("uart3_ck", &clkops_uart, &armper_ck.clk), .rate = 12000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1670,10 +1625,8 @@ static struct omap1_clk uart3_1510 = { */ static struct uart_clk uart3_16xx = { .clk = { - .name = "uart3_ck", - .ops = &clkops_uart_16xx, /* Direct from ULPD, no real parent */ - .parent = &armper_ck.clk, + CLK_INIT("uart3_ck", &clkops_uart_16xx, &armper_ck.clk), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1683,9 +1636,8 @@ static struct uart_clk uart3_16xx = { }; static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ - .name = "usb_clko", - .ops = &clkops_generic, /* Direct from ULPD, no parent */ + CLK_INIT_ROOT("usb_clko", &clkops_generic), .rate = 6000000, .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), @@ -1693,9 +1645,8 @@ static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ }; static struct omap1_clk usb_hhc_ck1510 = { - .name = "usb_hhc_ck", - .ops = &clkops_generic, /* Direct from ULPD, no parent */ + CLK_INIT_ROOT("usb_hhc_ck", &clkops_generic), .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1703,9 +1654,8 @@ static struct omap1_clk usb_hhc_ck1510 = { }; static struct omap1_clk usb_hhc_ck16xx = { - .name = "usb_hhc_ck", - .ops = &clkops_generic, /* Direct from ULPD, no parent */ + CLK_INIT_ROOT("usb_hhc_ck", &clkops_generic), .rate = 48000000, /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ .flags = ENABLE_REG_32BIT, @@ -1714,36 +1664,32 @@ static struct omap1_clk usb_hhc_ck16xx = { }; static struct omap1_clk usb_dc_ck = { - .name = "usb_dc_ck", - .ops = &clkops_generic, /* Direct from ULPD, no parent */ + CLK_INIT_ROOT("usb_dc_ck", &clkops_generic), .rate = 48000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, }; static struct omap1_clk uart1_7xx = { - .name = "uart1_ck", - .ops = &clkops_generic, /* Direct from ULPD, no parent */ + CLK_INIT_ROOT("uart1_ck", &clkops_generic), .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 9, }; static struct omap1_clk uart2_7xx = { - .name = "uart2_ck", - .ops = &clkops_generic, /* Direct from ULPD, no parent */ + CLK_INIT_ROOT("uart2_ck", &clkops_generic), .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = 11, }; static struct omap1_clk mclk_1510 = { - .name = "mclk", - .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + CLK_INIT_ROOT("mclk", &clkops_generic), .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, @@ -1758,33 +1704,28 @@ static const struct clk_ops clkops_ext_clk = { }; static struct omap1_clk mclk_16xx = { - .name = "mclk", - .ops = &clkops_ext_clk, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + CLK_INIT_ROOT("mclk", &clkops_ext_clk), .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), .enable_bit = COM_ULPD_PLL_CLK_REQ, }; static struct omap1_clk bclk_1510 = { - .name = "bclk", - .ops = &clkops_generic, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + CLK_INIT_ROOT("bclk", &clkops_generic), .rate = 12000000, }; static struct omap1_clk bclk_16xx = { - .name = "bclk", - .ops = &clkops_ext_clk, /* Direct from ULPD, no parent. May be enabled by ext hardware. */ + CLK_INIT_ROOT("bclk", &clkops_ext_clk), .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), .enable_bit = SWD_ULPD_PLL_CLK_REQ, }; static struct omap1_clk mmc1_ck = { - .name = "mmc1_ck", - .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, + CLK_INIT("mmc1_ck", &clkops_generic, &armper_ck.clk), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1796,10 +1737,8 @@ static struct omap1_clk mmc1_ck = { * CONF_MOD_MCBSP3_AUXON ?? */ static struct omap1_clk mmc2_ck = { - .name = "mmc2_ck", - .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, + CLK_INIT("mmc2_ck", &clkops_generic, &armper_ck.clk), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), @@ -1807,10 +1746,8 @@ static struct omap1_clk mmc2_ck = { }; static struct omap1_clk mmc3_ck = { - .name = "mmc3_ck", - .ops = &clkops_generic, /* Functional clock is direct from ULPD, interface clock is ARMPER */ - .parent = &armper_ck.clk, + CLK_INIT("mmc3_ck", &clkops_generic, &armper_ck.clk), .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), @@ -1826,25 +1763,20 @@ static const struct clk_ops clkops_mpu = { }; static struct omap1_clk virtual_ck_mpu = { - .name = "mpu", - .ops = &clkops_mpu, - .parent = &arm_ck, /* Is smarter alias for */ + /* Is smarter alias for */ + CLK_INIT("mpu", &clkops_mpu, &arm_ck), }; /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK remains active during MPU idle whenever this is enabled */ static struct omap1_clk i2c_fck = { - .name = "i2c_fck", - .ops = &clkops_followparent, + CLK_INIT("i2c_fck", &clkops_followparent, &armxor_ck.clk), .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armxor_ck.clk, }; static struct omap1_clk i2c_ick = { - .name = "i2c_ick", - .ops = &clkops_followparent, + CLK_INIT("i2c_ick", &clkops_followparent, &armper_ck.clk), .flags = CLOCK_NO_IDLE_PARENT, - .parent = &armper_ck.clk, }; /* From patchwork Thu Aug 8 21:43:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170863 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9131867ile; Thu, 8 Aug 2019 14:44:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzN6u+xNl35/ynk8Kxj5uVTOUvk90VI6p0rO0CXCkdyrF1lmYH3hZfslGnEMyYtCnz8iuQC X-Received: by 2002:a17:902:6b81:: with SMTP id p1mr15662050plk.91.1565300687113; Thu, 08 Aug 2019 14:44:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565300687; cv=none; d=google.com; s=arc-20160816; b=oxbD+WFcAttkSMpS6b9wpp4eGFMoh7IpgTtjAY4s7Ul9W1jPVrDCZoyqtFwhgJsSOs 4wqvVpO1Y0EJq1JdcSUcC33+3SmirFFOVX9iJ/rHMSlrpWe3Edr//BqZiBQoTW26XDes hqP+sYenhVLXMVC1/ZZCG8T3Vq9ZkJmAtO9uRfG1wXkX8Ir7qIxtlGsYGm8w7qtIXQck u+dV31OmBnJ77J0Dp0aJ2IzCX/A46bYMKX8kyu5x4PBVuLn2secrDZT0kCgFDlk/wQQh ju9XzSugLi0sO4RsM+Vt7xDkg5RMoot4G7DCD+LugKRtr/hAdKh8Zm4qd6gRu+Dym0/W piWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=+K65L2NYHSlnuA4UlwIdf/0untVO+Ai6zXnUgMIeDOA=; b=CZyanQ+oHlTVLyqB6O681zeh0zDb+yJa9s5D5adQ0w6IHVxEQoX48FxTlGVkVhytaM SJPy45RjRbNQxRFci6A6fc4QFCvnBNpbsXpOnuw7XAMarWzmJOz4KLHNiupqtxoAcncV F7QIxrNAwKYJT8phgrSXq+FEUiUJ9dfDTJg6oSARO71ICfBnkFkfv4v6MH4R5JUWDENv 4FreHiNoH+ok3c7s5vkc7Ev4wm+1Lj8LDNv76VU12M9y6zNwk6k3t4SgK1XZgvZ48xfx GZmI7jch7sI7IUMpetKzTpfLLTfOKz5SdW0tFHBQremH/hHWGwOEJi/5c/S5eCH3ZfWV HpOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d25si53545875pge.301.2019.08.08.14.44.46; Thu, 08 Aug 2019 14:44:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389974AbfHHVoq (ORCPT + 5 others); Thu, 8 Aug 2019 17:44:46 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:45475 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725535AbfHHVoq (ORCPT ); Thu, 8 Aug 2019 17:44:46 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue010 [212.227.15.129]) with ESMTPA (Nemesis) id 1Mi2eP-1iZYbR2men-00e8dS; Thu, 08 Aug 2019 23:44:16 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen , Paul Walmsley Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 21/22] ARM: omap1: use common clk framework Date: Thu, 8 Aug 2019 23:43:39 +0200 Message-Id: <20190808214347.2865294-2-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808214347.2865294-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> <20190808214347.2865294-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:GQIn1tnKFajJAEk26jAMrrfsIrasnMIc5IJrTtbH4vX4wMZ/nlo Pe7NOrxJYdEhtvdWKFmane20TcDdxDqP+/10nbePXuUa+KV+ImVxej3Hs9tkt85D+GWQhnr jyCpgxiP7zDfXdR9AkYHftd88kgy7pi9pn/keCEGZ4xpyMsT/nW/cSPztjhFWbTeBrQRgft CQTb5GXOkhXzGIY7hZE5w== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:VLFzM9nHg98=:6iqdv3DdnolRFOat8mfQv/ g25M4pkILEGBgQk3DWOznzVih8/JwkvivS5p3hE5r4xjnMIZftk/y67s8t26h8Y0ZCBeSCUD6 KV3/Zbf3HQrzIQcwr8czjVw8qnFUeQrNlTIkrjPefzJGczIZdj4xtJA3QthB1HBvbfVqlJBPc 6WyfpT/07OaeB1nwpStohbQr21CL7Tgi0vG9Vk2pZz3wtYuXmRlsOUXufQORzS+yCZgyZmpvJ SRYx8ebfCL25sQ5FvSuKB2dmuR49+FGhcfelH9zllwMZHKd3EXM80jbaQa6Jb146gMHIgfSe1 4I9q/aBBk8DJel/iPeEZd78447X1P6eOUj7cE3z69OPpXjd1a0I4MUgI8SQFvT64Y7auAMSrK 7wdPQtUq7OVdbjpoR3Or2G1VgvAPxDK57YeSWtQ3VXEmWqXQaQFQMqyLSE/UeTcAOoGCRvkZI IvfSANofRM/nhFEUUv3cvZMeCW/j7PEibXp+hM+0AVvm2feYMHO6j/jxKG8LxFFJnhbi/et0v ChUfLvFK7sn7N2rqeywVlIikb1MCtnYkFHhRV9EebK9obeBGJdiUG/sK/JmuQXyQ3p6TZIwff HHCtF/3E69hNJQK97bX1r2QppgJl8ZnbJI5HAd795/e5lBz+3wDlLJi/a/wMdYsUxDbkJWI9h KcrIWFzjXHXhUXUAN6Yz5Fffq5+e3nNBBd4Dpk+dEstmR3FtI5WhJ0s0HwwzDx3S6f8RGsqLF XPB1ksoL5yWQcMBIQIaO7HnGIY4nJGsH2dlY3Q== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The omap1 clock driver now uses types and calling conventions that are compatible with the common clk core. Turn on CONFIG_COMMON_CLK and remove all the code that is now duplicated. Note: if this previous steps didn't already break it, this one most likely will, because the interfaces are very likely to have different semantics. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/mach-omap1/clock.c | 413 +----------------------------------- 2 files changed, 4 insertions(+), 410 deletions(-) -- 2.20.0 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0febd7a1d65f..17a21f75f386 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -496,6 +496,7 @@ config ARCH_OMAP1 select ARCH_OMAP select CLKDEV_LOOKUP select CLKSRC_MMIO + select COMMON_CLK select FORCE_PCI if PCCARD select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index a951c787adb4..1f105c659e7e 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include @@ -52,32 +53,6 @@ struct omap1_clk_lookup { #define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ #define CK_1710 (1 << 4) /* 1710 extra for rate selection */ -/** - * struct clk_ops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @recalc_rate: fn ptr that returns the clock's current rate - * @set_rate: fn ptr that can change the clock's current rate - * @round_rate: fn ptr that can round the clock's current rate - * @init: fn ptr to do clock-specific initialization - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clk_ops { - int (*enable)(struct clk_hw *); - void (*disable)(struct clk_hw *); - unsigned long (*recalc_rate)(struct clk_hw *, unsigned long); - int (*set_rate)(struct clk_hw *, unsigned long, unsigned long); - long (*round_rate)(struct clk_hw *, unsigned long, unsigned long *); - void (*init)(struct clk_hw *); -}; - /* * struct omap1_clk.flags possibilities * @@ -90,12 +65,8 @@ struct clk_ops { /** * struct omap1_clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list * @ops: struct clkops * for this clock * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children * @rate: current clock rate * @enable_reg: register to write to enable the clock (see @enable_bit) * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) @@ -115,38 +86,13 @@ struct clk_ops { * clocks and decremented by the clock code when clk_disable() is * called on child clocks. * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) + * XXX @usecount should be marked for internal use only. * * XXX The notion of the clock's current rate probably needs to be * separated from the clock's target rate. */ -struct clk { - struct clk_hw *clk_hw; -}; - -struct clk_init_data { - const char *name; - const struct clk_ops *ops; - const struct clk_hw **parent_hws; - u8 num_parents; - unsigned long flags; -}; - -struct clk_hw { - struct clk clk; - const struct clk_init_data *init; -}; - struct omap1_clk { struct clk_hw clk_hw; - struct list_head node; - struct omap1_clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ unsigned long rate; void __iomem *enable_reg; u8 enable_bit; @@ -267,10 +213,6 @@ static u32 cpu_mask; __u32 arm_idlect1_mask; static struct clk_hw *api_ck_p, *ck_dpll1_p, *ck_ref_p; -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); - /* * Omap1 specific clock functions */ @@ -677,16 +619,6 @@ static void omap1_init_ext_clk(struct clk_hw *clk_hw) clk-> rate = 96000000 / dsor; } -struct clk_hw *clk_hw_get_parent(const struct clk_hw *clk_hw) -{ - struct omap1_clk *clk = to_omap1_clk(clk_hw); - - if (!clk->parent) - return NULL; - - return &clk->parent->clk_hw; -} - static void omap1_clk_disable(struct clk_hw *clk_hw) { struct omap1_clk *clk = to_omap1_clk(clk_hw); @@ -860,173 +792,11 @@ static const struct clk_ops clkops_uart_16xx = { .disable = omap1_clk_disable_uart_functional_16xx, }; -static long omap1_clk_round_rate(struct clk_hw *clk_hw, unsigned long rate) -{ - struct omap1_clk *clk = to_omap1_clk(clk_hw); - struct clk_hw *parent = clk_hw_get_parent(clk_hw); - struct omap1_clk *parent_clk; - unsigned long parent_rate = 0; - - if (parent) { - parent_clk = to_omap1_clk(parent); - parent_rate = parent_clk->rate; - } - - if (clk_hw->init->ops->round_rate != NULL) - return clk_hw->init->ops->round_rate(clk_hw, rate, &parent_rate); - - if (parent) - parent_clk->rate = parent_rate; - - return clk->rate; -} - -static int omap1_clk_set_rate(struct clk_hw *clk_hw, unsigned long rate) -{ - struct clk_hw *parent = clk_hw_get_parent(clk_hw); - unsigned long parent_rate = 0; - int ret = -EINVAL; - - if (parent) - parent_rate = to_omap1_clk(parent)->rate; - - if (clk_hw->init->ops->set_rate) - ret = clk_hw->init->ops->set_rate(clk_hw, rate, parent_rate); - - return ret; -} - /* Propagate rate to children */ static void propagate_rate(struct omap1_clk *tclk) { - struct omap1_clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->clk_hw.init->ops->recalc_rate) - clkp->rate = clkp->clk_hw.init->ops->recalc_rate(&clkp->clk_hw, tclk->rate); - propagate_rate(clkp); - } -} - -/* - * Omap1 clock reset and init functions - */ - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap1_clk_enable(clk->clk_hw); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - struct omap1_clk *_clk = to_omap1_clk(clk->clk_hw); - - if (clk == NULL || IS_ERR(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (_clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", - _clk->clk_hw.init->name); - WARN_ON(1); - goto out; - } - - omap1_clk_disable(clk->clk_hw); - -out: - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = to_omap1_clk(clk->clk_hw)->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * Optional clock functions defined in include/linux/clk.h - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap1_clk_round_rate(clk->clk_hw, rate); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; + clk_set_rate(tclk->clk_hw.clk, tclk->rate); } -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap1_clk_set_rate(clk->clk_hw, rate); - if (ret == 0) - propagate_rate(to_omap1_clk(clk->clk_hw)); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n"); - - return -EINVAL; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - struct clk_hw *parent = clk_hw_get_parent(clk->clk_hw); - - if (!parent) - return NULL; - - return &parent->clk; -} -EXPORT_SYMBOL(clk_get_parent); - -/* - * OMAP specific clock functions shared between omap1 and omap2 - */ /* Used for clocks that always have same value as the parent clock */ static unsigned long followparent_recalc(struct clk_hw *clk_hw, unsigned long parent_rate) @@ -1047,47 +817,6 @@ static unsigned long omap_fixed_divisor_recalc(struct clk_hw *clk_hw, unsigned l return parent_rate / clk->fixed_div; } -/** - * clk_preinit - initialize any fields in the struct omap1_clk before clk init - * @clk: struct omap1_clk * to initialize - * - * Initialize any struct omap1_clk fields needed before normal clk initialization - * can run. No return value. - */ -static void clk_preinit(struct omap1_clk *clk) -{ - INIT_LIST_HEAD(&clk->children); -} - -static int clk_register(struct device *dev, struct clk_hw *clk_hw) -{ - struct omap1_clk *clk = to_omap1_clk(clk_hw); - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - /* - * trap out already registered clocks - */ - if (clk->node.next || clk->node.prev) - return 0; - - clk_hw->clk.clk_hw = clk_hw; - - mutex_lock(&clocks_mutex); - if (clk_hw->init->num_parents) { - clk->parent = to_omap1_clk(clk_hw->init->parent_hws[0]); - list_add(&clk->sibling, &clk->parent->children); - } - - list_add(&clk->node, &clocks); - if (clk_hw->init->ops->init) - clk_hw->init->ops->init(clk_hw); - mutex_unlock(&clocks_mutex); - - return 0; -} - /* * Low level helpers */ @@ -1135,139 +864,6 @@ static struct omap1_clk dummy_ck = { CLK_INIT_ROOT("dummy", &clkops_null), }; -/* - * - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -/* - * Disable any unused clocks left on by the bootloader - */ -static void omap1_clk_disable_unused(struct omap1_clk *clk) -{ - __u32 regval32; - - /* Clocks in the DSP domain need api_ck. Just assume bootloader - * has not enabled any DSP clocks */ - if (clk->enable_reg == DSP_IDLECT2) { - pr_info("Skipping reset check for DSP domain clock \"%s\"\n", - clk->clk_hw.init->name); - return; - } - - /* Is the clock already disabled? */ - if (clk->flags & ENABLE_REG_32BIT) - regval32 = __raw_readl(clk->enable_reg); - else - regval32 = __raw_readw(clk->enable_reg); - - if ((regval32 & (1 << clk->enable_bit)) == 0) - return; - - printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->clk_hw.init->name); - clk->clk_hw.init->ops->disable(&clk->clk_hw); - printk(" done\n"); -} - -static int __init clk_disable_unused(void) -{ - struct omap1_clk *ck; - unsigned long flags; - - pr_info("clock: disabling unused clocks to save power\n"); - - spin_lock_irqsave(&clockfw_lock, flags); - list_for_each_entry(ck, &clocks, node) { - if (ck->clk_hw.init->ops == &clkops_null) - continue; - - if (ck->usecount > 0 || !ck->enable_reg) - continue; - - omap1_clk_disable_unused(ck); - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -late_initcall(clk_disable_unused); -#endif - -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) -/* - * debugfs support to trace clock tree hierarchy and attributes - */ - -#include -#include - -static struct dentry *clk_debugfs_root; - -static int debug_clock_show(struct seq_file *s, void *unused) -{ - struct omap1_clk *c; - struct omap1_clk *pa; - - mutex_lock(&clocks_mutex); - seq_printf(s, "%-30s %-30s %-10s %s\n", - "clock-name", "parent-name", "rate", "use-count"); - - list_for_each_entry(c, &clocks, node) { - pa = c->parent; - seq_printf(s, "%-30s %-30s %-10lu %d\n", - c->name, pa ? pa->name : "none", c->rate, - c->usecount); - } - mutex_unlock(&clocks_mutex); - - return 0; -} - -DEFINE_SHOW_ATTRIBUTE(debug_clock); - -static void clk_debugfs_register_one(struct omap1_clk *c) -{ - struct dentry *d; - struct omap1_clk *pa = c->parent; - - d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root); - c->dent = d; - - debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount); - debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate); - debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags); -} - -static void clk_debugfs_register(struct omap1_clk *c) -{ - struct omap1_clk *pa = c->parent; - - if (pa && !pa->dent) - clk_debugfs_register(pa); - - if (!c->dent) - clk_debugfs_register_one(c); -} - -static int __init clk_debugfs_init(void) -{ - struct omap1_clk *c; - struct dentry *d; - - d = debugfs_create_dir("clock", NULL); - clk_debugfs_root = d; - - list_for_each_entry(c, &clocks, node) - clk_debugfs_register(c); - - debugfs_create_file("summary", S_IRUGO, d, NULL, &debug_clock_fops); - - return 0; -} -late_initcall(clk_debugfs_init); - -#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ - /* * Omap1 clocks */ @@ -1897,9 +1493,6 @@ int __init omap1_clk_init(void) /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; - for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - clk_preinit(to_omap1_clk(c->lk.clk_hw)); - cpu_mask = 0; if (cpu_is_omap1710()) cpu_mask |= CK_1710; From patchwork Thu Aug 8 21:47:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170864 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9135054ile; Thu, 8 Aug 2019 14:48:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTWp+xEZV1B2mG23B6pu0XSAt247GKKKSgqxIw1bPKcrp1CbDp7ZcOgla9tqIC8zCTuA4t X-Received: by 2002:a17:902:be15:: with SMTP id r21mr15289576pls.293.1565300935050; Thu, 08 Aug 2019 14:48:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565300935; cv=none; d=google.com; s=arc-20160816; b=u86n/1ubQcazYXWtL+4kvJPEpNv4pvd8NoLawJSkfhqWYAiBY3aLOpiSXTeMa1r5gJ 61VF3GwDMX7F6jZM9VfyIxSh7losJC2mpz+UgzkEqOzyOiWuL7xFzqD9FxJO+HZSQbWC EK0dHe8jkJ1nXJ1e3RVYRY1FhAoJq/T3UVjHRQ/9qOReNK8Bwmyoqw6ZhCT4EDlKF0k3 rkm/b06MHiF4nWVZ/607f4XaztxWW52ol57m9lWjRLcdXiaqyBM9zjE7nBuEzyr+vk4G Mjpsz4kGAHj6glkEYxUwFCD0o3BD+KYiojkbKx9vwNPXWm5mk+Vi3HUqOMWreTDKPb5o C9Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=K43Af3xEOZnGy6J3ioDl82F44p+FknUgvw94xBI1epA=; b=pqOj8wb1PxHU0DctF//hBCUUTrrOzrHarB+jS+rN6QGqq1a6yqVMXUqu8UYRGfTOwz /9rUh8pF6gc2KSEQ3DI258/1j6V318vdvMqaX8kLnKcopxiFZ0izkLh81ZmpbwUFl3AO RljVZn54u6PDsMtPah/DX+3NqQ/bIsiz7Cfv+x6tJuFzgBWcbvO8cYnhCI1pDX/OPkiw EC0JVtkHICrlDxHqRN1qYJXbmMDfabSrluCzisblAxrAYPbkIUcNYneFELANLusvZ/m9 Is0x8D/W+sbWUzQH+NLvziSz8wxDx0iFArSrahLHmIwsIDWwvWoL3Q0OekWRbrVR/+Vr ll7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s189si51783645pgb.272.2019.08.08.14.48.54; Thu, 08 Aug 2019 14:48:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390169AbfHHVsy (ORCPT + 5 others); Thu, 8 Aug 2019 17:48:54 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:47875 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725785AbfHHVsy (ORCPT ); Thu, 8 Aug 2019 17:48:54 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.145]) with ESMTPA (Nemesis) id 1N94qX-1iQJwe1jYF-0166ng; Thu, 08 Aug 2019 23:48:23 +0200 From: Arnd Bergmann To: Tony Lindgren , Aaro Koskinen Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Linus Walleij , Bartlomiej Zolnierkiewicz , Tomi Valkeinen , Arnd Bergmann , linux-kernel@vger.kernel.org Subject: [PATCH 22/22] ARM: omap1: enable multiplatform Date: Thu, 8 Aug 2019 23:47:44 +0200 Message-Id: <20190808214816.2964251-1-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190808212234.2213262-1-arnd@arndb.de> References: <20190808212234.2213262-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:TSY15Ec0Vm9MEnIqiHpDeo1aLv3yVAHxGEW3y7owCHC8HVezU1m t1EoU4HYJw5wjdKxa/ZpyBDQMkpQKUTEmuIvHeifK6mQGImsNTnNA9xYsQOcHUNoAhV6PNc H7wZTQaY9JkBJP+FvfBCVvGznYJdxV7JfqgFgDWJBsAL1r9pI7GlVEBqijx9j0SbAnrnFAz jpg1oDKNmfYONht7i/xuw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:lBiIPnWWbKw=:hhYXLugkIoDp5pJBIoptVK vf7Nz5y4jcRkvxsQPUxxsY4+ySLTmak3FrHe06SbB1Fk9662ilifaNYAHuBvDpWdopG+k+ihH 649IJH032bqHo6Xg7Mv0JZC0LIJac/15oeGxwh7I2aW31epNfmW0CKJflUzkmS6qJlB/1Op6Q dtkjWitfnmSJT3nELQtPrV9kxFWLQp4H5PKs90rtbesZFgRkBvvIXvGscSYBkbde9tLYcI9uF b+y1BSBODPlNW1PLu+c6XQklLFwoCtIYCZ18dq5oObiANb7ici7XD7ipO91ROlgX93iHtqWw/ D2fkABFD2XE9EjTy6rV1akL+cm7dUR/RaRYG1cw1q8VBXxbP4EIXT51w6XuKsnq+HRvdgJfaD BX0anTLN0IYBDWTdWsw9VA7tZze12vqxbiUeS3u+SBawUW68o3Eg06R0Aw5QMVzTAB+0DNhO3 CmxbXdmzf3h8gtrh2KTR+D3IWirVm9qD3Pgky8ueX+nLe/tGFKCRlvZ+Xf/5kHcC9FPvc+S3o l+p32CpslrlCy4r8gwcllSmQWpMgZG5I7A8nsXP6daWRREb6w8ljO2m6wodxWaVumK68vpoyC 0ly3k+NRVzWQjT3/vVkFFf8ytVVn5WS09Juh0TQO+gODCcVXttJ7WFpipnRDzwRRErVec3dG1 f+DenJuefvQw5zHSdoBFpHMrWFYunXS+sNDNP0T0bZIhLhDT6pfArV8px8aoYaDijQ/KeK0Zy okcYgm/JDiDZluvI2MEigbyfzNPNyQYkD5bYtA== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org With all the header files out of the way, and the clock driver converted to drivers/clk/, nothing stops us from building OMAP together with the other platforms. As usual, the decompressor support is a victim here, and is only available when CONFIG_DEBUG_LL is configured for the particular board. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 18 --- arch/arm/configs/omap1_defconfig | 3 + arch/arm/mach-omap1/Kconfig | 20 ++- arch/arm/mach-omap1/Makefile | 4 + arch/arm/mach-omap1/hardware.h | 2 +- arch/arm/mach-omap1/include/mach/uncompress.h | 117 ------------------ arch/arm/mach-omap1/serial.c | 3 +- .../mach-omap1/{include/mach => }/serial.h | 0 arch/arm/plat-omap/Makefile | 1 + 9 files changed, 26 insertions(+), 142 deletions(-) delete mode 100644 arch/arm/mach-omap1/include/mach/uncompress.h rename arch/arm/mach-omap1/{include/mach => }/serial.h (100%) -- 2.20.0 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 17a21f75f386..8542dfc5cf84 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -490,24 +490,6 @@ config ARCH_S3C24XX (), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). -config ARCH_OMAP1 - bool "TI OMAP1" - select ARCH_HAS_HOLES_MEMORYMODEL - select ARCH_OMAP - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select COMMON_CLK - select FORCE_PCI if PCCARD - select GENERIC_CLOCKEVENTS - select GENERIC_IRQ_CHIP - select GENERIC_IRQ_MULTI_HANDLER - select GPIOLIB - select HAVE_IDE - select IRQ_DOMAIN - select SPARSE_IRQ - help - Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) - endchoice menu "Multiple platform selection" diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 0c43c589f191..902125f89315 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -20,6 +20,9 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MULTI_V4T=y +CONFIG_ARCH_MULTI_V5=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP1=y CONFIG_OMAP_RESET_CLOCKS=y diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 6a2c441ab579..5b1d3a24462f 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -1,4 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_OMAP1 + bool "TI OMAP1" + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 + select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_OMAP + select CLKSRC_MMIO + select FORCE_PCI if PCCARD + select GPIOLIB + select HAVE_IDE + help + Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) + if ARCH_OMAP1 menu "TI OMAP1 specific features" @@ -14,27 +26,27 @@ config ARCH_OMAP1_AUTO select MACH_OMAP_GENERIC if (ARCH_OMAP15XX || ARCH_OMAP16XX) config ARCH_OMAP730 - depends on ARCH_OMAP1 + depends on ARCH_MULTI_V5 bool "OMAP730 Based System" select ARCH_OMAP_OTG select CPU_ARM926T select OMAP_MPU_TIMER config ARCH_OMAP850 - depends on ARCH_OMAP1 + depends on ARCH_MULTI_V5 bool "OMAP850 Based System" select ARCH_OMAP_OTG select CPU_ARM926T config ARCH_OMAP15XX - depends on ARCH_OMAP1 + depends on ARCH_MULTI_V4T default y bool "OMAP15xx Based System" select CPU_ARM925T select OMAP_MPU_TIMER config ARCH_OMAP16XX - depends on ARCH_OMAP1 + depends on ARCH_MULTI_V5 bool "OMAP16xx Based System" select ARCH_OMAP_OTG select CPU_ARM926T diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 1337d7a2754c..1f0f97868953 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,6 +3,10 @@ # Makefile for the linux kernel. # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/arch/arm/mach-omap1/include +asflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/arch/arm/mach-omap1/include +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/arch/arm/plat-omap/include + # Common support obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \ serial.o devices.o dma.o fb.o diff --git a/arch/arm/mach-omap1/hardware.h b/arch/arm/mach-omap1/hardware.h index 2cfc342c069c..232b8deef907 100644 --- a/arch/arm/mach-omap1/hardware.h +++ b/arch/arm/mach-omap1/hardware.h @@ -64,7 +64,7 @@ static inline u32 omap_cs3_phys(void) #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) -#include +#include "serial.h" /* * --------------------------------------------------------------------------- diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h deleted file mode 100644 index 9cca6a56788f..000000000000 --- a/arch/arm/mach-omap1/include/mach/uncompress.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Initially based on: - * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Rewritten by: - * Author: - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include - -#include -#include - -#include "serial.h" - -#define MDR1_MODE_MASK 0x07 - -volatile u8 *uart_base; -int uart_shift; - -/* - * Store the DEBUG_LL uart number into memory. - * See also debug-macro.S, and serial.c for related code. - */ -static void set_omap_uart_info(unsigned char port) -{ - /* - * Get address of some.bss variable and round it down - * a la CONFIG_AUTO_ZRELADDR. - */ - u32 ram_start = (u32)&uart_shift & 0xf8000000; - u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS); - *uart_info = port; -} - -static inline void putc(int c) -{ - if (!uart_base) - return; - - /* Check for UART 16x mode */ - if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) - return; - - while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) - barrier(); - uart_base[UART_TX << uart_shift] = c; -} - -static inline void flush(void) -{ -} - -/* - * Macros to configure UART1 and debug UART - */ -#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ - if (machine_is_##mach()) { \ - uart_base = (volatile u8 *)(dbg_uart); \ - uart_shift = (dbg_shft); \ - port = (dbg_id); \ - set_omap_uart_info(port); \ - break; \ - } - -#define DEBUG_LL_OMAP7XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \ - OMAP1UART##p) - -#define DEBUG_LL_OMAP1(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP1UART##p) - -static inline void arch_decomp_setup(void) -{ - int port = 0; - - /* - * Initialize the port based on the machine ID from the bootloader. - * Note that we're using macros here instead of switch statement - * as machine_is functions are optimized out for the boards that - * are not selected. - */ - do { - /* omap7xx/8xx based boards using UART1 with shift 0 */ - DEBUG_LL_OMAP7XX(1, herald); - DEBUG_LL_OMAP7XX(1, omap_perseus2); - - /* omap15xx/16xx based boards using UART1 */ - DEBUG_LL_OMAP1(1, ams_delta); - DEBUG_LL_OMAP1(1, nokia770); - DEBUG_LL_OMAP1(1, omap_h2); - DEBUG_LL_OMAP1(1, omap_h3); - DEBUG_LL_OMAP1(1, omap_innovator); - DEBUG_LL_OMAP1(1, omap_osk); - DEBUG_LL_OMAP1(1, omap_palmte); - DEBUG_LL_OMAP1(1, omap_palmz71); - - /* omap15xx/16xx based boards using UART2 */ - DEBUG_LL_OMAP1(2, omap_palmtt); - - /* omap15xx/16xx based boards using UART3 */ - DEBUG_LL_OMAP1(3, sx1); - } while (0); -} diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index d6d1843337a5..a8db332dc72e 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -19,8 +19,7 @@ #include -#include - +#include "serial.h" #include "mux.h" #include "pm.h" #include "soc.h" diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/serial.h similarity index 100% rename from arch/arm/mach-omap1/include/mach/serial.h rename to arch/arm/mach-omap1/serial.h diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 371f2ed00eda..a11c96a093c9 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -4,6 +4,7 @@ # ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-omap/include +ccflags-$(CONFIG_ARCH_OMAP1) += -I$(srctree)/arch/arm/mach-omap1/include # Common support obj-y := sram.o dma.o counter_32k.o