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[209.51.188.17]) by mx.google.com with ESMTPS id s45si37542596edd.112.2019.08.08.13.28.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Aug 2019 13:28:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="U6D/k8pu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvp12-00028V-Ix for patch@linaro.org; Thu, 08 Aug 2019 16:28:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59760) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvozO-0006xA-JI for qemu-devel@nongnu.org; Thu, 08 Aug 2019 16:26:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvozN-0001E8-Ma for qemu-devel@nongnu.org; Thu, 08 Aug 2019 16:26:22 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:45946) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hvozN-0001By-HO for qemu-devel@nongnu.org; Thu, 08 Aug 2019 16:26:21 -0400 Received: by mail-pg1-x541.google.com with SMTP id o13so44619955pgp.12 for ; Thu, 08 Aug 2019 13:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=otP5Jhfl1E+0A9Fm71GI7ndCATRFA/GRNsznhHQJJms=; b=U6D/k8pueOnINcKO96ewDohrHmZ87S9SdidjRs0w8n/eTVuJGDAiOHNgUnmrhpiRGP 0RIQ+LDvf7kDPtG6QBd+2OR7P7aVhpmAJm1A9BzZva7KSutWjNwzR7MWyitBzJhsjiLo X4svsBqMWpGXLlwgsher8u03wIP7xwcPPX6ncHlWCqt5mOJxoa1zDYxx2G98g8eqD1Hd 5jm/663k6yxKiDdxjUlRLuYS9gY8yz8rLibCJJtwasI703ZrQZLhM3HvycsF2Jj4LORs jbul/lBhoawVT4/LLWTCCSiubqe/G71gIiHi0TwqMGKsTKjxB/2FLh+Nqu/vrV5CasZC qVkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=otP5Jhfl1E+0A9Fm71GI7ndCATRFA/GRNsznhHQJJms=; b=T/WNZ73Y0J3vSsJwAWlTUF1jeh0rBJuZ7cktHML0HUi9/b8quV7G6kGSKOfd9OO+rO v+KxynhPeM2aymmQo1i0qgzk8MNB2iun35hb2aFZ7N3fxvQUbSF2Jq5EeTM1io8SIpxT LBGgNI6bqtRUOVXtz/0sncGvy4RuFgtF+/wpFDcHJZZEoysvKXje1z+Gvy2VvFNZ6hEw 0qFpL5V7po/RxkqQXL6bRjoKJ8glKzI9V/NnVkc/2zibALNR0EO03InjKXo+KnC0jGg3 cmMMXCiWkG+2rhefjJ01zRlKBW0bosvRCpyz+wOQuwH6zBLrxYjyc52DuKZMaSdFj6cX 08VA== X-Gm-Message-State: APjAAAUNCFncZGa9hIma6qbyoxcrrZ6I/rLrtFSSe367uSjNQsjUIEdO kGa+ZL0QDimAxumALSLH/fiIgmxusWY= X-Received: by 2002:a17:90a:2008:: with SMTP id n8mr5763309pjc.4.1565295979981; Thu, 08 Aug 2019 13:26:19 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.18 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:10 -0700 Message-Id: <20190808202616.13782-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 1/7] target/arm: Use tcg_gen_extract_i32 for shifter_out_im X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Extract is a compact combination of shift + and. Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 846052acea..43e005d191 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -620,14 +620,7 @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) static void shifter_out_im(TCGv_i32 var, int shift) { - if (shift == 0) { - tcg_gen_andi_i32(cpu_CF, var, 1); - } else { - tcg_gen_shri_i32(cpu_CF, var, shift); - if (shift != 31) { - tcg_gen_andi_i32(cpu_CF, cpu_CF, 1); - } - } + tcg_gen_extract_i32(cpu_CF, var, shift, 1); } /* Shift by immediate. Includes special handling for shift == 0. */ From patchwork Thu Aug 8 20:26:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 170833 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9059405ile; Thu, 8 Aug 2019 13:26:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqyPmDCpcdxRQcfnw3z5OMKAz7sSA18lq4JGtQRhoB0PFeDU/84WCAxFC0neJ0d573MplPC0 X-Received: by 2002:a50:f285:: with SMTP id f5mr5146913edm.109.1565296014274; Thu, 08 Aug 2019 13:26:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565296014; cv=none; d=google.com; s=arc-20160816; b=Awu8rPBKwVa+j+xE0E1sGC5nJt8AcDrByeA2fUMMWHT/Pu7rf5VTETWdxei5Mzv+de MrqarJn80XEccj0XyezyC41Zj8eSuDD97wokPdt/snVSurzk3Hh9QZm3UEBpggckvr1n y/q5d5NlxU34R2RoaUfT6uy8VIF1C1f+W4wvT+wItstxmCJkypkwnxU7MtQI/iA9vDgb 7P1jmz/qtZPyWoJpkEtCUeYnCeKiKUUhf4KAEPp2RbM5DLUuEeurOyDG45u6oBiaqZ7F D3bzVI6SEb4vAHSnna3/b4DiGSq65jJXH+ckN7F8hbO2FCMse5BGyrVupIMRfk3LX3mW vvzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=h5Yd6DdTtsmby24hx/qMc8uUeIQaxSevj10drk1jtIY=; b=BV21KDWgpfaLy2KQI82SuYAX5VzYxusCpIgH1NNcNFUFbih+oXhergej/M++nLkJy5 bb42ZKsBaRLqVIAqN8jJHBeQkMDLp25Ix+Sq/J1ZkVC9JekWObHYlajtbUeCN5JAtOTS iD7RLGnNZ041e4+brVKH5kzjBVKWItJiEEMUZrm2FCH+22IaXwKhCQOJzpjhXj6bbezl 8DeUg/+nCQciTEkbraLc7bx+vWC6m35diC8RlrfbWpZS1rMdetk95vW6seeBD/x0rzV7 +gYsYs38EtiI9Nqv5SCQ52EqNOYfJb8C0BuPjTGUI+bwa6zZSpe4MGS4+lqEPo4uhZDl 6gvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=li+g5mWa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:11 -0700 Message-Id: <20190808202616.13782-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 2/7] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use deposit as the composit operation to merge the bits from the two inputs. Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 43e005d191..94170af134 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8769,19 +8769,16 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) shift = (insn >> 7) & 0x1f; if (insn & (1 << 6)) { /* pkhtb */ - if (shift == 0) + if (shift == 0) { shift = 31; + } tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tmp2, tmp2); + tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); } else { /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); + tcg_gen_shli_i32(tmp2, tmp2, shift); + tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); } - tcg_gen_or_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); } else if ((insn & 0x00200020) == 0x00200000) { @@ -9817,19 +9814,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); if (insn & (1 << 5)) { /* pkhtb */ - if (shift == 0) + if (shift == 0) { shift = 31; + } tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tmp2, tmp2); + tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); } else { /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); + tcg_gen_shli_i32(tmp2, tmp2, shift); + tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); } - tcg_gen_or_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); } else { From patchwork Thu Aug 8 20:26:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 170835 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9060282ile; Thu, 8 Aug 2019 13:27:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqzgG5fXNd35yWl+636beHw/1bFzRnA0ZoNty8RYab+yixoA0ZM4eBjL5zdqxaI9PbUtoDJq X-Received: by 2002:aa7:d918:: with SMTP id a24mr17884859edr.235.1565296068021; Thu, 08 Aug 2019 13:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565296068; cv=none; d=google.com; s=arc-20160816; b=Bh8I4Y57hDEwh5VSC7L2TO+iswmsDdcnFdVFTc1cdATbnUv+3BANzjJlabxRy1dghL sk54Mai9HoSaTT+VOJf29KqUsMv8+n5a4WupuF+l7ePVFkqPNJCK+338D65cIJH12RKD 79MOIrsmtRC1e8zsrdZ0i4BR92MwXYyjTCOWjr8l9gMztT2G/UV4WOOPRL+SVkDat1MH 9+Xjk+GrfYLH+aUR9Z9c0nPUANkK8G9ZC4rVduFTTRFxnw/4RuOwaFtI5A0DXlAjjCBe bR5Yo4oyB3aExhPr2b7Ucac8rxPdiw05kzW7X++Jh3cP9F+oEnEFFG7iPPCvhxxsuks6 cZUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=KppSBSLgqldeUIFCtJ9vyMILLmhpVP0HjXn8WOkkAA4=; b=J/naLvJ2K5hvwgMuAW64NLqq9FwDwnuy5KcUUp3Kkfs90D6j0NCOagvOSeOuBMD7/v Imk2bXGcquDQvv21NY/P0EqzkaxGd4tUiPUSL15YBlsLLaSKc52Nsbpi0qpoNuydcuEP byyTAtSzZgRXzH/jSlvbv4NlHAFtDhiw9EWB7SDGVRz+H7f3GJsty45fDcW7zT7LTJLs M4qZrd7li1j/yMY6ibPP9oGn8Tt2gCRfbCJTfoAiWk1Cuim1yRsBMv2p8ybvXu3c65Po 0o0A2uVeTrSnUH0z2Bt6GaN2ZPLj/8VZ2SHdHb8TXYWAzCGCtv7yNKjjU/KqGuPm0lP6 bwlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WnwvmjTr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.21 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:12 -0700 Message-Id: <20190808202616.13782-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 3/7] target/arm: Remove redundant shift tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The immediate shift generator functions already test for, and eliminate, the case of a shift by zero. Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 94170af134..3ddc404b3b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8826,8 +8826,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) shift = (insn >> 10) & 3; /* ??? In many cases it's not necessary to do a rotate, a shift is sufficient. */ - if (shift != 0) - tcg_gen_rotri_i32(tmp, tmp, shift * 8); + tcg_gen_rotri_i32(tmp, tmp, shift * 8); op1 = (insn >> 20) & 7; switch (op1) { case 0: gen_sxtb16(tmp); break; @@ -9904,8 +9903,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) shift = (insn >> 4) & 3; /* ??? In many cases it's not necessary to do a rotate, a shift is sufficient. */ - if (shift != 0) - tcg_gen_rotri_i32(tmp, tmp, shift * 8); + tcg_gen_rotri_i32(tmp, tmp, shift * 8); op = (insn >> 20) & 7; switch (op) { case 0: gen_sxth(tmp); break; @@ -10632,11 +10630,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 7: goto illegal_op; default: /* Saturate. */ - if (shift) { - if (op & 1) - tcg_gen_sari_i32(tmp, tmp, shift); - else - tcg_gen_shli_i32(tmp, tmp, shift); + if (op & 1) { + tcg_gen_sari_i32(tmp, tmp, shift); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); } tmp2 = tcg_const_i32(imm); if (op & 4) { @@ -10827,9 +10824,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } tmp = load_reg(s, rm); - if (shift) { - tcg_gen_shli_i32(tmp, tmp, shift); - } + tcg_gen_shli_i32(tmp, tmp, shift); tcg_gen_add_i32(addr, addr, tmp); tcg_temp_free_i32(tmp); break; From patchwork Thu Aug 8 20:26:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 170831 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9059178ile; Thu, 8 Aug 2019 13:26:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqyxOnyXoUTG8F5s3bY+UJmFDWonRikypJlVf28/z4mZbT9EVKvSEHL0lpI88uxtvQcd5Tf+ X-Received: by 2002:a50:9263:: with SMTP id j32mr18047385eda.121.1565296000165; Thu, 08 Aug 2019 13:26:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565296000; cv=none; d=google.com; s=arc-20160816; b=x36Bmn3LUPo+s0jIs9bJGxlHjbrUwZhlGItCi4p9DVBcb3OxXTs6gOCSiMIKAwSzny hMr8M5sMococ/66tdxzxYgquAYKNrSGKW9nTVAkipfkKikm8FtgQYW1fPC731fuymT0S K0Z1qTL38K8zPIL6CqghMuLl67w30NrR70KO8Ki4sK2kH9Ym7ywGvpgZleEzdjTXAQ/e iJzTB9wodRsnRXtDCkfS987W7ROSZ1LRnfgfcFyHvvUaOnP8ZGdafad1sq7srJFQzu7/ lIZxSKmqBonmY29WrblA2QgjSkKlyruf6jMgMNIlla1HgB2q+bdat9LS2b2gaykOMkiq mX8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=nqzQU642U0COih1CmgjWbkQy5lirJcAcLB93HWWBZtw=; b=VICKV27nIwk7a7SmcXfoRoZ1Qrf6YNdOggq0oVki+O79FfHBnl8eig7WcmsHrGnfuN AacM5UnFrAjOMV5mFTxzLOVytsmIbLRVBIGt8DVJeTnpoX8w0C4rBSNRRSx1zBxr404I H4vplZ8XQ4MESh3qOCfBGIOCY2WPdjCU2WKzpGzOk2FmPYU+iqWeMaT2/RLZocb2R/sr wYVu5YTpfNLJwR3EP3wv2Gx34PhysUMcVxgVPZvv9pn8Bx+ICvQ1bqG7fjIwC9dXdwLg khnBewvO9kgwR4ngjXZ9r+nPAixJi1OaFC5U8P32a9Gnj7xsiYfRe9z/253Xt/y3kVSb 46gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=f4x3IifJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.22 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:13 -0700 Message-Id: <20190808202616.13782-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 4/7] target/arm: Use ror32 instead of open-coding the operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The helper function is more documentary, and also already handles the case of rotate by zero. Signed-off-by: Richard Henderson --- target/arm/translate.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3ddc404b3b..b40f163bab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7979,8 +7979,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* CPSR = immediate */ val = insn & 0xff; shift = ((insn >> 8) & 0xf) * 2; - if (shift) - val = (val >> shift) | (val << (32 - shift)); + val = ror32(val, shift); i = ((insn & (1 << 22)) != 0); if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), i, val)) { @@ -8243,9 +8242,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* immediate operand */ val = insn & 0xff; shift = ((insn >> 8) & 0xf) * 2; - if (shift) { - val = (val >> shift) | (val << (32 - shift)); - } + val = ror32(val, shift); tmp2 = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, val); if (logic_cc && shift) { From patchwork Thu Aug 8 20:26:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 170834 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9059469ile; Thu, 8 Aug 2019 13:26:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqzerxUK20ot29IFzy8wf61b7G8GQmLU+eTrexSDzCkvseuuZx7gWpZnhov+SLgBo3Bt+Yzo X-Received: by 2002:a17:906:a416:: with SMTP id l22mr1353617ejz.238.1565296018790; Thu, 08 Aug 2019 13:26:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565296018; cv=none; d=google.com; s=arc-20160816; b=zZNrYeSoDKORBQL4O3YfbIay6mibKKT4p/lGIOrrIDm6sRWKMSW+W5bJ6KTCIfhDTL 8wKkJU/7q+yOfN26sF+sWYZ8uxEFo0r0wqdfY5mAWSOtrjWf7vasK3QWW88iZ43AIz0c ppApAWwcMdmh9rhm6bhLSsZaZ555oaUBmdq+8sIPNkZbx8yRlK0RkerqRlpwzclWwZ3X D1dFjScmz3fJP3RIBj/lgyuBuJFT02kx07if6Of+B5sRHalgPgObATDGnaTKKECu7JZ8 2iolwCcfLNRM2REjvFmt+a7XNGBZziGTwRlAbRS3P62akxazM1O4hAPNjkxRtDWrev2k M+Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RskjHA12b+UCLX2htP8k3zX7fIXUBDlXhLLJAVERdC0=; b=SlqdYNI6P4ofbEYuM43FoJvxo1UthWasS0dEUgexwrN61vfIPj4l+XJrEzWqIwsB0f FsGtgU0/lulfwr/JhMSNLcNT0d4uhnLhJbiLdU8zwJd7hgrm1/4t5fDjUMDHmxsoKAhW XpYaFhHqWgh5s1Bnu4GwWtA/uaCVSdyB3K+AmVo0u5m1qyxeFNNLY5R/j3jD/6YEPIsI sfQDMBxYItCwcC5rBuNNJoiWl9piXXZpH9IAglCfAsd27qciiInWPFfWs6CER1j+ZiP2 g02zqT2jDQEH3+ii9myniO2WAqbTXUsS7B5tRRM/CokmAl3JwLxBq6q6yB3Jym8f2u4e zK2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AI5BNglK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.23 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:14 -0700 Message-Id: <20190808202616.13782-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 5/7] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rotate is the more compact and obvious way to swap 16-bit elements of a 32-bit word. Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b40f163bab..ddc54e77e4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -459,11 +459,7 @@ static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b) /* Swap low and high halfwords. */ static void gen_swap_half(TCGv_i32 var) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, var, 16); - tcg_gen_shli_i32(var, var, 16); - tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); + tcg_gen_rotri_i32(var, var, 16); } /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.25 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:15 -0700 Message-Id: <20190808202616.13782-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 6/7] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All of the inputs to these instructions are 32-bits. Rather than extend each input to 64-bits and then extract the high 32-bits of the output, use tcg_gen_muls2_i32 and other 32-bit generator functions. Signed-off-by: Richard Henderson --- target/arm/translate.c | 72 +++++++++++++++--------------------------- 1 file changed, 26 insertions(+), 46 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ddc54e77e4..77154be743 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -391,34 +391,6 @@ static void gen_revsh(TCGv_i32 var) tcg_gen_ext16s_i32(var, var); } -/* Return (b << 32) + a. Mark inputs as dead */ -static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b) -{ - TCGv_i64 tmp64 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(tmp64, b); - tcg_temp_free_i32(b); - tcg_gen_shli_i64(tmp64, tmp64, 32); - tcg_gen_add_i64(a, tmp64, a); - - tcg_temp_free_i64(tmp64); - return a; -} - -/* Return (b << 32) - a. Mark inputs as dead. */ -static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b) -{ - TCGv_i64 tmp64 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(tmp64, b); - tcg_temp_free_i32(b); - tcg_gen_shli_i64(tmp64, tmp64, 32); - tcg_gen_sub_i64(a, tmp64, a); - - tcg_temp_free_i64(tmp64); - return a; -} - /* 32x32->64 multiply. Marks inputs as dead. */ static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b) { @@ -8872,23 +8844,27 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) (SMMUL, SMMLA, SMMLS) */ tmp = load_reg(s, rm); tmp2 = load_reg(s, rs); - tmp64 = gen_muls_i64_i32(tmp, tmp2); + tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rd != 15) { - tmp = load_reg(s, rd); + tmp3 = load_reg(s, rd); if (insn & (1 << 6)) { - tmp64 = gen_subq_msw(tmp64, tmp); + tcg_gen_sub_i32(tmp, tmp, tmp3); } else { - tmp64 = gen_addq_msw(tmp64, tmp); + tcg_gen_add_i32(tmp, tmp, tmp3); } + tcg_temp_free_i32(tmp3); } if (insn & (1 << 5)) { - tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); + /* + * Adding 0x80000000 to the 64-bit quantity + * means that we have carry in to the high + * word when the low word has the high bit set. + */ + tcg_gen_shri_i32(tmp2, tmp2, 31); + tcg_gen_add_i32(tmp, tmp, tmp2); } - tcg_gen_shri_i64(tmp64, tmp64, 32); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); + tcg_temp_free_i32(tmp2); store_reg(s, rn, tmp); break; case 0: @@ -10114,22 +10090,26 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tmp64 = gen_muls_i64_i32(tmp, tmp2); + tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rs != 15) { - tmp = load_reg(s, rs); + tmp3 = load_reg(s, rs); if (insn & (1 << 20)) { - tmp64 = gen_addq_msw(tmp64, tmp); + tcg_gen_add_i32(tmp, tmp, tmp3); } else { - tmp64 = gen_subq_msw(tmp64, tmp); + tcg_gen_sub_i32(tmp, tmp, tmp3); } + tcg_temp_free_i32(tmp3); } if (insn & (1 << 4)) { - tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); + /* + * Adding 0x80000000 to the 64-bit quantity + * means that we have carry in to the high + * word when the low word has the high bit set. + */ + tcg_gen_shri_i32(tmp2, tmp2, 31); + tcg_gen_add_i32(tmp, tmp, tmp2); } - tcg_gen_shri_i64(tmp64, tmp64, 32); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); + tcg_temp_free_i32(tmp2); break; case 7: /* Unsigned sum of absolute differences. */ gen_helper_usad8(tmp, tmp, tmp2); From patchwork Thu Aug 8 20:26:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 170838 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp9061744ile; Thu, 8 Aug 2019 13:29:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzATmdkpWK/lctr/ZuxLKxb6Ii0hSPIL6RPTr3r0K4WRwOS3cIsjdJoHdZDI3fBA4zs4Bgj X-Received: by 2002:aa7:d64f:: with SMTP id v15mr18172931edr.132.1565296155143; Thu, 08 Aug 2019 13:29:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565296155; cv=none; d=google.com; s=arc-20160816; b=CFl4gy9v3CBxVz6JW1x4e11xnKhF7764F2WOkWQ6dmH8YaFtKRvF2yAOCTWXDCRHd0 OGVtbrC8ZChTpsJcDnLRZTOmMlZbtJ4xDnYma9aFfh+7wRw1kH+/Umm3xD9gPTXbvgiw nWN8Dt4VBajj84V9xgA6E5iAKaFJRv7EpuHYMsAsafOV3VBv7cABvq2+kj+nzN6t4kmH KcqQ4pPlZ+YuTkb3jWIMvlY094T2oYAD502meU44znP7PbcfUbq782p4OeFlrvlwLyga T+mUV7oGayGEM20EYiSwrE4VyrOq+m+MHgY3KrYiHT0i5YOpeawEkNnpLgZp4j7ICc1Y sKBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AcVFjfcusS5dLWT70g3h9t3XMQa4NwJ2WZoNCoEA3tk=; b=SyuaX/070mdsW4hAGIw6m0AI85K28SRgV6mlQPsCgwIXEi4SvXOXDKVn9YV1xB1Jlx H/BeW9LlzwLFxaChO8sRy1rt8R9fwblI7x1f8AB6cB/HKi/Mm7z0CEsBf4EHG8yiRjBk dSVkJjkPkreFoQh212i1oV+Q00NVD7tkqM8v4uGAKvrO4Wk7blMu+lI+szO/MwgJ4XW6 Z6XO6Sjpv8OnZuG0Fv5CPIXwSMF4xxZTYXjoFT+8MsHsboOUrEm57WY8VzG4mFc3pRxn Q+M0+5gYiQQsVQbsVJFRUlkZaLvslj3q/mUxh2o7gPwdj7N/38tyfbl+mQRyp5fV+S2x E0EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zTL5AmxU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.26 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:16 -0700 Message-Id: <20190808202616.13782-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 7/7] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Separate shift + extract low will result in one extra insn for hosts like RISC-V, MIPS, and Sparc. Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 77154be743..9e103e4fad 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1761,8 +1761,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) if (insn & ARM_CP_RW_BIT) { /* TMRRC */ iwmmxt_load_reg(cpu_V0, wrd); tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); - tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0); + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); } else { /* TMCRR */ tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); iwmmxt_store_reg(cpu_V0, wrd); @@ -2807,8 +2806,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) if (insn & ARM_CP_RW_BIT) { /* MRA */ iwmmxt_load_reg(cpu_V0, acc); tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); - tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0); + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1); } else { /* MAR */ tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); @@ -6005,8 +6003,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) gen_helper_neon_narrow_high_u16(tmp, cpu_V0); break; case 2: - tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); - tcg_gen_extrl_i64_i32(tmp, cpu_V0); + tcg_gen_extrh_i64_i32(tmp, cpu_V0); break; default: abort(); } @@ -6020,8 +6017,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) break; case 2: tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31); - tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); - tcg_gen_extrl_i64_i32(tmp, cpu_V0); + tcg_gen_extrh_i64_i32(tmp, cpu_V0); break; default: abort(); } @@ -7254,9 +7250,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) tmp = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(tmp, tmp64); store_reg(s, rt, tmp); - tcg_gen_shri_i64(tmp64, tmp64, 32); tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); + tcg_gen_extrh_i64_i32(tmp, tmp64); tcg_temp_free_i64(tmp64); store_reg(s, rt2, tmp); } else { @@ -7365,8 +7360,7 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) tcg_gen_extrl_i64_i32(tmp, val); store_reg(s, rlow, tmp); tmp = tcg_temp_new_i32(); - tcg_gen_shri_i64(val, val, 32); - tcg_gen_extrl_i64_i32(tmp, val); + tcg_gen_extrh_i64_i32(tmp, val); store_reg(s, rhigh, tmp); }