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[209.132.180.67]) by mx.google.com with ESMTP id k72si54589669pge.95.2019.08.08.05.32.54; Thu, 08 Aug 2019 05:32:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y4bogs4w; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389946AbfHHMcy (ORCPT + 5 others); Thu, 8 Aug 2019 08:32:54 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:43590 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389844AbfHHMcx (ORCPT ); Thu, 8 Aug 2019 08:32:53 -0400 Received: by mail-lf1-f67.google.com with SMTP id c19so66722248lfm.10 for ; Thu, 08 Aug 2019 05:32:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+8tfM/JArjChSabxtDC9UnR99CKTRNqVrNVadN2+Zpg=; b=y4bogs4w5cdyFiV0Q81uwTndTFt7Ruiw4lOBUZBn4ZRqdJ81AovXdxjR6+Q7IG4p5h VBawsd5swh/Hd44FRwHfedPKaJY2k6ZhnHEoaFDU5n5GlPpw0aaDsZ82xxE7aK6KSviE bHl4sNgNGvkzncYLQFGwHeaUzn8Ivvc4iWtRF9g+c0m8ICBksxmJRcMSERZi2J1kY8z5 Iv2LPtRA7RpJA+8M/8u66Aw8V22R4EzfMLRHgPC9h5a4nLqHRXNAudxMBcS359GLSwZu QaEbptpINNUn7C8f9ccR42RKqCwJ4HT44VdAB4nIBCJqIfrbUaCga/KO/BhPuzGi86cb YB2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+8tfM/JArjChSabxtDC9UnR99CKTRNqVrNVadN2+Zpg=; b=rQLBDKNbbeFKlFVuyLopCeNDabtKvpogQK0EsqfHiTQricSnD6e2sY7wGkqtTPOZsJ w6F3dYHOe3aMlE4vZLl1DAJmKYeg9TIO3VclwBJ2Ld82mpYq93e2BIH15Kg5I9HLQ87T EPdHUNEqcTSR9TheJNl0LuTUAW/PCsZPYiNtuptBQ3zp3R8OinI0jlOWlhy0eExLka/9 H3U4bmM9avwNj510tK7nx3M6VuY5ypo/kBFwZw6IEg5hvnQQXeewf5S9y1xt4fCKi7Uo yE3uO/iLy8xWIywnmOgYa6j7Ofr/BvuVhnLhT1g1QvyRT2vGK5K9GgWJS4yYGV+68yer fHEg== X-Gm-Message-State: APjAAAWvmZePguaOmiNXJKnN3QxduafFq9yV8GmcWIrhIgOw9EKgRTDZ rRcc/v1CRRZO/NHYN2X6lmt4DlAXnEQ= X-Received: by 2002:ac2:43bc:: with SMTP id t28mr9567414lfl.14.1565267570810; Thu, 08 Aug 2019 05:32:50 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h10sm16976423lfp.33.2019.08.08.05.32.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 05:32:49 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Thomas Gleixner , Marc Zyngier , Lina Iyer , Jon Hunter , Sowjanya Komatineni , Bitan Biswas , linux-tegra@vger.kernel.org, David Daney , Masahiro Yamada , Brian Masney , Thierry Reding Subject: [PATCH 1/6 v2] gpio: Add support for hierarchical IRQ domains Date: Thu, 8 Aug 2019 14:32:37 +0200 Message-Id: <20190808123242.5359-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hierarchical IRQ domains can be used to stack different IRQ controllers on top of each other. Bring hierarchical IRQ domains into the GPIOLIB core with the following basic idea: Drivers that need their interrupts handled hierarchically specify a callback to translate the child hardware IRQ and IRQ type for each GPIO offset to a parent hardware IRQ and parent hardware IRQ type. Users have to pass the callback, fwnode, and parent irqdomain before calling gpiochip_irqchip_add(). We use the new method of just filling in the struct gpio_irq_chip before adding the gpiochip for all hierarchical irqchips of this type. The code path for device tree is pretty straight-forward, while the code path for old boardfiles or anything else will be more convoluted requireing upfront allocation of the interrupts when adding the chip. One specific use-case where this can be useful is if a power management controller has top-level controls for wakeup interrupts. In such cases, the power management controller can be a parent to other interrupt controllers and program additional registers when an IRQ has its wake capability enabled or disabled. The hierarchical irqchip helper code will only be available when IRQ_DOMAIN_HIERARCHY is selected to GPIO chips using this should select or depend on that symbol. When using hierarchical IRQs, the parent interrupt controller must also be hierarchical all the way up to the top interrupt controller wireing directly into the CPU, so on systems that do not have this we can get rid of all the extra code for supporting hierarchical irqs. Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Lina Iyer Cc: Jon Hunter Cc: Sowjanya Komatineni Cc: Bitan Biswas Cc: linux-tegra@vger.kernel.org Cc: David Daney Cc: Masahiro Yamada Cc: Brian Masney Signed-off-by: Thierry Reding Signed-off-by: Brian Masney Co-developed-by: Brian Masney Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Squash in changes contributed by Brian Masney to support customization and solve some bugs. - Add gpiochip_populate_parent_fwspec_{two,four}cell functions so that irqchips using four cells can use this code. - Pass girq->handler to the domain as default handler: there are apparently cases where handle_bad_irq will not quite cut it. - Change "child_pin_to_irq" into "child_offset_to_irq" so we avoid confusion with pin control. - Diet down the parent domain presence checks, one time is enough to check it. - Change domain allocation error to -ENOMEM and do not print errors. - Diet some chip_info() blather. - Assume nr_irqs to be 1 in .translate() and warn if not. ChangeLog RFC->v1: - Tested on real hardware - Incorporate Thierry's idea to have a translation callback. He was right about this approach, I was wrong in insisting on IRQ maps. --- Documentation/driver-api/gpio/driver.rst | 122 ++++++++- drivers/gpio/gpiolib.c | 318 ++++++++++++++++++++++- include/linux/gpio/driver.h | 111 ++++++++ 3 files changed, 525 insertions(+), 26 deletions(-) -- 2.21.0 diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst index 921c71a3d683..5e96dbc7f4e7 100644 --- a/Documentation/driver-api/gpio/driver.rst +++ b/Documentation/driver-api/gpio/driver.rst @@ -259,7 +259,7 @@ most often cascaded off a parent interrupt controller, and in some special cases the GPIO logic is melded with a SoC's primary interrupt controller. The IRQ portions of the GPIO block are implemented using an irq_chip, using -the header . So basically such a driver is utilizing two sub- +the header . So this combined driver is utilizing two sub- systems simultaneously: gpio and irq. It is legal for any IRQ consumer to request an IRQ from any irqchip even if it @@ -391,25 +391,119 @@ Infrastructure helpers for GPIO irqchips ---------------------------------------- To help out in handling the set-up and management of GPIO irqchips and the -associated irqdomain and resource allocation callbacks, the gpiolib has -some helpers that can be enabled by selecting the GPIOLIB_IRQCHIP Kconfig -symbol: - -- gpiochip_irqchip_add(): adds a chained cascaded irqchip to a gpiochip. It - will pass the struct gpio_chip* for the chip to all IRQ callbacks, so the - callbacks need to embed the gpio_chip in its state container and obtain a - pointer to the container using container_of(). - (See Documentation/driver-api/driver-model/design-patterns.rst) +associated irqdomain and resource allocation callbacks. These are activated +by selecting the Kconfig symbol GPIOLIB_IRQCHIP. If the symbol +IRQ_DOMAIN_HIERARCHY is also selected, hierarchical helpers will also be +provided. A big portion of overhead code will be managed by gpiolib, +under the assumption that your interrupts are 1-to-1-mapped to the +GPIO line index: + + GPIO line offset Hardware IRQ + 0 0 + 1 1 + 2 2 + ... ... + ngpio-1 ngpio-1 + +If some GPIO lines do not have corresponding IRQs, the bitmask valid_mask +and the flag need_valid_mask in gpio_irq_chip can be used to mask off some +lines as invalid for associating with IRQs. + +The preferred way to set up the helpers is to fill in the +struct gpio_irq_chip inside struct gpio_chip before adding the gpio_chip. +If you do this, the additional irq_chip will be set up by gpiolib at the +same time as setting up the rest of the GPIO functionality. The following +is a typical example of a cascaded interrupt handler using gpio_irq_chip: + + /* Typical state container with dynamic irqchip */ + struct my_gpio { + struct gpio_chip gc; + struct irq_chip irq; + }; + + int irq; /* from platform etc */ + struct my_gpio *g; + struct gpio_irq_chip *girq; + + /* Set up the irqchip dynamically */ + g->irq.name = "my_gpio_irq"; + g->irq.irq_ack = my_gpio_ack_irq; + g->irq.irq_mask = my_gpio_mask_irq; + g->irq.irq_unmask = my_gpio_unmask_irq; + g->irq.irq_set_type = my_gpio_set_irq_type; + + /* Get a pointer to the gpio_irq_chip */ + girq = &g->gc.irq; + girq->chip = &g->irq; + girq->parent_handler = ftgpio_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->parents[0] = irq; + + return devm_gpiochip_add_data(dev, &g->gc, g); + +The helper support using hierarchical interrupt controllers as well. +In this case the typical set-up will look like this: + + /* Typical state container with dynamic irqchip */ + struct my_gpio { + struct gpio_chip gc; + struct irq_chip irq; + struct fwnode_handle *fwnode; + }; + + int irq; /* from platform etc */ + struct my_gpio *g; + struct gpio_irq_chip *girq; + + /* Set up the irqchip dynamically */ + g->irq.name = "my_gpio_irq"; + g->irq.irq_ack = my_gpio_ack_irq; + g->irq.irq_mask = my_gpio_mask_irq; + g->irq.irq_unmask = my_gpio_unmask_irq; + g->irq.irq_set_type = my_gpio_set_irq_type; + + /* Get a pointer to the gpio_irq_chip */ + girq = &g->gc.irq; + girq->chip = &g->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->fwnode = g->fwnode; + girq->parent_domain = parent; + girq->child_to_parent_hwirq = my_gpio_child_to_parent_hwirq; + + return devm_gpiochip_add_data(dev, &g->gc, g); + +As you can see pretty similar, but you do not supply a parent handler for +the IRQ, instead a parent irqdomain, an fwnode for the hardware and +a funcion .child_to_parent_hwirq() that has the purpose of looking up +the parent hardware irq from a child (i.e. this gpio chip) hardware irq. +As always it is good to look at examples in the kernel tree for advice +on how to find the required pieces. + +The old way of adding irqchips to gpiochips after registration is also still +available but we try to move away from this: + +- DEPRECATED: gpiochip_irqchip_add(): adds a chained cascaded irqchip to a + gpiochip. It will pass the struct gpio_chip* for the chip to all IRQ + callbacks, so the callbacks need to embed the gpio_chip in its state + container and obtain a pointer to the container using container_of(). + (See Documentation/driver-model/design-patterns.txt) - gpiochip_irqchip_add_nested(): adds a nested cascaded irqchip to a gpiochip, as discussed above regarding different types of cascaded irqchips. The cascaded irq has to be handled by a threaded interrupt handler. Apart from that it works exactly like the chained irqchip. -- gpiochip_set_chained_irqchip(): sets up a chained cascaded irq handler for a - gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler - data. Notice that we pass is as the handler data, since the irqchip data is - likely used by the parent irqchip. +- DEPRECATED: gpiochip_set_chained_irqchip(): sets up a chained cascaded irq + handler for a gpio_chip from a parent IRQ and passes the struct gpio_chip* + as handler data. Notice that we pass is as the handler data, since the + irqchip data is likely used by the parent irqchip. - gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a gpio_chip from a parent IRQ. As the parent IRQ has usually been diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 537a37a89891..4a71a58ce47f 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1720,6 +1720,273 @@ void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip, } EXPORT_SYMBOL_GPL(gpiochip_set_nested_irqchip); +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY + +/** + * gpiochip_set_hierarchical_irqchip() - connects a hierarchical irqchip + * to a gpiochip + * @gc: the gpiochip to set the irqchip hierarchical handler to + * @irqchip: the irqchip to handle this level of the hierarchy, the interrupt + * will then percolate up to the parent + */ +static void gpiochip_set_hierarchical_irqchip(struct gpio_chip *gc, + struct irq_chip *irqchip) +{ + /* DT will deal with mapping each IRQ as we go along */ + if (is_of_node(gc->irq.fwnode)) + return; + + /* + * This is for legacy and boardfile "irqchip" fwnodes: allocate + * irqs upfront instead of dynamically since we don't have the + * dynamic type of allocation that hardware description languages + * provide. Once all GPIO drivers using board files are gone from + * the kernel we can delete this code, but for a transitional period + * it is necessary to keep this around. + */ + if (is_fwnode_irqchip(gc->irq.fwnode)) { + int i; + int ret; + + for (i = 0; i < gc->ngpio; i++) { + struct irq_fwspec fwspec; + unsigned int parent_hwirq; + unsigned int parent_type; + struct gpio_irq_chip *girq = &gc->irq; + + /* + * We call the child to parent translation function + * only to check if the child IRQ is valid or not. + * Just pick the rising edge type here as that is what + * we likely need to support. + */ + ret = girq->child_to_parent_hwirq(gc, i, + IRQ_TYPE_EDGE_RISING, + &parent_hwirq, + &parent_type); + if (ret) { + chip_err(gc, "skip set-up on hwirq %d\n", + i); + continue; + } + + fwspec.fwnode = gc->irq.fwnode; + /* This is the hwirq for the GPIO line side of things */ + fwspec.param[0] = girq->child_offset_to_irq(gc, i); + /* Just pick something */ + fwspec.param[1] = IRQ_TYPE_EDGE_RISING; + fwspec.param_count = 2; + ret = __irq_domain_alloc_irqs(gc->irq.domain, + /* just pick something */ + -1, + 1, + NUMA_NO_NODE, + &fwspec, + false, + NULL); + if (ret < 0) { + chip_err(gc, + "can not allocate irq for GPIO line %d parent hwirq %d in hierarchy domain: %d\n", + i, parent_hwirq, + ret); + } + } + } + + chip_err(gc, "%s unknown fwnode type proceed anyway\n", __func__); + + return; +} + +static int gpiochip_hierarchy_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + /* We support standard DT translation */ + if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { + return irq_domain_translate_twocell(d, fwspec, hwirq, type); + } + + /* This is for board files and others not using DT */ + if (is_fwnode_irqchip(fwspec->fwnode)) { + int ret; + + ret = irq_domain_translate_twocell(d, fwspec, hwirq, type); + if (ret) + return ret; + WARN_ON(*type == IRQ_TYPE_NONE); + return 0; + } + return -EINVAL; +} + +static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d, + unsigned int irq, + unsigned int nr_irqs, + void *data) +{ + struct gpio_chip *gc = d->host_data; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + unsigned int parent_hwirq; + unsigned int parent_type; + struct gpio_irq_chip *girq = &gc->irq; + int ret; + + /* + * The nr_irqs parameter is always one except for PCI multi-MSI + * so this should not happen. + */ + WARN_ON(nr_irqs != 1); + + ret = gc->irq.child_irq_domain_ops.translate(d, fwspec, &hwirq, &type); + if (ret) + return ret; + + chip_info(gc, "allocate IRQ %d, hwirq %lu\n", irq, hwirq); + + ret = girq->child_to_parent_hwirq(gc, hwirq, type, + &parent_hwirq, &parent_type); + if (ret) { + chip_err(gc, "can't look up hwirq %lu\n", hwirq); + return ret; + } + chip_info(gc, "found parent hwirq %u\n", parent_hwirq); + + /* + * We set handle_bad_irq because the .set_type() should + * always be invoked and set the right type of handler. + */ + irq_domain_set_info(d, + irq, + hwirq, + gc->irq.chip, + gc, + girq->handler, + NULL, NULL); + irq_set_probe(irq); + + /* + * Create a IRQ fwspec to send up to the parent irqdomain: + * specify the hwirq we address on the parent and tie it + * all together up the chain. + */ + parent_fwspec.fwnode = d->parent->fwnode; + /* This parent only handles asserted level IRQs */ + girq->populate_parent_fwspec(gc, &parent_fwspec, parent_hwirq, + parent_type); + chip_info(gc, "alloc_irqs_parent for %d parent hwirq %d\n", + irq, parent_hwirq); + ret = irq_domain_alloc_irqs_parent(d, irq, 1, &parent_fwspec); + if (ret) + chip_err(gc, + "failed to allocate parent hwirq %d for hwirq %lu\n", + parent_hwirq, hwirq); + + return ret; +} + +static unsigned int gpiochip_child_offset_to_irq_noop(struct gpio_chip *chip, + unsigned int offset) +{ + return offset; +} + +static void gpiochip_hierarchy_setup_domain_ops(struct irq_domain_ops *ops) +{ + ops->activate = gpiochip_irq_domain_activate; + ops->deactivate = gpiochip_irq_domain_deactivate; + ops->alloc = gpiochip_hierarchy_irq_domain_alloc; + ops->free = irq_domain_free_irqs_common; + + /* + * We only allow overriding the translate() function for + * hierarchical chips, and this should only be done if the user + * really need something other than 1:1 translation. + */ + if (!ops->translate) + ops->translate = gpiochip_hierarchy_irq_domain_translate; +} + +static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc) +{ + if (!gc->irq.child_to_parent_hwirq || + !gc->irq.fwnode) { + chip_err(gc, "missing irqdomain vital data\n"); + return -EINVAL; + } + + if (!gc->irq.child_offset_to_irq) + gc->irq.child_offset_to_irq = gpiochip_child_offset_to_irq_noop; + + if (!gc->irq.populate_parent_fwspec) + gc->irq.populate_parent_fwspec = + gpiochip_populate_parent_fwspec_twocell; + + gpiochip_hierarchy_setup_domain_ops(&gc->irq.child_irq_domain_ops); + + gc->irq.domain = irq_domain_create_hierarchy( + gc->irq.parent_domain, + 0, + gc->ngpio, + gc->irq.fwnode, + &gc->irq.child_irq_domain_ops, + gc); + + if (!gc->irq.domain) + return -ENOMEM; + + gpiochip_set_hierarchical_irqchip(gc, gc->irq.chip); + + return 0; +} + +static bool gpiochip_hierarchy_is_hierarchical(struct gpio_chip *gc) +{ + return !!gc->irq.parent_domain; +} + +void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + fwspec->param_count = 2; + fwspec->param[0] = parent_hwirq; + fwspec->param[1] = parent_type; +} +EXPORT_SYMBOL_GPL(gpiochip_populate_parent_fwspec_twocell); + +void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + fwspec->param_count = 4; + fwspec->param[0] = 0; + fwspec->param[1] = parent_hwirq; + fwspec->param[2] = 0; + fwspec->param[3] = parent_type; +} +EXPORT_SYMBOL_GPL(gpiochip_populate_parent_fwspec_fourcell); + +#else + +static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc) +{ + return -EINVAL; +} + +static bool gpiochip_hierarchy_is_hierarchical(struct gpio_chip *gc) +{ + return false; +} + +#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ + /** * gpiochip_irq_map() - maps an IRQ into a GPIO irqchip * @d: the irqdomain used by this irqchip @@ -1788,6 +2055,11 @@ static const struct irq_domain_ops gpiochip_domain_ops = { .xlate = irq_domain_xlate_twocell, }; +/* + * TODO: move these activate/deactivate in under the hierarchicial + * irqchip implementation as static once SPMI and SSBI (all external + * users) are phased over. + */ /** * gpiochip_irq_domain_activate() - Lock a GPIO to be used as an IRQ * @domain: The IRQ domain used by this IRQ chip @@ -1827,10 +2099,23 @@ EXPORT_SYMBOL_GPL(gpiochip_irq_domain_deactivate); static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset) { + struct irq_domain *domain = chip->irq.domain; + if (!gpiochip_irqchip_irq_valid(chip, offset)) return -ENXIO; - return irq_create_mapping(chip->irq.domain, offset); + if (irq_domain_is_hierarchy(domain)) { + struct irq_fwspec spec; + + spec.fwnode = domain->fwnode; + spec.param_count = 2; + spec.param[0] = chip->irq.child_offset_to_irq(chip, offset); + spec.param[1] = IRQ_TYPE_NONE; + + return irq_create_fwspec_mapping(&spec); + } + + return irq_create_mapping(domain, offset); } static int gpiochip_irq_reqres(struct irq_data *d) @@ -1907,7 +2192,7 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, struct lock_class_key *request_key) { struct irq_chip *irqchip = gpiochip->irq.chip; - const struct irq_domain_ops *ops; + const struct irq_domain_ops *ops = NULL; struct device_node *np; unsigned int type; unsigned int i; @@ -1943,16 +2228,25 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip, gpiochip->irq.lock_key = lock_key; gpiochip->irq.request_key = request_key; - if (gpiochip->irq.domain_ops) - ops = gpiochip->irq.domain_ops; - else - ops = &gpiochip_domain_ops; - - gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio, - gpiochip->irq.first, - ops, gpiochip); - if (!gpiochip->irq.domain) - return -EINVAL; + /* If a parent irqdomain is provided, let's build a hierarchy */ + if (gpiochip_hierarchy_is_hierarchical(gpiochip)) { + int ret = gpiochip_hierarchy_add_domain(gpiochip); + if (ret) + return ret; + } else { + /* Some drivers provide custom irqdomain ops */ + if (gpiochip->irq.domain_ops) + ops = gpiochip->irq.domain_ops; + + if (!ops) + ops = &gpiochip_domain_ops; + gpiochip->irq.domain = irq_domain_add_simple(np, + gpiochip->ngpio, + gpiochip->irq.first, + ops, gpiochip); + if (!gpiochip->irq.domain) + return -EINVAL; + } if (gpiochip->irq.parent_handler) { void *data = gpiochip->irq.parent_handler_data ?: gpiochip; diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 6a0e420915a3..0e6d3b0c0211 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -23,6 +23,9 @@ enum gpio_lookup_flags; #ifdef CONFIG_GPIOLIB #ifdef CONFIG_GPIOLIB_IRQCHIP + +struct gpio_chip; + /** * struct gpio_irq_chip - GPIO interrupt controller */ @@ -49,6 +52,84 @@ struct gpio_irq_chip { */ const struct irq_domain_ops *domain_ops; +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY + /** + * @fwnode: + * + * Firmware node corresponding to this gpiochip/irqchip, necessary + * for hierarchical irqdomain support. + */ + struct fwnode_handle *fwnode; + + /** + * @parent_domain: + * + * If non-NULL, will be set as the parent of this GPIO interrupt + * controller's IRQ domain to establish a hierarchical interrupt + * domain. The presence of this will activate the hierarchical + * interrupt support. + */ + struct irq_domain *parent_domain; + + /** + * @child_to_parent_hwirq: + * + * This callback translates a child hardware IRQ offset to a parent + * hardware IRQ offset on a hierarchical interrupt chip. The child + * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the + * ngpio field of struct gpio_chip) and the corresponding parent + * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by + * the driver. The driver can calculate this from an offset or using + * a lookup table or whatever method is best for this chip. Return + * 0 on successful translation in the driver. + * + * If some ranges of hardware IRQs do not have a corresponding parent + * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and + * @need_valid_mask to make these GPIO lines unavailable for + * translation. + */ + int (*child_to_parent_hwirq)(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type); + + /** + * @populate_parent_fwspec: + * + * This optional callback populates the &struct irq_fwspec for the + * parent's IRQ domain. If this is not specified, then + * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell + * variant named &gpiochip_populate_parent_fwspec_fourcell is also + * available. + */ + void (*populate_parent_fwspec)(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type); + + /** + * @child_offset_to_irq: + * + * This optional callback is used to translate the child's GPIO line + * offset on the GPIO chip to an IRQ number for the GPIO to_irq() + * callback. If this is not specified, then a default callback will be + * provided that returns the line offset. + */ + unsigned int (*child_offset_to_irq)(struct gpio_chip *chip, + unsigned int pin); + + /** + * @child_irq_domain_ops: + * + * The IRQ domain operations that will be used for this GPIO IRQ + * chip. If no operations are provided, then default callbacks will + * be populated to setup the IRQ hierarchy. Some drivers need to + * supply their own translate function. + */ + struct irq_domain_ops child_irq_domain_ops; +#endif + /** * @handler: * @@ -449,6 +530,36 @@ struct bgpio_pdata { int ngpio; }; +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY + +void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type); +void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type); + +#else + +static void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type) +{ +} + +static void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip, + struct irq_fwspec *fwspec, + unsigned int parent_hwirq, + unsigned int parent_type) +{ +} + +#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ + + #if IS_ENABLED(CONFIG_GPIO_GENERIC) int bgpio_init(struct gpio_chip *gc, struct device *dev, From patchwork Thu Aug 8 12:32:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 170799 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp8510237ile; Thu, 8 Aug 2019 05:32:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqyZBFAV8m7MqTgpWv64Xu68B6krzoBV4UKkPXdUj066r018m81djBL6vKlUuPswa/c4xw1R X-Received: by 2002:a17:902:7288:: with SMTP id d8mr13556405pll.133.1565267577428; Thu, 08 Aug 2019 05:32:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565267577; cv=none; d=google.com; s=arc-20160816; b=K3feT6Rmi+UQ0H2Ue4/2xYtT52qnaEZM8KQ5QBvlSWd+uNmM9cnh0Amn5uYl8jxgf4 atv7TqSRdt67l/DoV/97Vz5eNeHiuQebsj5d1wxM5bXPcAyvPVlaIWeVOORDC7VfzfIx FVdC8tdGdLRBpzB0paF5iJdt42+DYg9SvHJqa8hPyMBf9b457Hst5KmcTgDUH9xCx0b2 Pt8vvUO/MoaeUj/PWkf/K0BveL3GtTzYktObQgUcW17wREA7mk1txR5PT5wiqnXznpes BEy00DsgwWjQa+JuhWLvtKyDExny75IcEzeqfp6sHT5COiGVxScefYWvnC1jaGAk5EON BctA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6apXi9bxastQPRf4tD07ZdOY58lc4FwfFcFzaouGZIw=; b=Lb0ZbPRODnX2ukGA2E19N0uePbX4/9MExUJuhoxGtx4KRuDwPNZPWjOJUmZwaOapeG Y/BiEMF7Iv7cNn0bABqBjaXqXYIaNQ1GIYDNQIQwH/Yzw4f3xncxdxVBSXX25Un8Rbrx JlNnl9YXwVA/7d6vQwE3Fa82P9LbrOW0kVk+dKX6ls5ae0KHi6EXFB2mYDCKMoVBsQSM OXGdQyxMJ34fiNCWkjyRgvsTPNGigkiw+Oxyia+fKbOp+hR0A6+sczH6v5FDxHRrQyG/ +A35LvdN/++uanj07XRxwDEEBs4YwPUONb3ASIBrghbWXShsr7WgAp3Tf8a4MDJyRTtz V5HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MMIx0Get; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This pulls the majority of the code out of the driver and use the generic code in gpiolib. Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Lina Iyer Cc: Jon Hunter Cc: Sowjanya Komatineni Cc: Bitan Biswas Cc: linux-tegra@vger.kernel.org Cc: Thierry Reding Cc: Brian Masney Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Rebased. ChangeLog RFC->v1: - Fixed some bugs in dereferencing the gpio_chip first from the irqchip data, then dereference the local state container from the gpio_chip - Adapted to changes in the core patch like provide as translation callback rather than a table. - Tested on the Linksys NSLU2 and works like a charm --- drivers/gpio/Kconfig | 2 +- drivers/gpio/gpio-ixp4xx.c | 277 +++++++++---------------------------- 2 files changed, 63 insertions(+), 216 deletions(-) -- 2.21.0 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bb13c266c329..b34e9b11a7ef 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -288,7 +288,7 @@ config GPIO_IXP4XX depends on ARM # For depends on ARCH_IXP4XX select GPIO_GENERIC - select IRQ_DOMAIN + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY help Say yes here to support the GPIO functionality of a number of Intel diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index 670c2a85a35b..8bd23e80c61f 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c @@ -47,7 +47,6 @@ * @dev: containing device for this instance * @fwnode: the fwnode for this GPIO chip * @gc: gpiochip for this instance - * @domain: irqdomain for this chip instance * @base: remapped I/O-memory base * @irq_edge: Each bit represents an IRQ: 1: edge-triggered, * 0: level triggered @@ -56,48 +55,22 @@ struct ixp4xx_gpio { struct device *dev; struct fwnode_handle *fwnode; struct gpio_chip gc; - struct irq_domain *domain; void __iomem *base; unsigned long long irq_edge; }; -/** - * struct ixp4xx_gpio_map - IXP4 GPIO to parent IRQ map - * @gpio_offset: offset of the IXP4 GPIO line - * @parent_hwirq: hwirq on the parent IRQ controller - */ -struct ixp4xx_gpio_map { - int gpio_offset; - int parent_hwirq; -}; - -/* GPIO lines 0..12 have corresponding IRQs, GPIOs 13..15 have no IRQs */ -const struct ixp4xx_gpio_map ixp4xx_gpiomap[] = { - { .gpio_offset = 0, .parent_hwirq = 6 }, - { .gpio_offset = 1, .parent_hwirq = 7 }, - { .gpio_offset = 2, .parent_hwirq = 19 }, - { .gpio_offset = 3, .parent_hwirq = 20 }, - { .gpio_offset = 4, .parent_hwirq = 21 }, - { .gpio_offset = 5, .parent_hwirq = 22 }, - { .gpio_offset = 6, .parent_hwirq = 23 }, - { .gpio_offset = 7, .parent_hwirq = 24 }, - { .gpio_offset = 8, .parent_hwirq = 25 }, - { .gpio_offset = 9, .parent_hwirq = 26 }, - { .gpio_offset = 10, .parent_hwirq = 27 }, - { .gpio_offset = 11, .parent_hwirq = 28 }, - { .gpio_offset = 12, .parent_hwirq = 29 }, -}; - static void ixp4xx_gpio_irq_ack(struct irq_data *d) { - struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ixp4xx_gpio *g = gpiochip_get_data(gc); __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); } static void ixp4xx_gpio_irq_unmask(struct irq_data *d) { - struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ixp4xx_gpio *g = gpiochip_get_data(gc); /* ACK when unmasking if not edge-triggered */ if (!(g->irq_edge & BIT(d->hwirq))) @@ -108,7 +81,8 @@ static void ixp4xx_gpio_irq_unmask(struct irq_data *d) static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ixp4xx_gpio *g = gpiochip_get_data(gc); int line = d->hwirq; unsigned long flags; u32 int_style; @@ -187,122 +161,31 @@ static struct irq_chip ixp4xx_gpio_irqchip = { .irq_set_type = ixp4xx_gpio_irq_set_type, }; -static int ixp4xx_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) -{ - struct ixp4xx_gpio *g = gpiochip_get_data(gc); - struct irq_fwspec fwspec; - - fwspec.fwnode = g->fwnode; - fwspec.param_count = 2; - fwspec.param[0] = offset; - fwspec.param[1] = IRQ_TYPE_NONE; - - return irq_create_fwspec_mapping(&fwspec); -} - -static int ixp4xx_gpio_irq_domain_translate(struct irq_domain *domain, - struct irq_fwspec *fwspec, - unsigned long *hwirq, - unsigned int *type) +static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) { - int ret; + /* All these interrupts are level high in the CPU */ + *parent_type = IRQ_TYPE_LEVEL_HIGH; - /* We support standard DT translation */ - if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { - return irq_domain_translate_twocell(domain, fwspec, - hwirq, type); + /* GPIO lines 0..12 have dedicated IRQs */ + if (child == 0) { + *parent = 6; + return 0; } - - /* This goes away when we transition to DT */ - if (is_fwnode_irqchip(fwspec->fwnode)) { - ret = irq_domain_translate_twocell(domain, fwspec, - hwirq, type); - if (ret) - return ret; - WARN_ON(*type == IRQ_TYPE_NONE); + if (child == 1) { + *parent = 7; return 0; } - return -EINVAL; -} - -static int ixp4xx_gpio_irq_domain_alloc(struct irq_domain *d, - unsigned int irq, unsigned int nr_irqs, - void *data) -{ - struct ixp4xx_gpio *g = d->host_data; - irq_hw_number_t hwirq; - unsigned int type = IRQ_TYPE_NONE; - struct irq_fwspec *fwspec = data; - int ret; - int i; - - ret = ixp4xx_gpio_irq_domain_translate(d, fwspec, &hwirq, &type); - if (ret) - return ret; - - dev_dbg(g->dev, "allocate IRQ %d..%d, hwirq %lu..%lu\n", - irq, irq + nr_irqs - 1, - hwirq, hwirq + nr_irqs - 1); - - for (i = 0; i < nr_irqs; i++) { - struct irq_fwspec parent_fwspec; - const struct ixp4xx_gpio_map *map; - int j; - - /* Not all lines support IRQs */ - for (j = 0; j < ARRAY_SIZE(ixp4xx_gpiomap); j++) { - map = &ixp4xx_gpiomap[j]; - if (map->gpio_offset == hwirq) - break; - } - if (j == ARRAY_SIZE(ixp4xx_gpiomap)) { - dev_err(g->dev, "can't look up hwirq %lu\n", hwirq); - return -EINVAL; - } - dev_dbg(g->dev, "found parent hwirq %u\n", map->parent_hwirq); - - /* - * We set handle_bad_irq because the .set_type() should - * always be invoked and set the right type of handler. - */ - irq_domain_set_info(d, - irq + i, - hwirq + i, - &ixp4xx_gpio_irqchip, - g, - handle_bad_irq, - NULL, NULL); - irq_set_probe(irq + i); - - /* - * Create a IRQ fwspec to send up to the parent irqdomain: - * specify the hwirq we address on the parent and tie it - * all together up the chain. - */ - parent_fwspec.fwnode = d->parent->fwnode; - parent_fwspec.param_count = 2; - parent_fwspec.param[0] = map->parent_hwirq; - /* This parent only handles asserted level IRQs */ - parent_fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; - dev_dbg(g->dev, "alloc_irqs_parent for %d parent hwirq %d\n", - irq + i, map->parent_hwirq); - ret = irq_domain_alloc_irqs_parent(d, irq + i, 1, - &parent_fwspec); - if (ret) - dev_err(g->dev, - "failed to allocate parent hwirq %d for hwirq %lu\n", - map->parent_hwirq, hwirq); + if (child >= 2 && child <= 12) { + *parent = child + 17; + return 0; } - - return 0; + return -EINVAL; } -static const struct irq_domain_ops ixp4xx_gpio_irqdomain_ops = { - .translate = ixp4xx_gpio_irq_domain_translate, - .alloc = ixp4xx_gpio_irq_domain_alloc, - .free = irq_domain_free_irqs_common, -}; - static int ixp4xx_gpio_probe(struct platform_device *pdev) { unsigned long flags; @@ -311,8 +194,8 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) struct irq_domain *parent; struct resource *res; struct ixp4xx_gpio *g; + struct gpio_irq_chip *girq; int ret; - int i; g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); if (!g) @@ -326,6 +209,35 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) return PTR_ERR(g->base); } + /* + * When we convert to device tree we will simply look up the + * parent irqdomain using irq_find_host(parent) as parent comes + * from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get + * the fwnode. For now we need this boardfile style code. + */ + if (np) { + struct device_node *irq_parent; + + irq_parent = of_irq_find_parent(np); + if (!irq_parent) { + dev_err(dev, "no IRQ parent node\n"); + return -ENODEV; + } + parent = irq_find_host(irq_parent); + if (!parent) { + dev_err(dev, "no IRQ parent domain\n"); + return -ENODEV; + } + g->fwnode = of_node_to_fwnode(np); + } else { + parent = ixp4xx_get_irq_domain(); + g->fwnode = irq_domain_alloc_fwnode(g->base); + if (!g->fwnode) { + dev_err(dev, "no domain base\n"); + return -ENODEV; + } + } + /* * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on * specific machines. @@ -360,7 +272,6 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) dev_err(dev, "unable to init generic GPIO\n"); return ret; } - g->gc.to_irq = ixp4xx_gpio_to_irq; g->gc.ngpio = 16; g->gc.label = "IXP4XX_GPIO_CHIP"; /* @@ -372,86 +283,22 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) g->gc.parent = &pdev->dev; g->gc.owner = THIS_MODULE; + girq = &g->gc.irq; + girq->chip = &ixp4xx_gpio_irqchip; + girq->fwnode = g->fwnode; + girq->parent_domain = parent; + girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq; + girq->handler = handle_bad_irq; + girq->default_type = IRQ_TYPE_NONE; + ret = devm_gpiochip_add_data(dev, &g->gc, g); if (ret) { dev_err(dev, "failed to add SoC gpiochip\n"); return ret; } - /* - * When we convert to device tree we will simply look up the - * parent irqdomain using irq_find_host(parent) as parent comes - * from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get - * the fwnode. For now we need this boardfile style code. - */ - if (np) { - struct device_node *irq_parent; - - irq_parent = of_irq_find_parent(np); - if (!irq_parent) { - dev_err(dev, "no IRQ parent node\n"); - return -ENODEV; - } - parent = irq_find_host(irq_parent); - if (!parent) { - dev_err(dev, "no IRQ parent domain\n"); - return -ENODEV; - } - g->fwnode = of_node_to_fwnode(np); - } else { - parent = ixp4xx_get_irq_domain(); - g->fwnode = irq_domain_alloc_fwnode(g->base); - if (!g->fwnode) { - dev_err(dev, "no domain base\n"); - return -ENODEV; - } - } - g->domain = irq_domain_create_hierarchy(parent, - IRQ_DOMAIN_FLAG_HIERARCHY, - ARRAY_SIZE(ixp4xx_gpiomap), - g->fwnode, - &ixp4xx_gpio_irqdomain_ops, - g); - if (!g->domain) { - irq_domain_free_fwnode(g->fwnode); - dev_err(dev, "no hierarchical irq domain\n"); - return ret; - } - - /* - * After adding OF support, this is no longer needed: irqs - * will be allocated for the respective fwnodes. - */ - if (!np) { - for (i = 0; i < ARRAY_SIZE(ixp4xx_gpiomap); i++) { - const struct ixp4xx_gpio_map *map = &ixp4xx_gpiomap[i]; - struct irq_fwspec fwspec; - - fwspec.fwnode = g->fwnode; - /* This is the hwirq for the GPIO line side of things */ - fwspec.param[0] = map->gpio_offset; - fwspec.param[1] = IRQ_TYPE_EDGE_RISING; - fwspec.param_count = 2; - ret = __irq_domain_alloc_irqs(g->domain, - -1, /* just pick something */ - 1, - NUMA_NO_NODE, - &fwspec, - false, - NULL); - if (ret < 0) { - irq_domain_free_fwnode(g->fwnode); - dev_err(dev, - "can not allocate irq for GPIO line %d parent hwirq %d in hierarchy domain: %d\n", - map->gpio_offset, map->parent_hwirq, - ret); - return ret; - } - } - } - platform_set_drvdata(pdev, g); - dev_info(dev, "IXP4 GPIO @%p registered\n", g->base); + dev_info(dev, "IXP4 GPIO registered\n"); return 0; } From patchwork Thu Aug 8 12:32:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 170801 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp8510280ile; Thu, 8 Aug 2019 05:32:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqyUEPB1n931xXqtnWyviIVa+j5R6Z1mooizPi6KP2biZM/hYcGlcQlRt9A6YS1C5zuD/gRm X-Received: by 2002:a17:902:e582:: with SMTP id cl2mr13713865plb.60.1565267579725; Thu, 08 Aug 2019 05:32:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565267579; cv=none; d=google.com; s=arc-20160816; b=j4m3Z1+jrqTt1eBpa3tR0i0Xzm2fjVx2hlsne+mA76zDemt1PE+gDOnE9G4Qh8Blan oNN8vfqlWcCLphCD/JJ9knts04UD2Bl9KgroSwiJQ0VX6MRL1+gBiXieHtmk2LY+hOnc jqQTjDmyAwM6U4CqlZB1Hpn2JUrdsXhC8yJ26EeZMPvgT74lttjQ3EQ3V/ZRro2AbvvK B7aWlCwhcSPwQy5UFGroZPLk7I+9oNfar48UZp/taNGVbv3cmLUUiWiLTcnK0j5Pr9a7 q6k3J3rQ9LyiOXXDzHEkSBVIDU4tY2bJjnqMetedePFtmJmB+qok5q448FAKm7qNUaJv WAQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MkHNIJOnmbUgzS/a/Zj0X23D5bcaeezV1tKLBba6NdU=; b=hoA4xDndqwyuL/wMU/puTjUSNpGqmAnWsDAhuGrcZuZbOHdmHEpi7lQ1iyoedrI/US AMcomkoh31MJQm0hWdN9+OF+gDvfR/DoBjc97RYasaS+a/mIInM9hR+5TQbZaXJfwVnf K62JeNm0oB2+Lb3SkZUsQmbx05FFNRZD02vpQk44hE14z6lkYFCYlT6e3I8sNE5n66uy XC6AqKbxfpEkFV2Nw/MqwFRnnTOjzQKBgNTWqcWmTyhwErVvmwxtAzAlWeEo3cviSk8d sv+CVJ51bgAIt2+F7KC3CC8QHKwhWUq3F3Uwk/2GC9zlJZyn6nmNleNAC9Y5yYkBTq95 TJIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tHIAoXry; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k72si54589669pge.95.2019.08.08.05.32.59; Thu, 08 Aug 2019 05:32:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tHIAoXry; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390080AbfHHMc7 (ORCPT + 5 others); Thu, 8 Aug 2019 08:32:59 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:34442 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389844AbfHHMc6 (ORCPT ); Thu, 8 Aug 2019 08:32:58 -0400 Received: by mail-lf1-f67.google.com with SMTP id b29so59473196lfq.1 for ; Thu, 08 Aug 2019 05:32:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MkHNIJOnmbUgzS/a/Zj0X23D5bcaeezV1tKLBba6NdU=; b=tHIAoXryGyT7e0oVcdjcyxWWiIFkHa5mMWInSoGITnHhABeDGteun9GIfBQvJe5Hcj +T9QfyPDwqbTn2dtgicqfPMVTi1nWp0M/7OKeB9KBJleGj12zGU/7U2Ef0V/Rabg+Nav wR4wzueg/ssGeYgU1oKYbZNRjf7qYFfwYMxokIMOyEHdA5p3Ig0jeoTAP+AB4cOD8SLa SWEX65zzUCkw56aCaj7ivhMce37Mjlbsq5YGUThbghpDyxKAn43j2CDY9UzPxR96eBnx OtnNFca4sYY3IOhnDhXUtAzZk7ZT67/piX1GJffZP+1JBScpJYj3BTwdkkbvGHAyvv5y 4p+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MkHNIJOnmbUgzS/a/Zj0X23D5bcaeezV1tKLBba6NdU=; b=sf5YDfkoF/WhSjyC9wxDr4f4jBuNEMRwbv0D2Ije9A7h6Xy8Fg6BrTqS2BOQSGrrMC 52KJgN0AziQUbLuuNGhrTEKwMoCAkC9bZiqgV1TsKieRSHoKRDhmg95eAG9VJmzijmPk /dFpkWvhLbZRuxFI08+v1zpUxNfp64kLHwK2NK0OrnCAk7ofJBoA/VJrWpqlDIYQP6Ep MZko8iNRhBUzTZJJXUCTO22aXRQefPrnWSZftB6MKmMSrwjrm8PkK2Rn9ANb6DNGutbu Ea2majA+lyVl/zTklcse7Cde3jIrQf10p2xrQZUZlB907Hk2mjVCmd9zdiMK7ygF/cfQ amZA== X-Gm-Message-State: APjAAAVYsnDpOY9X5pn+qntPMLLHI7d8LeCyVxgc6DnlwK9zAgVYPDFa IByyHfzeXqWtrm1+YrmvyWQmGZKmlh8= X-Received: by 2002:a19:c150:: with SMTP id r77mr9803308lff.76.1565267576313; Thu, 08 Aug 2019 05:32:56 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h10sm16976423lfp.33.2019.08.08.05.32.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 05:32:55 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Brian Masney , Linus Walleij Subject: [PATCH 3/6 v2] qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core Date: Thu, 8 Aug 2019 14:32:39 +0200 Message-Id: <20190808123242.5359-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190808123242.5359-1-linus.walleij@linaro.org> References: <20190808123242.5359-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Brian Masney Now that the GPIO core has support for hierarchical IRQ chips, convert Qualcomm's spmi-gpio over to use these new helpers to reduce duplicated code across drivers. This change was tested on a LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Change "child_pin_to_irq" into "child_offset_to_irq" so we avoid confusion with pin control. --- drivers/pinctrl/qcom/Kconfig | 1 + drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 92 +++++++----------------- 2 files changed, 26 insertions(+), 67 deletions(-) -- 2.21.0 diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 8e14a5f2e970..fa2c87821401 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -138,6 +138,7 @@ config PINCTRL_QCOM_SPMI_PMIC select PINMUX select PINCONF select GENERIC_PINCONF + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index f39da87ea185..442db15e0729 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -170,8 +170,6 @@ struct pmic_gpio_state { struct regmap *map; struct pinctrl_dev *ctrl; struct gpio_chip chip; - struct fwnode_handle *fwnode; - struct irq_domain *domain; }; static const struct pinconf_generic_params pmic_gpio_bindings[] = { @@ -751,23 +749,6 @@ static int pmic_gpio_of_xlate(struct gpio_chip *chip, return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; } -static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -{ - struct pmic_gpio_state *state = gpiochip_get_data(chip); - struct irq_fwspec fwspec; - - fwspec.fwnode = state->fwnode; - fwspec.param_count = 2; - fwspec.param[0] = pin + PMIC_GPIO_PHYSICAL_OFFSET; - /* - * Set the type to a safe value temporarily. This will be overwritten - * later with the proper value by irq_set_type. - */ - fwspec.param[1] = IRQ_TYPE_EDGE_RISING; - - return irq_create_fwspec_mapping(&fwspec); -} - static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct pmic_gpio_state *state = gpiochip_get_data(chip); @@ -787,7 +768,6 @@ static const struct gpio_chip pmic_gpio_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_gpio_of_xlate, - .to_irq = pmic_gpio_to_irq, .dbg_show = pmic_gpio_dbg_show, }; @@ -964,46 +944,24 @@ static int pmic_gpio_domain_translate(struct irq_domain *domain, return 0; } -static int pmic_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs, void *data) +static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) { - struct pmic_gpio_state *state = container_of(domain->host_data, - struct pmic_gpio_state, - chip); - struct irq_fwspec *fwspec = data; - struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq; - unsigned int type; - int ret, i; - - ret = pmic_gpio_domain_translate(domain, fwspec, &hwirq, &type); - if (ret) - return ret; - - for (i = 0; i < nr_irqs; i++) - irq_domain_set_info(domain, virq + i, hwirq + i, - &pmic_gpio_irq_chip, state, - handle_level_irq, NULL, NULL); + return offset + PMIC_GPIO_PHYSICAL_OFFSET; +} - parent_fwspec.fwnode = domain->parent->fwnode; - parent_fwspec.param_count = 4; - parent_fwspec.param[0] = 0; - parent_fwspec.param[1] = hwirq + 0xc0; - parent_fwspec.param[2] = 0; - parent_fwspec.param[3] = fwspec->param[1]; +static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, - &parent_fwspec); + return 0; } -static const struct irq_domain_ops pmic_gpio_domain_ops = { - .activate = gpiochip_irq_domain_activate, - .alloc = pmic_gpio_domain_alloc, - .deactivate = gpiochip_irq_domain_deactivate, - .free = irq_domain_free_irqs_common, - .translate = pmic_gpio_domain_translate, -}; - static int pmic_gpio_probe(struct platform_device *pdev) { struct irq_domain *parent_domain; @@ -1013,6 +971,7 @@ static int pmic_gpio_probe(struct platform_device *pdev) struct pinctrl_desc *pctrldesc; struct pmic_gpio_pad *pad, *pads; struct pmic_gpio_state *state; + struct gpio_irq_chip *girq; int ret, npins, i; u32 reg; @@ -1092,19 +1051,21 @@ static int pmic_gpio_probe(struct platform_device *pdev) if (!parent_domain) return -ENXIO; - state->fwnode = of_node_to_fwnode(state->dev->of_node); - state->domain = irq_domain_create_hierarchy(parent_domain, 0, - state->chip.ngpio, - state->fwnode, - &pmic_gpio_domain_ops, - &state->chip); - if (!state->domain) - return -ENODEV; + girq = &state->chip.irq; + girq->chip = &pmic_gpio_irq_chip; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; + girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate; ret = gpiochip_add_data(&state->chip, state); if (ret) { dev_err(state->dev, "can't add gpio chip\n"); - goto err_chip_add_data; + return ret; } /* @@ -1130,8 +1091,6 @@ static int pmic_gpio_probe(struct platform_device *pdev) err_range: gpiochip_remove(&state->chip); -err_chip_add_data: - irq_domain_remove(state->domain); return ret; } @@ -1140,7 +1099,6 @@ static int pmic_gpio_remove(struct platform_device *pdev) struct pmic_gpio_state *state = platform_get_drvdata(pdev); gpiochip_remove(&state->chip); - irq_domain_remove(state->domain); return 0; } From patchwork Thu Aug 8 12:32:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 170802 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp8510318ile; Thu, 8 Aug 2019 05:33:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqyird9+K013+LdkK3vLtCaMK3w/kScGCw0CZ4jZTXXzpITKIFyxXPcJHQNJU5ekVdrxg5uF X-Received: by 2002:a17:902:e509:: with SMTP id ck9mr5737736plb.326.1565267581762; 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[209.132.180.67]) by mx.google.com with ESMTP id k72si54589669pge.95.2019.08.08.05.33.01; Thu, 08 Aug 2019 05:33:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vz7n0fyX; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390079AbfHHMdB (ORCPT + 5 others); Thu, 8 Aug 2019 08:33:01 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:46213 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389844AbfHHMdA (ORCPT ); Thu, 8 Aug 2019 08:33:00 -0400 Received: by mail-lf1-f67.google.com with SMTP id z15so62444154lfh.13 for ; Thu, 08 Aug 2019 05:32:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6j2s4f6jQJuHPasrXYF7RrNBQqL8kwSajU7ijH7uh7Y=; b=Vz7n0fyXndxRLV4SgJvKO4M5hht3Hu0y+nhhvmwn+LALe74xuWXC/nWfD7fMDA8oEX GW8oL0yeY5UUmiCFEhaaUmsw/7pL3vXaJO0AfAeiKjIe9nTs953IHt0EBJlguFL+btiL Wi6OOhWOzb4sUBV6KA269ifxrE9jpvH562IUgcGazor3y/PWgBZGBm5c+5o6+ioCCAF0 h9h7aejhuJhO0u9nfHMAjacX74A1q3Y8ABpIWmbk3gdXd6dbg/saQir6iPo35yGT45C4 SglN6fd5CPHJAbu9vA3b3GxK99C7LmNHrOn98a+3GtaVx4/uSQ8K9t+TQZyqmPrbxDuX /Yrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6j2s4f6jQJuHPasrXYF7RrNBQqL8kwSajU7ijH7uh7Y=; b=d9g+b+/gtpIHId7Q+jZ39E0BifDNxasUjWo32pbbxRhGyG4215HFRHKl33mDaQ1RZv neqE4j38lm6nMkfmb+xCqh77+khnrs236Qcpr7FbOK7bhuQbSm7b3Bgdmrz6DgVmAn1s Shs3YKFifD9kobqHaTwwMG3Toj0uVwjAQHvcvAoiNMQuMoKiBdYqS6AMDPktC1SbB3pf h3RGk7IRBe/3pUF35s9GYA2aanhrWW5TQdQecEPS4pKD6ciuCGMhxMI8t7ZrRt+ZQ//2 eTTcAQd4uD4ubFgNRHSjRKrPhtJguzwANuhCRNlqyfQcjV/7ofDqX2D6fRUV+3u1Wgs/ HbXA== X-Gm-Message-State: APjAAAWhXAbd0M+se2iR9e0ZicJXdJOFlppPw8Hjnjr8pQP7Axox2AZu 0XEJYv5bQAXKsCXQw7/71bDQiqF60eE= X-Received: by 2002:a19:4a50:: with SMTP id x77mr9051038lfa.91.1565267578286; Thu, 08 Aug 2019 05:32:58 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h10sm16976423lfp.33.2019.08.08.05.32.57 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 05:32:57 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , David Daney , Thierry Reding , Brian Masney Subject: [PATCH 4/6 v2] RFT: gpio: thunderx: Switch to GPIOLIB_IRQCHIP Date: Thu, 8 Aug 2019 14:32:40 +0200 Message-Id: <20190808123242.5359-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190808123242.5359-1-linus.walleij@linaro.org> References: <20190808123242.5359-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Use the new infrastructure for hierarchical irqchips in gpiolib. The major part of the rewrite was dues to the fact that the driver was passing around a per-irq pointer to struct thunderx_line * data container, and the central handlers will assume struct gpio_chip * to be passed to we need to use the hwirq as index to look up the struct thunderx_line * for each IRQ. The pushing and pop:ing of the irqdomain was confusing because I've never seen this before, but I tried to replicate it as best I could. I have no chance to test or debug this so I need help. Cc: David Daney Cc: Thierry Reding Cc: Brian Masney Signed-off-by: Linus Walleij --- ChangeLog RFT v1-> RFT v2: - Rebased. --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-thunderx.c | 163 ++++++++++++----------------------- 2 files changed, 57 insertions(+), 107 deletions(-) -- 2.21.0 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b34e9b11a7ef..3125aca2db9f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -539,6 +539,7 @@ config GPIO_THUNDERX tristate "Cavium ThunderX/OCTEON-TX GPIO" depends on ARCH_THUNDER || (64BIT && COMPILE_TEST) depends on PCI_MSI + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY select IRQ_FASTEOI_HIERARCHY_HANDLERS help diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 715371b5102a..ddad5c7ea617 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -53,7 +53,6 @@ struct thunderx_line { struct thunderx_gpio { struct gpio_chip chip; u8 __iomem *register_base; - struct irq_domain *irqd; struct msix_entry *msix_entries; /* per line MSI-X */ struct thunderx_line *line_entries; /* per line irq info */ raw_spinlock_t lock; @@ -283,54 +282,60 @@ static void thunderx_gpio_set_multiple(struct gpio_chip *chip, } } -static void thunderx_gpio_irq_ack(struct irq_data *data) +static void thunderx_gpio_irq_ack(struct irq_data *d) { - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct thunderx_gpio *txgpio = gpiochip_get_data(gc); writeq(GPIO_INTR_INTR, - txline->txgpio->register_base + intr_reg(txline->line)); + txgpio->register_base + intr_reg(irqd_to_hwirq(d))); } -static void thunderx_gpio_irq_mask(struct irq_data *data) +static void thunderx_gpio_irq_mask(struct irq_data *d) { - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct thunderx_gpio *txgpio = gpiochip_get_data(gc); writeq(GPIO_INTR_ENA_W1C, - txline->txgpio->register_base + intr_reg(txline->line)); + txgpio->register_base + intr_reg(irqd_to_hwirq(d))); } -static void thunderx_gpio_irq_mask_ack(struct irq_data *data) +static void thunderx_gpio_irq_mask_ack(struct irq_data *d) { - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct thunderx_gpio *txgpio = gpiochip_get_data(gc); writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, - txline->txgpio->register_base + intr_reg(txline->line)); + txgpio->register_base + intr_reg(irqd_to_hwirq(d))); } -static void thunderx_gpio_irq_unmask(struct irq_data *data) +static void thunderx_gpio_irq_unmask(struct irq_data *d) { - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct thunderx_gpio *txgpio = gpiochip_get_data(gc); writeq(GPIO_INTR_ENA_W1S, - txline->txgpio->register_base + intr_reg(txline->line)); + txgpio->register_base + intr_reg(irqd_to_hwirq(d))); } -static int thunderx_gpio_irq_set_type(struct irq_data *data, +static int thunderx_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); - struct thunderx_gpio *txgpio = txline->txgpio; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct thunderx_gpio *txgpio = gpiochip_get_data(gc); + struct thunderx_line *txline = + &txgpio->line_entries[irqd_to_hwirq(d)]; u64 bit_cfg; - irqd_set_trigger_type(data, flow_type); + irqd_set_trigger_type(d, flow_type); bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; if (flow_type & IRQ_TYPE_EDGE_BOTH) { - irq_set_handler_locked(data, handle_fasteoi_ack_irq); + irq_set_handler_locked(d, handle_fasteoi_ack_irq); bit_cfg |= GPIO_BIT_CFG_INT_TYPE; } else { - irq_set_handler_locked(data, handle_fasteoi_mask_irq); + irq_set_handler_locked(d, handle_fasteoi_mask_irq); } raw_spin_lock(&txgpio->lock); @@ -359,33 +364,6 @@ static void thunderx_gpio_irq_disable(struct irq_data *data) irq_chip_disable_parent(data); } -static int thunderx_gpio_irq_request_resources(struct irq_data *data) -{ - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); - struct thunderx_gpio *txgpio = txline->txgpio; - int r; - - r = gpiochip_lock_as_irq(&txgpio->chip, txline->line); - if (r) - return r; - - r = irq_chip_request_resources_parent(data); - if (r) - gpiochip_unlock_as_irq(&txgpio->chip, txline->line); - - return r; -} - -static void thunderx_gpio_irq_release_resources(struct irq_data *data) -{ - struct thunderx_line *txline = irq_data_get_irq_chip_data(data); - struct thunderx_gpio *txgpio = txline->txgpio; - - irq_chip_release_resources_parent(data); - - gpiochip_unlock_as_irq(&txgpio->chip, txline->line); -} - /* * Interrupts are chained from underlying MSI-X vectors. We have * these irq_chip functions to be able to handle level triggering @@ -402,48 +380,22 @@ static struct irq_chip thunderx_gpio_irq_chip = { .irq_unmask = thunderx_gpio_irq_unmask, .irq_eoi = irq_chip_eoi_parent, .irq_set_affinity = irq_chip_set_affinity_parent, - .irq_request_resources = thunderx_gpio_irq_request_resources, - .irq_release_resources = thunderx_gpio_irq_release_resources, .irq_set_type = thunderx_gpio_irq_set_type, .flags = IRQCHIP_SET_TYPE_MASKED }; -static int thunderx_gpio_irq_translate(struct irq_domain *d, - struct irq_fwspec *fwspec, - irq_hw_number_t *hwirq, - unsigned int *type) +static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) { - struct thunderx_gpio *txgpio = d->host_data; - - if (WARN_ON(fwspec->param_count < 2)) - return -EINVAL; - if (fwspec->param[0] >= txgpio->chip.ngpio) - return -EINVAL; - *hwirq = fwspec->param[0]; - *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; - return 0; -} - -static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq, - unsigned int nr_irqs, void *arg) -{ - struct thunderx_line *txline = arg; + struct thunderx_gpio *txgpio = gpiochip_get_data(gc); - return irq_domain_set_hwirq_and_chip(d, virq, txline->line, - &thunderx_gpio_irq_chip, txline); -} - -static const struct irq_domain_ops thunderx_gpio_irqd_ops = { - .alloc = thunderx_gpio_irq_alloc, - .translate = thunderx_gpio_irq_translate -}; - -static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - struct thunderx_gpio *txgpio = gpiochip_get_data(chip); - - return irq_find_mapping(txgpio->irqd, offset); + *parent = txgpio->base_msi + (2 * child); + *parent_type = IRQ_TYPE_LEVEL_HIGH; + return 0; } static int thunderx_gpio_probe(struct pci_dev *pdev, @@ -453,6 +405,7 @@ static int thunderx_gpio_probe(struct pci_dev *pdev, struct device *dev = &pdev->dev; struct thunderx_gpio *txgpio; struct gpio_chip *chip; + struct gpio_irq_chip *girq; int ngpio, i; int err = 0; @@ -497,8 +450,8 @@ static int thunderx_gpio_probe(struct pci_dev *pdev, } txgpio->msix_entries = devm_kcalloc(dev, - ngpio, sizeof(struct msix_entry), - GFP_KERNEL); + ngpio, sizeof(struct msix_entry), + GFP_KERNEL); if (!txgpio->msix_entries) { err = -ENOMEM; goto out; @@ -539,27 +492,6 @@ static int thunderx_gpio_probe(struct pci_dev *pdev, if (err < 0) goto out; - /* - * Push GPIO specific irqdomain on hierarchy created as a side - * effect of the pci_enable_msix() - */ - txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain, - 0, 0, of_node_to_fwnode(dev->of_node), - &thunderx_gpio_irqd_ops, txgpio); - if (!txgpio->irqd) { - err = -ENOMEM; - goto out; - } - - /* Push on irq_data and the domain for each line. */ - for (i = 0; i < ngpio; i++) { - err = irq_domain_push_irq(txgpio->irqd, - txgpio->msix_entries[i].vector, - &txgpio->line_entries[i]); - if (err < 0) - dev_err(dev, "irq_domain_push_irq: %d\n", err); - } - chip->label = KBUILD_MODNAME; chip->parent = dev; chip->owner = THIS_MODULE; @@ -574,11 +506,28 @@ static int thunderx_gpio_probe(struct pci_dev *pdev, chip->set = thunderx_gpio_set; chip->set_multiple = thunderx_gpio_set_multiple; chip->set_config = thunderx_gpio_set_config; - chip->to_irq = thunderx_gpio_to_irq; + girq = &chip->irq; + girq->chip = &thunderx_gpio_irq_chip; + girq->fwnode = of_node_to_fwnode(dev->of_node); + girq->parent_domain = + irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; + girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq; + girq->handler = handle_bad_irq; + girq->default_type = IRQ_TYPE_NONE; + err = devm_gpiochip_add_data(dev, chip, txgpio); if (err) goto out; + /* Push on irq_data and the domain for each line. */ + for (i = 0; i < ngpio; i++) { + err = irq_domain_push_irq(chip->irq.domain, + txgpio->msix_entries[i].vector, + chip); + if (err < 0) + dev_err(dev, "irq_domain_push_irq: %d\n", err); + } + dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n", ngpio, chip->base); return 0; @@ -593,10 +542,10 @@ static void thunderx_gpio_remove(struct pci_dev *pdev) struct thunderx_gpio *txgpio = pci_get_drvdata(pdev); for (i = 0; i < txgpio->chip.ngpio; i++) - irq_domain_pop_irq(txgpio->irqd, + irq_domain_pop_irq(txgpio->chip.irq.domain, txgpio->msix_entries[i].vector); - irq_domain_remove(txgpio->irqd); + irq_domain_remove(txgpio->chip.irq.domain); pci_set_drvdata(pdev, NULL); } From patchwork Thu Aug 8 12:32:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 170803 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp8510369ile; Thu, 8 Aug 2019 05:33:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxeZ+ET/41ZUPOb6H1CQOlsiHZLI+Tk4jfgX3DNW8OUE/itCCrpzCPkSA+sKoJjxU6xm6w2 X-Received: by 2002:a63:6888:: with SMTP id d130mr12029643pgc.197.1565267583926; Thu, 08 Aug 2019 05:33:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565267583; cv=none; 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[209.132.180.67]) by mx.google.com with ESMTP id k72si54589669pge.95.2019.08.08.05.33.03; Thu, 08 Aug 2019 05:33:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ymhzJEk8; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390081AbfHHMdD (ORCPT + 5 others); Thu, 8 Aug 2019 08:33:03 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:39010 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389844AbfHHMdD (ORCPT ); Thu, 8 Aug 2019 08:33:03 -0400 Received: by mail-lf1-f67.google.com with SMTP id x3so12939781lfn.6 for ; Thu, 08 Aug 2019 05:33:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SmtPwA7NjZrWTlsBilnXx+sFQ6/jgEnaP8r4ClnBdAY=; b=ymhzJEk8HPk97o8+rgM4kehWED2C/fzxHmyjJcSZuukzdq8pu+oN+Ho6qOZCgAttsE LYTNpUa2XLUhFdlunjbPhFthEUKLFJXOwzar8sw7h1IlszJmh8/i2brpNqLSQ43U4Ry6 mT6pM1PM+i6jcLFqm9fe+5H5dWfaR7BDYlbPko6UpLxZZC1lPryXKAXyFrAp6KczR2i/ 2C39/+ybV8ZcRP43/8Mmqa/F+IcKGTT5Bv1GyRlN7+FPcehzpsq22m8B7Xc4c0qbhGbi KDigF8FE9e/nXq7jPQP+yHER2QztfpUAFUn1nFaOK8OjG1i/ZRQapszGJZapWDNPlPc9 TBYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SmtPwA7NjZrWTlsBilnXx+sFQ6/jgEnaP8r4ClnBdAY=; b=b2C26PfxEeChBzeeo8iZTfc9D6Jr5B8OjHhkM5kWYN3fl/K5dhQsxkY4J5QKGXpU9k HitxeTA/OThWR9p27aVObOt7WBPFQD+tp3dMPLCc6a/e37dSna5BnJET1NQS/WnLUE4z BXXJokfEmLVYrvhCLmYcQfVfosQ2XjTYXDk4WuUEXT0/tx9KHASrnlqaS3CcAxrRW2Uw +Nst8aONQp2uIOfXpOXrZ4mRZ36RrFsc/oC4qlq/KMavMu+yCqsz2Ftlp8kmvdpp6C7r XQcxZuZShXnSzM5I34b5bgPU9/NSgBqChtwsEKF0H6SzJt8Qa63OPl1HyVkM/ZZFLhBA dcYQ== X-Gm-Message-State: APjAAAXkegFRfVsvC7ckwWyooYKdfzu+I2WdZSfY2PSSYwE3TgvlCoIY MH4dOhOJlmhV2f9cymN3QXehQ5oPYCY= X-Received: by 2002:a19:641a:: with SMTP id y26mr9107101lfb.29.1565267580241; Thu, 08 Aug 2019 05:33:00 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h10sm16976423lfp.33.2019.08.08.05.32.58 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 05:32:59 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Masahiro Yamada , Thierry Reding , Brian Masney Subject: [PATCH 5/6 v2] RFT: gpio: uniphier: Switch to GPIOLIB_IRQCHIP Date: Thu, 8 Aug 2019 14:32:41 +0200 Message-Id: <20190808123242.5359-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190808123242.5359-1-linus.walleij@linaro.org> References: <20190808123242.5359-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Use the new infrastructure for hierarchical irqchips in gpiolib. I have no chance to test or debug this so I need help. Cc: Masahiro Yamada Cc: Thierry Reding Cc: Brian Masney Signed-off-by: Linus Walleij --- ChangeLog RFT v1 -> RFT v2: - Drop noisy change of "data" parameter to "d" - Use ->child_offset_to_irq() callback to account for the UNIPHIER_GPIO_IRQ_OFFSET. --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-uniphier.c | 161 +++++++++-------------------------- 2 files changed, 43 insertions(+), 119 deletions(-) -- 2.21.0 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3125aca2db9f..cc07bbe4864e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -550,6 +550,7 @@ config GPIO_UNIPHIER tristate "UniPhier GPIO support" depends on ARCH_UNIPHIER || COMPILE_TEST depends on OF_GPIO + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY help Say yes here to support UniPhier GPIOs. diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index 93cdcc41e9fb..86e8446215fc 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -30,7 +29,6 @@ struct uniphier_gpio_priv { struct gpio_chip chip; struct irq_chip irq_chip; - struct irq_domain *domain; void __iomem *regs; spinlock_t lock; u32 saved_vals[0]; @@ -162,28 +160,10 @@ static void uniphier_gpio_set_multiple(struct gpio_chip *chip, } } -static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - struct irq_fwspec fwspec; - - if (offset < UNIPHIER_GPIO_IRQ_OFFSET) - return -ENXIO; - - fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node); - fwspec.param_count = 2; - fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET; - /* - * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH - * temporarily. Anyway, ->irq_set_type() will override it later. - */ - fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; - - return irq_create_fwspec_mapping(&fwspec); -} - static void uniphier_gpio_irq_mask(struct irq_data *data) { - struct uniphier_gpio_priv *priv = data->chip_data; + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct uniphier_gpio_priv *priv = gpiochip_get_data(gc); u32 mask = BIT(data->hwirq); uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0); @@ -193,7 +173,8 @@ static void uniphier_gpio_irq_mask(struct irq_data *data) static void uniphier_gpio_irq_unmask(struct irq_data *data) { - struct uniphier_gpio_priv *priv = data->chip_data; + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct uniphier_gpio_priv *priv = gpiochip_get_data(gc); u32 mask = BIT(data->hwirq); uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask); @@ -203,7 +184,8 @@ static void uniphier_gpio_irq_unmask(struct irq_data *data) static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type) { - struct uniphier_gpio_priv *priv = data->chip_data; + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct uniphier_gpio_priv *priv = gpiochip_get_data(gc); u32 mask = BIT(data->hwirq); u32 val = 0; @@ -245,82 +227,6 @@ static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv, return -ENOENT; } -static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain, - struct irq_fwspec *fwspec, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - if (WARN_ON(fwspec->param_count < 2)) - return -EINVAL; - - *out_hwirq = fwspec->param[0]; - *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; - - return 0; -} - -static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain, - unsigned int virq, - unsigned int nr_irqs, void *arg) -{ - struct uniphier_gpio_priv *priv = domain->host_data; - struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq; - unsigned int type; - int ret; - - if (WARN_ON(nr_irqs != 1)) - return -EINVAL; - - ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type); - if (ret) - return ret; - - ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq); - if (ret < 0) - return ret; - - /* parent is UniPhier AIDET */ - parent_fwspec.fwnode = domain->parent->fwnode; - parent_fwspec.param_count = 2; - parent_fwspec.param[0] = ret; - parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ? - IRQ_TYPE_EDGE_FALLING : type; - - ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, - &priv->irq_chip, priv); - if (ret) - return ret; - - return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); -} - -static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain, - struct irq_data *data, bool early) -{ - struct uniphier_gpio_priv *priv = domain->host_data; - struct gpio_chip *chip = &priv->chip; - - return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); -} - -static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain, - struct irq_data *data) -{ - struct uniphier_gpio_priv *priv = domain->host_data; - struct gpio_chip *chip = &priv->chip; - - gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); -} - -static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = { - .alloc = uniphier_gpio_irq_domain_alloc, - .free = irq_domain_free_irqs_common, - .activate = uniphier_gpio_irq_domain_activate, - .deactivate = uniphier_gpio_irq_domain_deactivate, - .translate = uniphier_gpio_irq_domain_translate, -}; - static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv) { /* @@ -338,6 +244,32 @@ static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio) return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK); } +static unsigned int uniphier_gpio_child_offset_to_irq(struct gpio_chip *gc, + unsigned int offset) +{ + return offset + UNIPHIER_GPIO_IRQ_OFFSET; +} + +static int uniphier_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct uniphier_gpio_priv *priv = gpiochip_get_data(gc); + int ret; + + ret = uniphier_gpio_irq_get_parent_hwirq(priv, child); + if (ret < 0) + return ret; + *parent = ret; + if (child_type == IRQ_TYPE_EDGE_BOTH) + *parent_type = IRQ_TYPE_EDGE_FALLING; + else + *parent_type = child_type; + return 0; +} + static int uniphier_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -345,6 +277,7 @@ static int uniphier_gpio_probe(struct platform_device *pdev) struct irq_domain *parent_domain; struct uniphier_gpio_priv *priv; struct gpio_chip *chip; + struct gpio_irq_chip *girq; struct irq_chip *irq_chip; unsigned int nregs; u32 ngpios; @@ -386,7 +319,6 @@ static int uniphier_gpio_probe(struct platform_device *pdev) chip->get = uniphier_gpio_get; chip->set = uniphier_gpio_set; chip->set_multiple = uniphier_gpio_set_multiple; - chip->to_irq = uniphier_gpio_to_irq; chip->base = -1; chip->ngpio = ngpios; @@ -398,34 +330,26 @@ static int uniphier_gpio_probe(struct platform_device *pdev) irq_chip->irq_set_affinity = irq_chip_set_affinity_parent; irq_chip->irq_set_type = uniphier_gpio_irq_set_type; + girq = &chip->irq; + girq->chip = irq_chip; + girq->fwnode = of_node_to_fwnode(dev->of_node); + girq->parent_domain = parent_domain; + girq->child_offset_to_irq = uniphier_gpio_child_offset_to_irq; + girq->child_to_parent_hwirq = uniphier_gpio_child_to_parent_hwirq; + girq->handler = handle_bad_irq; + girq->default_type = IRQ_TYPE_NONE; + uniphier_gpio_hw_init(priv); ret = devm_gpiochip_add_data(dev, chip, priv); if (ret) return ret; - priv->domain = irq_domain_create_hierarchy( - parent_domain, 0, - UNIPHIER_GPIO_IRQ_MAX_NUM, - of_node_to_fwnode(dev->of_node), - &uniphier_gpio_irq_domain_ops, priv); - if (!priv->domain) - return -ENOMEM; - platform_set_drvdata(pdev, priv); return 0; } -static int uniphier_gpio_remove(struct platform_device *pdev) -{ - struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev); - - irq_domain_remove(priv->domain); - - return 0; -} - static int __maybe_unused uniphier_gpio_suspend(struct device *dev) { struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); @@ -485,7 +409,6 @@ MODULE_DEVICE_TABLE(of, uniphier_gpio_match); static struct platform_driver uniphier_gpio_driver = { .probe = uniphier_gpio_probe, - .remove = uniphier_gpio_remove, .driver = { .name = "uniphier-gpio", .of_match_table = uniphier_gpio_match, From patchwork Thu Aug 8 12:32:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 170804 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp8510395ile; Thu, 8 Aug 2019 05:33:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjfEHic4tDIpRpHCwkXgiX196LSZDudMzTnPl0lVYprlM9b3ujPgZwGhpdhOwCHhmeiq2q X-Received: by 2002:a62:5883:: with SMTP id m125mr15170378pfb.248.1565267585331; Thu, 08 Aug 2019 05:33:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565267585; cv=none; d=google.com; s=arc-20160816; b=tuVdveRm9Vm2/eHgyVurq7+qvJ2m0ICP/NK9PYbflaNxhqAC3leNOjwNUM+kA1GbNs NJPaIMPB02SXeLlfmb2qcepOmkHH1jynjNSIgd1rmru0zbN06bgnI/9tV94PSsYcdFBH C4WqNdAe53CDtbGfpO3TLzyKdn1RVphenEMA/nfPTf99OM19ax5JpTG3Bkg9+St3/8kZ 277/FG2Zyn4Qf+ubBkrCT1G3BdYHs5/DEpj/yLyJXYQxPQotXYNMjk78C6+uRBwMrqHZ zTzfRmLJRKDvfCQc/2bn+TxYmJ6lWEcEbChgSVf848yZOC9ZUllm90Q0ARvu4wH9D09B PBEA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id k72si54589669pge.95.2019.08.08.05.33.05; Thu, 08 Aug 2019 05:33:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jhTNJAxa; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390082AbfHHMdE (ORCPT + 5 others); Thu, 8 Aug 2019 08:33:04 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:39187 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389937AbfHHMdE (ORCPT ); Thu, 8 Aug 2019 08:33:04 -0400 Received: by mail-lj1-f193.google.com with SMTP id v18so88660893ljh.6 for ; Thu, 08 Aug 2019 05:33:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3d/YX3xQUjSdE9XgrTOBh4aQEajQ1l3t0t0ocHH6eps=; b=jhTNJAxa+jhwaNI6QsPD3ImdY6WbZnDzaJe2M7EiDGf59pHNsDrmM7AO83NaMAImWv 2hTvJouMXMluWwjsq4Hh0ZtE/MYGRJV+T9Ezh1whUyTbMO9mu+14iksUt5IZ6An4gvzW JN9OPeQp9MVuHTgpDI9E0JrHyyIjBCNmk0bGXvWpq9HfnFnyxem7V/+lwxVH2I5wokpn ADk8GP2mYdVeHZQNSs9D42Cr7iQ+aoTSFO/ejFW2DfK/+POCd5KRUUKucFznFeA4Fu5D y3Q5XtTvLzLF5ClRcCZOyRD/SGGn8oK9IkM3cy/bnv/Ndwd4UX2VcftLEXAnHs4DXGnT Z4YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3d/YX3xQUjSdE9XgrTOBh4aQEajQ1l3t0t0ocHH6eps=; b=Mx3gEz0VG6km1pUCgxeYW9Wv+MMJK10ysY5Y15cd6GsoBMMs9BF/E7G9XFtmry7ErC up8GPGqoKtMjgcNgc7PvaIzoc3o/2pB2dxFWTKEkTmwz2v2JDlGsr3GxsSGo1GBxk4Ex cd/O5eAxVlX1j1LRUaQsztfRB/ZVVFZQpH/rU3jhuebLldowBK00TJJJK7A1pD65nwOb X8c6DzFXQVsoDhDCalEeOfu6VAcYMvud6ubRwyITCj5CoAzgFuxvDo8Uav6wwiSaFHM4 xi0pX4XUJV9JRDnQ62AtihzYIYaEaX1fYIQeRCjzoDx5mpucBg6CY8PaQmnp5kSJ07Ev YThQ== X-Gm-Message-State: APjAAAXKr8O0UO2F7k/fk+luKq+rBKAs6pGdfNKz6qIbolec0p5SMgBs CTyRGd2jNKPIc0YilpBEW7jMMkUGtqs= X-Received: by 2002:a2e:86c1:: with SMTP id n1mr8050165ljj.162.1565267582297; Thu, 08 Aug 2019 05:33:02 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h10sm16976423lfp.33.2019.08.08.05.33.00 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 05:33:01 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Masahiro Yamada , Thierry Reding , Brian Masney Subject: [PATCH 6/6 v2] RFT: gpio: uniphier: Restrict valid interrupts Date: Thu, 8 Aug 2019 14:32:42 +0200 Message-Id: <20190808123242.5359-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190808123242.5359-1-linus.walleij@linaro.org> References: <20190808123242.5359-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Uniphier GPIO can only create interrupt mappings on GPIOs offset 0..23. Set the valid_mask in the struct gpio_irqchip and clear bits 24..ngpios indicating that these can not be mapped to interrupts. Cc: Masahiro Yamada Cc: Thierry Reding Cc: Brian Masney Signed-off-by: Linus Walleij --- ChangeLog RFT -> RTF v2: - New patch to set the valid mask for the interrupts. --- drivers/gpio/gpio-uniphier.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.21.0 diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index 86e8446215fc..9840fcf7de57 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -338,6 +338,7 @@ static int uniphier_gpio_probe(struct platform_device *pdev) girq->child_to_parent_hwirq = uniphier_gpio_child_to_parent_hwirq; girq->handler = handle_bad_irq; girq->default_type = IRQ_TYPE_NONE; + girq->need_valid_mask = true; uniphier_gpio_hw_init(priv); @@ -345,6 +346,10 @@ static int uniphier_gpio_probe(struct platform_device *pdev) if (ret) return ret; + /* Only GPIOs 0..UNIPHIER_GPIO_IRQ_MAX_NUM are valid for interrupts */ + bitmap_clear(girq->valid_mask, UNIPHIER_GPIO_IRQ_MAX_NUM, + ngpios - UNIPHIER_GPIO_IRQ_MAX_NUM); + platform_set_drvdata(pdev, priv); return 0;