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When CMD/DATA lines direction change from output to input, uSDHC controller begin sampling, the integration issue will make input enable signal from uSDHC propagated to the PAD with a long delay, thus the new input value on the pad comes to uSDHC lately. The uSDHC sampled the old input value and the sampling result is wrong. Workaround: Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will propagate input to uSDHC with no delay, so correct value is sampled. This issue will wrongly trigger the start bit when sample the USDHC command response, cause the USDHC trigger command CRC/index/endbit error, which will finally impact the tuning pass window, espically will impact the standard tuning logic, and can't find a correct delay cell to get the best timing. Signed-off-by: Haibo Chen --- .../boot/dts/freescale/imx93-11x11-evk.dts | 30 ++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 2b9d47716f75..021caf471bf6 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -237,18 +237,19 @@ MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; }; @@ -265,14 +266,15 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; From patchwork Tue Oct 17 06:50:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bough Chen X-Patchwork-Id: 734629 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69EE48F5C for ; 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Received: from DB7PR04MB4010.eurprd04.prod.outlook.com (2603:10a6:5:21::30) by DBAPR04MB7336.eurprd04.prod.outlook.com (2603:10a6:10:1a9::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36; Tue, 17 Oct 2023 06:45:55 +0000 Received: from DB7PR04MB4010.eurprd04.prod.outlook.com ([fe80::e796:8366:5d4:4188]) by DB7PR04MB4010.eurprd04.prod.outlook.com ([fe80::e796:8366:5d4:4188%4]) with mapi id 15.20.6886.034; Tue, 17 Oct 2023 06:45:55 +0000 From: haibo.chen@nxp.com To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, haibo.chen@nxp.com Subject: [PATCH 3/3] arm64: dts: imx93-11x11-evk: add 12 ms delay to make sure the VDD_SD power off Date: Tue, 17 Oct 2023 14:50:48 +0800 Message-Id: <20231017065048.1304294-3-haibo.chen@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017065048.1304294-1-haibo.chen@nxp.com> References: <20231017065048.1304294-1-haibo.chen@nxp.com> X-ClientProxiedBy: SG2PR02CA0129.apcprd02.prod.outlook.com (2603:1096:4:188::19) To DB7PR04MB4010.eurprd04.prod.outlook.com (2603:10a6:5:21::30) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB4010:EE_|DBAPR04MB7336:EE_ X-MS-Office365-Filtering-Correlation-Id: d4b9ac7d-295e-4159-772c-08dbcedcb663 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: y3ZU6LYZplLCUtsSYfDgedJu6Ptc/ZokUo6SOxHoswCsirgDvL93XM6gsNRj163e7ci0zeGJV8v7T7ZfxpZhwCvSirfvvH01gY1iHidAiuAnYQvlfs5pmJ1Zan4Tr30a1gGGZtfthmADQWgd00OQ01bxSOecXOzgJr6NQXW0bDdXpaF+y752eDzijEiMHk1jOhGw8zNj9UYkvLIQ1cdxGeZrJdH+7sI1OKrrS+h1KylKMZF/aCmTvuhzJCeiEoTsXolIiKRhYVcYwTw50Em6sqFbGr6iEZzVykqbgUeXdzFjEwGLVLHcw2yDJilo1BX0KMOgult6w96lWqcksAqJWz+RiJDjub0EeA1ev963v180jGrwD0ui41M4uOE5gUAVKE02AZbb2zAhzVpF4zw2lFsNWrmxjxkpX+BJoO8XMs5PPqIQsQsdD7cqL2FB4+1veeypY9FK8IIOLh7mzANabo5XIkA9OCs4dEKIuOh8AL3mqp3sUBRTW1A2TvyYgSOdth47pS6DyFh57+evpqOdlOy1UJ4Djya84tyEVmTI/etynP2k8zp+dRz4manEforuJjABL04o0o8G9UfpIJBqlixOMcE9RMwYNCX7tPBSAczPSTRgJcuLEVx66eC4vZR0xi6TPoxsZFVlwD5qj5sU5r6Mhd+T0QsgBH/MtrcBOBEmAIyUcWnbFPIKaic9Z3PodGvFGFUHpjEPDqzV4WRbs8vElAGYEc2pgQdsJROoFLuPXh2CTRgfTPyzd630XE9SWW7xffjvLURgAgG8HV0DqdAFsoyuX6kzyWo4EHNY2LSQozD+AvjQy/pCTUjTlD4pbvq9VTIQe3K2KPTlv/HGicLCN141MMg3vnFQjFWaI10Y4TyEIt6rhPtxaaEUA1PIAqrEmfbmJ1ZJXcg6IDUEjr4/OjCq0L7IaoV1nY1o/fgM2GA5CouJVNuUNAPjC32OdYJeKibqDmKwbf7N5wYQ5HwehH9vPDXQtX+7yFm+V68lOgO9LmEqWbt5Hrb7gdJI1EGs2AfB2zZ04Yn5GzYV314JMuJLgPfx7Z5N1R1jUeWXx5PRHiWg3FLRUrF2PlUsMGmyQLXPCWjZg0uwO5m+zpcSUBe2Pblobl6bjDxbRSARjwBloHIIn/N7oaevGyxVyUAZjHSFC/W3X2fYsVH24pqwVD5G6XanQ7A9JDP0Rlok8ySaqwNGTN/P9HGxxyuMphiO2xTmY7qyOQj6Cbb3rY3Ot9uAN43mWp3Gk7X4B/LUr4wcjNtvlMG98XwiTF8pFg/A3hxf1x0OsSx/A123yJecT9EVssdgnFXr1IkhcQ33f4NeWWRJBVAKmkyatPwLJ/FzJpLscPesq/g5evQuBsW0A86dYMvnogfXBK1bEJIpt2q7JgAqJR79oFx2s2hCsamHQ0hqVOGmrLXCuup/jTp4tGyLxgtu3T728N6mHF3+3PY8dtEjQm251nyu3Y4R+xzfAeP2RHp9vSS4AerpNnyfgg0/VenwNRJzOihNzFYaKfVNtjkVJC9Kto0w6V+brHSJ3YMoGG0bBfSlLpdozsca6NpCHZKrTBzlpP7W9qRQZEuOCVIKbqRJCIStQ+E4 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4b9ac7d-295e-4159-772c-08dbcedcb663 X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB4010.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2023 06:45:55.5242 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7hqZyVwY1bC8Z4jN3Fqlq5fNdGrED/ZrF9nXOeyAr0Ddnc4Ny1dA6VfumuxyayUUjphGtXnYzKYOR34mxwOcbw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7336 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Haibo Chen To support SD3.0 mode, according to the SD spec, a clean power off for the VDD_SD is keep the VDD_SD lower than 0.5V for at least 1ms. On imx93 board, gate off the VDD_SD, it will cost about 10ms to see the voltage change from 3.3v to 0.5v. So at least need to dealy 11ms to make sure a clean power off and power on. Here add 12ms dealy. Signed-off-by: Haibo Chen --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 021caf471bf6..9921ea13ab48 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -76,6 +76,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; enable-active-high; }; };